Testing device

Abstract

The embodiment of the invention provides a testing device which comprises a testing board, the testing board comprises a fixing assembly, an electrical assembly and a control assembly, the fixing assembly is used for fixing the testing board on a mainboard, the mainboard comprises a power supply chip, the electrical assembly comprises a plurality of spring probes, and the spring probes are arranged on the testing board. The plurality of spring probes are connected with a plurality of signal pins of the power supply chip, and the plurality of spring probes are used for acquiring a plurality of to-be-tested signals of the power supply chip through the plurality of signal pins; and the control assembly is connected with the electrical assembly, and the control assembly is used for generating a test result according to the plurality of to-be-tested signals. According to the scheme, through the fixing assembly and the electrical assembly, the testing device can be quickly connected with the power supply chip on the mainboard, so that the testing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of servers, and in particular to a testing device. Background Art

[0002] The server is an important device in information application scenarios. Through the excellent computing power of the server, it can provide users with reliable computing services to improve user work efficiency.

[0003] In actual applications, the server is tested and optimized according to the test results to ensure that the server can provide stable computing services. The server test includes testing the components on the server motherboard. In the related art, the components on the motherboard are electrically connected to the test device by welding wires, so that the components on the motherboard are tested by the test device.

[0004] However, the welding process suffers from inefficiencies, which results in low testing efficiency. Summary of the invention

[0005] The embodiments of the present application provide a testing device to improve testing efficiency.

[0006] In a first aspect, an embodiment of the present application provides a testing device, comprising a testing board, wherein the testing board comprises: a fixing component, an electrical component, and a control component, wherein the fixing component is used to fix the testing board on a mainboard, and the mainboard comprises a power chip; the electrical component comprises a plurality of spring probes, and the plurality of spring probes are connected to a plurality of signal pins of the power chip, and the plurality of spring probes are used to obtain a plurality of test signals of the power chip through the plurality of signal pins; the control component is connected to the electrical component, and the control component is used to generate a test result according to the plurality of test signals.

[0007] In a possible embodiment, the fixing component includes: a positioning component and a fixing structure, wherein the positioning component is connected to a preset component of the mainboard, and the positioning component is used to align the electrical component with the power chip; the fixing structure is connected to the mainboard, and the fixing structure is used to fix the test board on the mainboard.

[0008] In a possible implementation, the test board further includes a fixture, wherein the fixture is clamped on the outside of the power chip, the size of the fixture is the same as the size of the power chip, and the fixture is used to fix the power chip.

[0009] In a possible implementation, the electrical component further includes a first communication interface, wherein the first communication interface is connected to a second communication interface of the mainboard, and the first communication interface is used to obtain an integrated circuit interconnect bus I2C signal of the power chip.

[0010] In a possible implementation manner, the first communication interface is a male interface, and the first communication interface is connected to the second communication interface via a female-female connection line.

[0011] In a possible implementation, the electrical component further includes a grounding interface, wherein the grounding interface is used to connect to a grounding connection point of the mainboard, and the grounding interface is used to perform differential measurement on the input voltage.

[0012] In a possible implementation, the electrical component further includes an output interface, wherein the output interface is connected to a load point on the mainboard via a load line, and the output interface is used to apply a load to the power chip so that the test device can test the test results of the power chip operating under multiple loads.

[0013] In a possible implementation, the test device further includes: a load machine, an oscilloscope, and a host computer, wherein the oscilloscope is connected to the output interface of the test board, and the oscilloscope is used to generate a waveform corresponding to the test result; the load machine is connected to the output interface of the test board, and the load machine is used to simulate a variety of loads; the host computer is connected to the oscilloscope and the load machine, and the host computer is used to control the loading mode of the load machine, the host computer is used to control the parameter adjustment and waveform access of the oscilloscope, the host computer is used to execute the test through automated program control, and the host computer is used to generate a test report based on the test result.

[0014] In a possible implementation, the test device further includes a DC power supply, wherein the DC power supply is connected to an output interface of the test board, and the DC power supply is used to provide an input voltage; the test board is connected to an input pin and an enable pin of the power supply chip, and the test board is used to provide an input voltage to the input pin and the enable pin, so that the test device tests the power-on timing and the power-off timing of the power supply chip; the host computer is connected to the DC power supply, and the host computer is used to control the input voltage of the DC power supply.

[0015] In a possible implementation manner, the test device further includes a cache component, wherein the cache component is connected to the control component, and the cache component is used to store the test result.

[0016] The test device provided in the embodiment of the present application includes a test board, and the test board includes: a fixing component, an electrical component, and a control component, wherein the fixing component is used to fix the test board on a mainboard, and the mainboard includes a power chip; the electrical component includes a plurality of spring probes, and the plurality of spring probes are connected to a plurality of signal pins of the power chip, and the plurality of spring probes are used to obtain a plurality of signals to be tested of the power chip through the plurality of signal pins; the control component is connected to the electrical component, and the control component is used to generate a test result according to the plurality of signals to be tested. The above scheme can quickly establish a connection between the test device and the power chip on the mainboard through the fixing component and the electrical component, thereby improving the efficiency of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an application scenario of a test device provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of a test process provided by an embodiment of the present application;

[0020] Figure 3 A schematic diagram of the structure of a fixing assembly provided in an embodiment of the present application;

[0021] Figure 4 A schematic diagram of the structure of a test board provided in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of the structure of a test board provided in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of the structure of a test board provided in an embodiment of the present application;

[0024] Figure 7 A schematic diagram of the structure of a test board provided in an embodiment of the present application;

[0025] Figure 8 A schematic diagram of the structure of a testing device provided in an embodiment of the present application;

[0026] Fig. 9 A schematic diagram of the structure of a testing device provided in an embodiment of the present application;

[0027] Fig.10 A schematic diagram of the structure of a testing device provided in an embodiment of the present application.

[0028] Description of reference numerals:

[0029] 1-test board; 12-fixed component; 121-positioning component; 122-fixed structure; 13-electrical component; 131-spring probe; 132-first communication interface; 133-ground interface; 134-output interface; 14-control component; 15-fixture; 2-oscilloscope; 3-load machine; 4-host computer; 5-DC power supply; 6-cache component.

[0030] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0031] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0032] It should be noted that the test device of the present application can be used in the field of server technology, and can also be used in any field other than servers, and the application field of the test device of the present application is not limited.

[0033] Figure 1 A schematic diagram of an application scenario of a test device provided in an embodiment of the present application is given as an example in combination with the scenario shown in the diagram: a server includes a mainboard, and the test device is connected to the mainboard. The test device can be used to test components on the mainboard to obtain test results.

[0034] For example, during the operation of the server, components on the mainboard may age or become damaged. By performing regular testing and processing, corresponding repairs can be performed on the faults so that the server can provide computing services normally.

[0035] Exemplarily, the mainboard includes a power chip, and a signal of the power chip is read by a testing device, and the signal is tested and processed to obtain a test result of the power chip.

[0036] In related technologies, testing the signal of the power chip requires wire bonding. Although the power chip is located on the front of the motherboard, some signals require the motherboard to be flipped over for wire bonding, which affects the test process. When welding wires and performing point testing on the motherboard at the same time, there is a risk of damaging the resistors, capacitors and power chips. Most importantly, the environment must be rebuilt for each test, which affects the test efficiency.

[0037] The testing device provided in this application is intended to solve the above technical problems in the prior art.

[0038] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0039] Figure 2 A schematic diagram of a test device provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the test board 1 includes: a fixing component 12, an electrical component 13, and a control component 14, wherein:

[0040] The fixing component 12 is used to fix the test board 1 on the main board, and the main board includes a power chip:

[0041] The electrical component 13 includes a plurality of spring probes 131, which are connected to a plurality of signal pins of the power chip, and are used to obtain a plurality of signals to be tested of the power chip through the plurality of signal pins;

[0042] The control component 14 is connected to the electrical component 13, and the control component 14 is used to generate a test result according to a plurality of signals to be tested.

[0043] Optionally, the power chip can be a point of load (POL) chip. A POL chip is a power management device specially designed for voltage regulation and power conversion close to a load (such as a CPU, GPU, FPGA, etc.). It is usually used in high-performance computing, communication equipment, servers, and other electronic systems that require efficient power management. On the server motherboard, the POL chip is used to provide a stable power supply.

[0044] Combined with the scenario example, the vibration generated during the test process may cause the test board 1 to be misaligned with the main board, resulting in poor pin contact or wear of main board components. Fixing the test board 1 to the main board by fixing the component 12 can avoid misalignment between the test board 1 and the main board, thereby improving the reliability of the test.

[0045] Exemplarily, the signal pin is used to transmit electrical signals related to the power chip, and the working information of the power chip can be obtained by testing the electrical signals.

[0046] Optionally, the electrical signal transmitted by the signal pin includes but is not limited to at least one of the following: input voltage (VIN), enable (EN), PGD (power good detect), drain-source voltage (VDS), or output voltage (VOUT), etc.

[0047] Combined with the scenario example, in the related art, the signal pin is connected to the test device by welding wire, which has the problem of low connection efficiency. In the present application, the spring probe 131 is in contact with the test device, which can quickly complete the connection of the test device, thereby improving the test efficiency.

[0048] Exemplarily, the control component 14 generates a test result according to a preset test logic.

[0049] Optionally, the control component 14 generates the test result through an internal microcontroller or embedded system, or the control component 14 obtains the test result by analyzing the signal to be tested through a software algorithm that may also be equipped.

[0050] Optionally, the control component 14 is connected to the electrical component 13 via an external lead, or the control component 14 is connected to the electrical component 13 via a circuit integrated in the test board 1 .

[0051] Based on the above implementation, the test device can be quickly connected to the power chip on the mainboard through the fixing component 12 and the electrical component 13, thereby improving the test efficiency.

[0052] A feasible implementation method is as follows: Figure 3 As shown, Figure 3 The fixing component 12 includes: a positioning component 121 and a fixing structure 122, wherein the positioning component 121 is connected to a preset component of the mainboard, and the positioning component 121 is used to align the electrical component 13 with the power chip; the fixing structure 122 is connected to the mainboard, and the fixing structure 122 is used to fix the test board 1 on the mainboard.

[0053] Optionally, the positioning component 121 is a pin or a through hole, and the alignment of the pin or the through hole with the corresponding position on the mainboard indicates that the electrical component 13 is aligned with the power chip.

[0054] Optional. The fixing structure 122 may be a screw or a clamp, etc. The fixing structure 122 prevents the relative positions of the test board 1 and the main board from changing.

[0055] In this feasible implementation, the electrical component 13 is aligned with the power chip by aligning the position through the positioning component 121 and fixing the test board 1 through the fixing structure 122, so that the electrical component 13 can accurately receive the corresponding electrical signal, thereby improving the accuracy of the test.

[0056] A feasible implementation method is as follows: Figure 4 As shown, Figure 4 The test board 1 also includes a fixture 15, wherein the fixture 15 is clamped on the outside of the power chip, the size of the fixture 15 is the same as the size of the power chip, and the fixture 15 is used to fix the power chip.

[0057] Optionally, the fixture 15 is a mechanical structure for fixing and positioning the power chip to ensure stability and accuracy during the test. Specifically, the fixture 15 fixes the power chip in a specific position through physical contact and ensures that it does not move or displace during the test.

[0058] Optionally, the fixture 15 or the surface of the fixture 15 is made of insulating material to prevent the metal material from generating a magnetic field that affects the operation of the power chip, thereby improving the accuracy of the test.

[0059] In combination with the scenario example, the size of the fixture 15 is the same as the size of the power chip, which means that the fixture 15 can fit closely to the outer contour of the power chip, thereby providing a good fixing effect.

[0060] Optionally, the fixture 15 has an adjustable part so as to provide a stable fixing effect on power chips of different sizes, thereby improving the versatility of the test device.

[0061] In this feasible implementation, the power chip is fixed by the fixture 15, and during the test process, there will be no poor contact or measurement error caused by the movement of the power chip, thereby improving the accuracy of the test.

[0062] A feasible implementation method is as follows: Figure 5 As shown, Figure 5 The electrical component 13 also includes a first communication interface 132, wherein the first communication interface 132 is connected to the second communication interface of the mainboard, and the first communication interface 132 is used to obtain the integrated circuit interconnection bus I2C signal of the power chip.

[0063] Optionally, the first communication interface 132 is connected to the electrical component 13 via a circuit integrated in the test board 1 .

[0064] For example, taking the POL chip as an example, the POL chip includes a POL chip that supports the Inter-Integrated Circuit (I2C) protocol and a POL chip that does not support the I2C protocol. The POL chip that supports the I2C protocol can be tested through the first communication interface 132.

[0065] Combined with the scenario example, the basic working status information of the power chip can be obtained by the test signals obtained by the multiple spring probes 131. Through the first communication interface 132, the I2C signal can be effectively obtained, and the status register and configuration parameters of the power chip can be obtained according to the I2C signal.

[0066] In this feasible implementation, acquiring the I2C signal through the first communication interface 132 can improve the richness of the test results, thereby improving the comprehensiveness of the test.

[0067] In a feasible implementation, the first communication interface 132 is a male interface, and the first communication interface 132 is connected to the second communication interface via a female-female connection line.

[0068] Exemplarily, the second communication interface may be brought out via a female-to-female connection cable.

[0069] Combined with the scenario example, during the whole machine process, the second communication interface may be blocked by other components on the mainboard, making it difficult to connect to the second communication interface. Leading out the second communication interface through a female-female connection line can reduce the difficulty of wiring and thus improve test efficiency.

[0070] A feasible implementation method is as follows: Figure 6 As shown, Figure 6 The electrical component 13 also includes a grounding interface 133, wherein the grounding interface 133 is used to connect to the grounding connection point of the mainboard, and the grounding interface 133 is used to perform differential measurement on the input voltage.

[0071] Optionally, the ground interface 133 is connected to the electrical component 13 via a circuit integrated in the test board 1 .

[0072] For example, by connecting the ground interface 133 to the ground connection point, the signal to be tested can have a common potential reference point, eliminate the potential difference caused by different ground paths, thereby improving the accuracy of the test, reducing electromagnetic interference and improving signal quality.

[0073] Illustratively, differential measurement is a high-precision measurement method that eliminates common-mode noise and interference by measuring the voltage difference between two signals. Since the ground interface 133 provides a stable ground potential reference point, differential measurement can be performed accurately.

[0074] Optionally, the input voltage (VIN) and the output voltage (VOUT) are differentially measured through a differential amplifier or a dedicated circuit to obtain the voltage difference to evaluate the efficiency and stability of the power chip.

[0075] In this feasible implementation, grounding is performed through the grounding interface 133, which can provide a unified potential reference point, thereby improving the accuracy of the test.

[0076] A feasible implementation method is as follows: Figure 7 As shown, Figure 7 The electrical component 13 also includes an output interface 134, wherein the output interface 134 is connected to a load point on the mainboard through a load line, and the output interface 134 is used to apply a load to the power chip so that the test device can test the test results of the power chip working under various loads.

[0077] Exemplarily, by applying a load to the power chip through the output interface 134 , different load conditions can be simulated, thereby comprehensively evaluating the performance of the power chip under different loads.

[0078] Exemplarily, the load line is responsible for transmitting the load current provided by the output interface 134 to the load point on the mainboard, ensuring that the load can be correctly applied to the power chip.

[0079] For example, a load point is a specific location on a motherboard, usually an output pin of a power chip or other key node that needs to be tested. The load point is used to receive and consume power provided by the power chip, simulating the load condition under actual working conditions.

[0080] In this feasible implementation, multiple load conditions are simulated through the output interface 134, so that the working performance of the power chip under different load conditions can be tested, thereby improving the comprehensiveness of the test.

[0081] In a feasible implementation, Figure 8 As shown, Figure 8 The schematic diagram of the structure of the test device is shown in FIG. The test device also includes: an oscilloscope 2, a load machine 3, and a host computer 4, wherein the oscilloscope 2 is connected to the output interface 134 of the test board 1, and the oscilloscope 2 is used to generate a waveform corresponding to the test result; the load machine 3 is connected to the output interface 134 of the test board 1, and the load machine 3 is used to simulate a variety of loads; the host computer 4 is connected to the oscilloscope 2 and the load machine 3, and the host computer 4 is used to control the load mode of the load machine 3, the host computer 4 is used to control the parameter adjustment and waveform access of the oscilloscope 2, the host computer 4 is used to execute the test through the automatic program control, and the host computer 4 is used to generate a test report according to the test result.

[0082] Exemplarily, the oscilloscope 2 is used to display the waveform of the electrical signal. The oscilloscope 2 is connected to the output interface 134 of the test board 1, and collects and displays the output waveform (e.g., output voltage waveform) of the power chip under different load conditions in real time. The oscilloscope 2 can analyze various parameters of the waveform, such as voltage ripple, rise time, fall time, or overshoot.

[0083] Exemplarily, the load machine 3 is used to simulate a variety of loads. The load machine 3 is connected to the output interface 134 of the test board 1, and can simulate different load conditions (such as constant load, dynamic load, or pulse load, etc.) as needed. The load machine 3 supports a variety of load modes (such as constant current mode, constant voltage mode, or constant power mode, etc.), and can accurately control the load current, voltage or power, etc.

[0084] Exemplarily, the host computer 4 can control the loading mode of the load machine 3 and set different load conditions through a software interface or an automated program. The host computer 4 can remotely adjust the parameters of the oscilloscope 2 (such as sampling rate, trigger conditions, etc.), and obtain and store the waveform data generated by the oscilloscope 2. The host computer 4 can realize automatic control of the entire test process by writing an automated script, such as loading different load conditions, recording waveform data, or generating a test report. The host computer 4 can automatically generate a detailed test report based on the collected data, such as various test indicators, abnormal conditions, or recommended measures.

[0085] Optionally, the automated test program may include: a measurement function measure2(), used to complete the setting of channel measurement items; a channel setting function tl1_channel_set(), used to complete the setting of the channel switch selection, horizontal position, label and trigger; a display function t2_win(), used to display a simple test interface, including the experiment name, measurement prompts, start test and end test buttons; a data recording and report generation module, used to automatically record test data and generate test reports, and save them to a specified path.

[0086] In this feasible implementation, through the oscilloscope 2, the load machine 3, and the host computer 4, the test board 1 can be automatically controlled to perform a full range of tests and automatically generate a test report, thereby improving the efficiency of the test.

[0087] In a feasible implementation, Fig. 9 As shown, Fig. 9 : is a structural diagram of the test device. The test device also includes a DC power supply 5, wherein the DC power supply 5 is connected to the output interface 134 of the test board 1, and the DC power supply 5 is used to provide an input voltage; the test board 1 is connected to the input pin and the enable pin of the power chip, and the test board 1 is used to provide an input voltage to the input pin and the enable pin, so that the test device tests the power-on timing and power-off timing of the power chip; the host computer 4 is connected to the DC power supply 5, and the host computer 4 is used to control the input voltage of the DC power supply 5.

[0088] Exemplarily, the DC power supply 5 is used to provide a stable DC voltage. The DC power supply 5 provides the required input voltage to the input pin of the power chip through the output interface 134 of the test board 1. The DC power supply 5 usually has adjustable voltage and current output functions, allowing testing under different conditions.

[0089] Exemplarily, the test board 1 is connected to the input pin and the enable pin of the power chip to ensure that the input voltage and the enable signal can be correctly transmitted to the power chip. The test board 1 provides the required power to the input pin of the power chip through the input voltage provided by the DC power supply 5. The test board 1 can start or shut down the working state of the power chip by controlling the enable pin, thereby testing its power-on and power-off timing.

[0090] Optionally, the host computer 4 controls the input voltage of the DC power supply 5 through a software interface or an automation program to simulate different input voltage conditions. The host computer 4 can write an automation script to realize automatic control of the entire test process, such as loading different input voltages, recording waveform data, or generating a test report. The host computer 4 can obtain the power-on and power-off timing waveforms of the power chip through the oscilloscope 2, and analyze them to ensure that they meet the design specifications.

[0091] In this feasible implementation, by automatically simulating different input voltages through the DC power supply 5, the stability of the power chip in various application scenarios can be automatically tested, thereby improving the efficiency of the test.

[0092] A feasible implementation method is as follows: Fig.10 As shown, Fig.10 The test device further comprises a cache component 6, wherein the cache component 6 is connected to the control component 14, and the cache component 6 is used to store the test results.

[0093] Optionally, the cache component 6 is used to temporarily store the test results until a preset condition is met, and all the test results stored in the cache component 6 are sent to the host computer 4.

[0094] Optionally, the preset condition may be that a preset period is reached, or the test results stored in the cache component 6 reach a preset size.

[0095] In this feasible implementation, the cache component 6 provides an additional data storage layer. Even if the main storage device fails, some or all test results may still be retained in the cache component 6, reducing the risk of data loss, thereby improving the reliability of the test.

[0096] It should be understood that the above-mentioned device embodiments are only illustrative, and the device of the present application can also be implemented in other ways. For example, the division of units / modules in the above-mentioned embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0097] In addition, unless otherwise specified, each functional unit / module in each embodiment of the present application may be integrated into one unit / module, each unit / module may exist physically separately, or two or more units / modules may be integrated together. The above-mentioned integrated unit / module may be implemented in the form of hardware or in the form of a software program module.

[0098] If the integrated unit / module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. The processor may be any appropriate hardware processor, such as CPU, GPU, FPGA, DSP, and ASIC, etc. The storage unit may be any appropriate magnetic storage medium or magneto-optical storage medium, such as Resistive Random Access Memory (RRAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.

[0099] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0100] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0102] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A testing device, characterized in that: The test board includes a fixing component, an electrical component, and a control component, wherein: The fixing assembly is used to fix the test board on the main board, and the main board includes a power chip: The electrical component includes a plurality of spring probes, the plurality of spring probes are connected to a plurality of signal pins of the power chip, and the plurality of spring probes are used to obtain a plurality of signals to be tested of the power chip through the plurality of signal pins; The control component is connected to the electrical component, and the control component is used to generate a test result according to the multiple signals to be tested.

2. The testing device according to claim 1, characterized in that: The fixing assembly includes: a positioning assembly and a fixing structure, wherein: The positioning component is connected to a preset component of the mainboard, and the positioning component is used to align the electrical component with the power chip; The fixing structure is connected to the main board, and is used to fix the test board on the main board.

3. The testing device according to claim 1, characterized in that: The test board also includes a fixture, wherein: The jig is clamped on the outside of the power chip, the size of the jig is the same as the size of the power chip, and the jig is used to fix the power chip.

4. The testing device according to claim 1, characterized in that: The electrical component further comprises a first communication interface, wherein The first communication interface is connected to the second communication interface of the mainboard, and the first communication interface is used to obtain an integrated circuit interconnect bus I2C signal of the power chip.

5. The testing device according to claim 4, characterized in that: The first communication interface is a male interface, and the first communication interface is connected to the second communication interface via a female-female connection line.

6. The testing device according to claim 1, characterized in that: The electrical component also includes a grounding interface, wherein The grounding interface is used to connect to the grounding connection point of the mainboard, and the grounding interface is used to perform differential measurement on the input voltage.

7. The testing device according to claim 1, characterized in that: The electrical component also includes an output interface, wherein: The output interface is connected to the load point on the mainboard via a load line, and the output interface is used to apply a load to the power chip so that the test device can test the test results of the power chip working under various loads.

8. The testing device according to claim 7, characterized in that: The test device also includes: an oscilloscope, a load machine, and a host computer, wherein: The oscilloscope is connected to the output interface of the test board, and the oscilloscope is used to generate a waveform corresponding to the test result; The load machine is connected to the output interface of the test board, and the load machine is used to simulate multiple loads; The host computer is connected to the oscilloscope and the load machine. The host computer is used to control the loading mode of the load machine, the host computer is used to control the parameter adjustment and waveform access of the oscilloscope, the host computer is used to execute the test through automated program control, and the host computer is used to generate a test report based on the test results.

9. The testing device according to claim 8, characterized in that: The testing device also includes a DC power supply, wherein: The DC power supply is connected to the output interface of the test board, and the DC power supply is used to provide an input voltage; The test board is connected to the input pin and the enable pin of the power chip, and the test board is used to provide input voltage to the input pin and the enable pin, so that the test device tests the power-on timing and the power-off timing of the power chip; The host computer is connected to the DC power supply, and is used to control the input voltage of the DC power supply.

10. The testing device according to claim 1, characterized in that: The test device also includes a cache component, wherein: The cache component is connected to the control component, and the cache component is used to store the test result.

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