A method for controlling the uniformity of silicon oxide thickness on a large surface area
By etching metal deposition grooves on the waveguide substrate and filling them with silicon oxide cladding, combined with photoresist layer and etching treatment, the problem of controlling silicon oxide thickness uniformity in large-area modulation areas is solved, thereby improving device performance and yield.
Patent Information
- Application Number
- CN202510124217.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-26
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2045-01-26
AI Technical Summary
Existing technologies make it difficult to precisely control the uniformity of silicon oxide thickness within large-area modulation regions, resulting in low yield of heterogeneous integration of lithium niobate and waveguide substrates, affecting device performance.
A metal deposition groove is etched on the waveguide substrate and filled with a silicon oxide cladding. A protective structure is formed through a photoresist layer as a mask for etching and chemical mechanical polishing. Two flattening processes are performed to control the uniformity of the silicon oxide thickness.
Precise control of silicon oxide thickness in large-area modulation regions is achieved, which improves device performance and product yield and meets device design requirements.
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Figure CN119828364B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electro-optical modulators, and in particular to a method for controlling the thickness uniformity of silicon oxide on a large surface area. Background Art
[0002] At present, the development of fields such as autonomous driving, remote interactive applications, and 3D virtual games has led to a rapid increase in the demand for high-bandwidth optical communications. Electro-optical modulators are key components in optical communications, which modulate optical signals through electric current to load information. Lithium niobate materials have been widely used due to their excellent electro-optical effect and high optical transparency. Lithium niobate materials and waveguide substrates can be heterogeneously integrated through bonding and other processes. In order to achieve good modulation performance, the silicon oxide thickness (i.e., spacing) between lithium niobate and the waveguide needs to be precisely controlled to 100nm±10nm. How to control the uniformity of silicon oxide thickness in a large modulation area (mm level) is a key issue.
[0003] Existing technology solutions grow silicon oxide on a waveguide substrate with grooves for metal electrodes, then perform chemical mechanical polishing (CMP) on the waveguide substrate to flatten the waveguide substrate and achieve the required thickness (100±10nm). However, due to the grooved metal structure and the large modulation area (mm-scale), the silicon oxide surface obtained by chemical mechanical polishing on the waveguide substrate surface has large surface fluctuations. Therefore, it is impossible to accurately control the silicon oxide thickness uniformity within the large modulation area (mm-scale), which cannot meet current device design requirements. It also reduces the yield of subsequent heterogeneous integration of lithium niobate materials and waveguide substrates, affecting device performance. Summary of the Invention
[0004] In view of this, an embodiment of the present application provides a method for controlling the uniformity of silicon oxide thickness on a large surface area, so as to achieve precise control of the uniformity of silicon oxide thickness on a large surface area, thereby improving device performance and product yield.
[0005] The present application provides the following technical solution: a method for controlling the uniformity of silicon oxide thickness on a large surface area, comprising:
[0006] Etching a metal deposition groove on a waveguide substrate, forming a metal electrode in the metal deposition groove, and filling the metal deposition groove with a silicon oxide cladding layer to cover the metal electrode with the silicon oxide cladding layer;
[0007] forming a first photoresist layer on the concavo-convex surface formed by the surface of the waveguide substrate and the surface of the silicon oxide cladding layer, and patterning the first photoresist layer so that the patterned first photoresist layer forms a protective structure above the gap between the metal electrode and the wall of the metal deposition tank;
[0008] Using the protection structure as a mask, the concave-convex surface is patterned by etching to perform a first planarization process on the concave-convex surface;
[0009] The protective structure is removed, and the concave-convex surface is subjected to a second flattening process to obtain a processed waveguide device.
[0010] According to one embodiment of the present application, the method further includes: forming a first silicon oxide layer on a silicon substrate, forming a patterned waveguide structure on the first silicon oxide layer, and covering the waveguide structure with a second silicon oxide layer to obtain the waveguide substrate.
[0011] According to an embodiment of the present application, the first silicon oxide layer is prepared by thermal oxidation, and the second silicon oxide layer is prepared by chemical vapor deposition.
[0012] According to one embodiment of the present application, forming a metal electrode in the metal deposition tank includes:
[0013] forming a metal electrode layer to cover the surface of the metal deposition tank and the surface of the waveguide substrate through the metal electrode layer, and forming a patterned second photoresist layer on the metal electrode layer in the metal deposition tank;
[0014] The metal electrode layer is patterned by dry etching using the second photoresist layer as a mask, and then the second photoresist layer is removed to form the metal electrode in the metal deposition tank.
[0015] According to one embodiment of the present application, the outermost width of the protective structure is greater than the width of the gap between the metal electrode and the wall of the metal deposition tank, so that the protective structure completely covers the gap.
[0016] According to an embodiment of the present application, the upper surface of the protective structure is a plane, and the lower surface of the protective structure is adapted to the corresponding position of the concave-convex surface.
[0017] According to an embodiment of the present application, the second planarization process adopts chemical mechanical polishing.
[0018] According to one embodiment of the present application, the metal deposition grooves are located on both sides of the waveguide structure, and the bottoms of the metal deposition grooves extend into the first silicon oxide layer.
[0019] According to one embodiment of the present application, the thickness of the metal electrode does not exceed the groove depth of the metal deposition groove, and the top of the metal electrode is not higher than the top of the waveguide structure.
[0020] According to an embodiment of the present application, the thickness of the metal electrode is 0.8-1 μm, and the groove depth of the metal deposition groove is 1.5-2 μm.
[0021] Compared with the prior art, the beneficial effects achieved by at least one of the above technical solutions adopted in the embodiments of this specification include at least the following: the embodiments of the present invention etch a metal deposition groove on a waveguide substrate, form a metal electrode in the metal deposition groove, and fill the metal deposition groove with a silicon oxide cladding layer to cover the metal electrode with the silicon oxide cladding layer; form a first photoresist layer on the concave-convex surface formed by the surface of the waveguide substrate and the surface of the silicon oxide cladding layer, and pattern the first photoresist layer so that the patterned first photoresist layer forms a protective structure above the gap between the metal electrode and the groove wall of the metal deposition groove; use the protective structure as a mask to pattern the concave-convex surface by etching to perform a first flattening treatment on the concave-convex surface; remove the protective structure, and then perform a second flattening treatment on the concave-convex surface to obtain a processed waveguide device. By adding a mask etching process, the large height difference of the non-uniform surface is reduced, so that the large-scale modulation area reaches a preliminary flat state, and then chemical mechanical polishing is performed so that the silicon oxide thickness on the substrate surface meets the device requirements. The embodiment of the present invention adopts a chemical mechanical polishing treatment scheme after mask etching, which can enable a large-area modulation area (mm level) to obtain a flat surface that meets the design requirements (100±10nm), so that the modulation performance of the silicon photonic platform can achieve the best effect, while providing a uniform surface for subsequent processes and improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0023] Figure 1 1. It is a flow chart of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;
[0024] Figure 2 This is a first structural diagram of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;
[0025] Figure 3 This is a second structural diagram of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;
[0026] Figure 4This is a third structural diagram of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;
[0027] Figure 5 This is a fourth structural diagram of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;
[0028] Figure 6 This is a fifth structural diagram of a method for controlling the uniformity of silicon oxide thickness on a large surface area according to an embodiment of the present invention;
[0029] Among them, 10 is a silicon substrate, 11 is a thermal oxide silicon layer, 12 is a silicon nitride waveguide layer, 13 is a chemical vapor deposition silicon oxide layer, 14 is a metal deposition tank, 15 is a metal electrode, and 16 is a protection structure. DETAILED DESCRIPTION
[0030] The embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0031] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.
[0032] like Figure 1 As shown, an embodiment of the present invention provides a method for controlling the uniformity of silicon oxide thickness on a large surface area, comprising:
[0033] 101. Etching a metal deposition groove on a waveguide substrate, forming a metal electrode in the metal deposition groove, and filling the metal deposition groove with a silicon oxide cladding layer so as to cover the metal electrode with the silicon oxide cladding layer;
[0034] 102. Forming a first photoresist layer on the concavo-convex surface formed by the surface of the waveguide substrate and the surface of the silicon oxide cladding layer, and patterning the first photoresist layer so that the patterned first photoresist layer forms a protective structure above the gap between the metal electrode and the wall of the metal deposition tank;
[0035] 103. Using the protection structure as a mask, patterning the concave-convex surface by etching to perform a first planarization process on the concave-convex surface;
[0036] 104. Remove the protective structure, and then perform a second flattening treatment on the concave-convex surface to obtain a processed waveguide device.
[0037] In order to obtain a flat surface that meets the design requirements (100±10nm) in a large-area modulation region (mm level) and to precisely control the uniformity of silicon oxide thickness on a large-area surface, an embodiment of the present invention spin-coats a first photoresist layer on the surface of a waveguide substrate that has not been flattened. After mask exposure, the required protective structure is formed to protect the relatively low trench area between the metal electrode and the metal deposition tank; the concave and convex surface of the unprotected area is then etched to reduce the height difference between the steps of the concave and convex surface, while reducing the amount of subsequent chemical mechanical polishing, so that the surface is initially flat, that is, the first flattening treatment is performed. Finally, chemical mechanical polishing is performed after removing the protective structure, that is, the second flattening treatment is performed to obtain a flat surface that meets the design requirements (100±10nm). The embodiment of the present invention reduces the large height difference of the non-uniform surface by adding a mask etching process, so that the large-scale modulation area reaches a preliminary flat state, and then chemical mechanical polishing is performed to make the silicon oxide thickness on the substrate surface meet the device requirements. The embodiment of the present invention adopts a two-step planarization process, that is, a chemical mechanical polishing process followed by mask etching, which can enable a large-area modulation area (mm level) to obtain a flat surface that meets the design requirements (100±10nm), so that the modulation performance of the silicon photonic platform can achieve the best effect, while providing a uniform surface for subsequent processes and improving product yield.
[0038] In some embodiments of the present invention, the method further comprises: forming a first silicon oxide layer on a silicon substrate, forming a patterned waveguide structure on the first silicon oxide layer, and covering the waveguide structure with a second silicon oxide layer to obtain the waveguide substrate. The first silicon oxide layer is a silicon oxide layer prepared by thermal oxidation, and the second silicon oxide layer is a silicon oxide layer prepared by chemical vapor deposition. The two silicon oxide layers are non-isotropic thin film structures, with a silicon nitride waveguide structure in between: the first silicon oxide layer is prepared by thermal oxidation, which has the best density and film quality, and can be used as a lower silicon oxide layer to grow a silicon nitride thin film layer with good crystalline quality to optimize optical performance; after the silicon nitride thin film layer is grown, it is impossible to continue to prepare silicon oxide by thermal oxidation, so a chemical vapor deposition method is used to prepare an upper cladding silicon oxide layer to form a second silicon oxide layer. The film quality is slightly worse than that of the first silicon oxide layer, but it can be used as a cladding to protect the silicon nitride waveguide structure.
[0039] In specific implementation, the thickness of the first silicon oxide layer is 3-8 μm, the thickness of the silicon nitride waveguide structure layer is 50-450 nm, and the thickness of the second silicon oxide layer is 500 nm-1 um. The specific dimensions of the three are determined according to current design conditions and process windows.
[0040] In some embodiments of the present invention, a metal electrode is formed in the metal deposition tank, including: forming a metal electrode layer to cover the surface of the metal deposition tank and the surface of the waveguide substrate through the metal electrode layer, and forming a patterned second photoresist layer on the metal electrode layer in the metal deposition tank; using the second photoresist layer as a mask, patterning the metal electrode layer by dry etching, and then removing the second photoresist layer to form the metal electrode in the metal deposition tank.
[0041] In some embodiments of the present invention, the outermost width of the protective structure is greater than the width of the gap between the metal electrode and the wall of the metal deposition tank, so that the protective structure completely covers the gap. Furthermore, the upper surface of the protective structure is flat, and the lower surface of the protective structure is adapted to the corresponding position of the concave-convex surface.
[0042] During specific implementation, the shape and size of the protective structure are determined according to the groove size of the metal deposition tank and the size of the metal electrode. The protective structure uses a layer of photoresist to protect the trench structure between the metal electrode and the metal deposition tank, that is, in the subsequent etching process, the lowest position of the silicon oxide on the concave and convex surface is protected. By controlling the etching depth, the entire concave and convex surface is made as flat as possible before the CMP process is performed to further polish the wafer surface to improve the flattening effect of the silicon oxide surface.
[0043] In some embodiments of the present invention, the metal deposition tank is located on both sides of the waveguide structure, and the bottom of the metal deposition tank extends into the first silicon oxide layer. In specific implementation, the metal electrode layer can be made of materials such as Al and Cu, the thickness of the metal electrode does not exceed the depth of the metal deposition tank, and the top of the metal electrode must not be higher than the top of the waveguide structure. The gap between the top of the metal electrode and the top of the waveguide structure is controlled to be 0-100nm. The reason is that after the metal electrode structure is prepared, it needs to be covered with a silicon oxide cladding layer and subjected to two flattening processes. The second silicon oxide layer is controlled to be 100nm higher than the silicon nitride waveguide layer to optimize the optical performance and prepare for the subsequent bonding process. If the metal electrode is higher than the waveguide structure layer, there is not enough process window to control the requirement of 100nm silicon oxide thickness on the silicon nitride waveguide layer, which affects the optical performance. It may also cause damage to the metal electrode during the flattening process, thereby affecting the electrical performance.
[0044] In specific implementation, the groove depth of the metal deposition groove is 1.5-2μm, which is determined by the final thickness of the second silicon oxide layer; the thickness of the metal electrode is 0.8-1μm, so that the top of the metal electrode is lower than the top of the silicon nitride waveguide structure to prevent subsequent CMP process and bonding process from causing damage to the electrode.
[0045] like Figure 2-Figure 6 As shown, this embodiment proposes a solution of first performing mask etching on a large area of uneven surface and then performing chemical mechanical polishing to obtain the required thickness uniformity and precision. The following is a detailed description of the process steps of the embodiment of the present invention using a Si3N4 waveguide substrate as an example (unless otherwise specified, all schematic diagrams are cross-sectional views):
[0046] First, a silicon nitride waveguide substrate is prepared, including a waveguide structure and a metal electrode structure, and the substrate is not planarized. Figure 2 As shown, the silicon nitride waveguide substrate includes a silicon substrate 10, a thermal oxide silicon layer 11, a silicon nitride waveguide layer 12, and a chemical vapor deposited silicon oxide layer 13 formed in sequence from bottom to top; a metal deposition groove 14 is etched on the silicon nitride waveguide substrate, a metal electrode 15 is formed in the metal deposition groove 14, and a silicon oxide cladding is filled in the metal deposition groove 14 to cover the metal electrode 15.
[0047] Next, a photoresist is spin-coated on the concave-convex surface formed by the surface of the silicon nitride waveguide substrate and the surface of the silicon oxide cladding layer, and then a mask is exposed to form the required protection structure 16 to protect the relatively low trench area between the metal electrode and the deep trench, such as Figure 3 shown.
[0048] Again, using the protection structure 16 as a mask, the uneven surface of the unprotected area, i.e., the silicon oxide layer, is etched to reduce the height difference between the steps of the uneven surface and reduce the amount of subsequent chemical mechanical polishing, so that the surface is initially flat. Figure 4 As shown. Again, remove the photoresist, as shown Figure 5 shown.
[0049] Finally, the silicon nitride waveguide substrate is subjected to chemical mechanical polishing to flatten the surface to meet device performance requirements.
[0050] The embodiment of the present invention adopts two flattening processes, namely, first performing a mask etching process to reduce the large height differences of the non-uniform surface, so that the large-area modulation area reaches a preliminary flat state, and then performing chemical mechanical polishing treatment. This can enable the large-area modulation area (mm level) to obtain a flat surface that meets the design requirements (100±10nm), so that the modulation performance of the silicon photonic platform can achieve the best effect, while providing a uniform surface for subsequent processes and improving product yield.
[0051] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A method for controlling the uniformity of silicon oxide thickness on a large surface area, characterized in that: include: Etching a metal deposition groove on a waveguide substrate, forming a metal electrode in the metal deposition groove, and filling the metal deposition groove with a silicon oxide cladding layer to cover the metal electrode with the silicon oxide cladding layer; forming a first photoresist layer on the concavo-convex surface formed by the surface of the waveguide substrate and the surface of the silicon oxide cladding layer, and patterning the first photoresist layer so that the patterned first photoresist layer forms a protective structure above the gap between the metal electrode and the wall of the metal deposition tank; Using the protection structure as a mask, the concave-convex surface is patterned by etching to perform a first planarization process on the concave-convex surface; removing the protective structure, and then performing a second planarization process on the concave-convex surface to obtain a processed waveguide device; The method further includes: forming a first silicon oxide layer on the silicon substrate, forming a patterned waveguide structure on the first silicon oxide layer, and covering the waveguide structure with a second silicon oxide layer to obtain the waveguide substrate.
2. The method for controlling the thickness uniformity of silicon oxide on a large surface area according to claim 1, wherein: The first silicon oxide layer is prepared by thermal oxidation, and the second silicon oxide layer is prepared by chemical vapor deposition.
3. The method for controlling the thickness uniformity of silicon oxide on a large surface area according to claim 1, wherein: Forming a metal electrode in the metal deposition tank, comprising: forming a metal electrode layer to cover the surface of the metal deposition tank and the surface of the waveguide substrate through the metal electrode layer, and forming a patterned second photoresist layer on the metal electrode layer in the metal deposition tank; The metal electrode layer is patterned by dry etching using the second photoresist layer as a mask, and then the second photoresist layer is removed to form the metal electrode in the metal deposition tank.
4. The method for controlling the thickness uniformity of silicon oxide on a large surface area according to claim 1, wherein: The outermost width of the protection structure is greater than the width of the gap between the metal electrode and the wall of the metal deposition tank, so that the protection structure completely covers the gap.
5. The method for controlling the thickness uniformity of silicon oxide on a large surface area according to claim 1, wherein: The upper surface of the protection structure is a plane, and the lower surface of the protection structure is adapted to the corresponding position of the concave-convex surface.
6. The method for controlling the thickness uniformity of silicon oxide on a large surface area according to claim 1, wherein: The second planarization process adopts chemical mechanical polishing.
7. The method for controlling the thickness uniformity of silicon oxide on a large surface area according to claim 1, wherein: The metal deposition grooves are located on both sides of the waveguide structure, and the bottoms of the metal deposition grooves extend into the first silicon oxide layer.
8. The method for controlling the thickness uniformity of silicon oxide on a large surface area according to claim 1, wherein: The thickness of the metal electrode does not exceed the depth of the metal deposition tank, and the top of the metal electrode is not higher than the top of the waveguide structure.
9. The method for controlling the thickness uniformity of silicon oxide on a large surface area according to claim 1, wherein: The thickness of the metal electrode is 0.8-1 μm, and the depth of the metal deposition groove is 1.5-2 μm.