Composite waveguide structure and preparation method thereof

Abstract

The invention provides a composite waveguide structure and a preparation method thereof, and belongs to the technical field of electro-optical modulators, the composite waveguide structure comprises a first waveguide wafer and a waveguide film, the first waveguide wafer comprises a first substrate, a passivation layer, a first waveguide structure and metal electrodes, the first waveguide structure and the metal electrodes are arranged in the passivation layer, and the metal electrodes are arranged on the two sides of the first waveguide structure. The upper side of the first waveguide structure is covered with a first waveguide cladding, and the upper side of the metal electrode is provided with a first bonding pad hole; the waveguide film comprises a second substrate, a buried oxide layer arranged on the second substrate and a second waveguide structure arranged on the upper side of the buried oxide layer, second bonding pad holes are formed in the two sides of the second waveguide structure, the upper side of the second waveguide structure is covered with a second waveguide wrapping layer, the second waveguide wrapping layer is bonded with the first waveguide wrapping layer, and the second waveguide wrapping layer is bonded with the second substrate. The position of the second waveguide structure corresponds to the position of the first waveguide structure, and the position of the second bonding pad hole corresponds to the position of the first bonding pad hole. According to the invention, the compatibility between a W2W heterogeneous integration mode and a CMOS technology is improved.

Description

Technical Field

[0001] The present application relates to the technical field of electro-optic modulators, and in particular to a composite waveguide structure and a method for preparing the same. Background Art

[0002] Optical communications, radio frequency photonic systems, millimeter wave measuring instruments and other equipment using optical devices have increasingly higher requirements for bandwidth. In semiconductor photonic modulators, the limitation of electron carrier transmission time fundamentally affects the high-frequency working characteristics of diode-based electro-optic modulators (EOM), which has aroused great interest in the research of materials with high-frequency electro-optic modulation characteristics. Lithium niobate (LN) has attracted extensive attention in integrated optics due to its superior electro-optical and nonlinear optical properties. Its Mach-Zehnder modulators (MZM) heterogeneously integrated with silicon or silicon nitride waveguides have been proven to achieve very high modulation bandwidths and can support high-frequency modulation far exceeding 100 GHz.

[0003] The processing method of this electro-optic modulator is preferably compatible with the traditional CMOS process used in silicon photonic devices, so as to obtain higher performance, lower cost and better manufacturing scalability. For the electro-optic modulation (composite waveguide) structure composed of thin-film lithium niobate and silicon nitride, it can usually be realized by die-to-wafer (D2W) or wafer-to-wafer (W2W) bonding.

[0004] The process of processing LN-SiNx composite waveguide by W2W bonding usually involves LN, metal electrode photolithography, thin film preparation and other front-end processes, which makes it incompatible with CMOS process, and the LN processing process depends on the processing process of SiNx waveguide chip, which limits the flexibility of LN process processing and reduces process efficiency. In fact, the processing method of making metal electrode (Al) under SiNx to form a buried electrode structure, and then combining the single chip cut and diced by LN with SiNx waveguide wafer or single SiNx waveguide chip by D2W or D2D bonding can solve the problem of CMOS process incompatibility, but it will face greater risks and challenges in the Si substrate removal process of LN, such as for D2W method: ① There is a risk of LN chip falling off during Si grinding, ② When wet etching residual Si after grinding, the etching solution has a risk of damaging SiNx waveguide devices, etc.; for D2D method, dry etching is usually used to remove Si substrate, which is also incompatible with CMOS process and not suitable for batch processing. Summary of the invention

[0005] In view of this, an embodiment of the present application provides a composite waveguide structure and a method for preparing the same, which at least partially solves the problem that the process flow in the prior art is incompatible with the CMOS process and has low process efficiency.

[0006] In a first aspect, an embodiment of the present application provides a composite waveguide structure, comprising a first waveguide wafer and a waveguide film bonded to the first waveguide wafer, wherein the first waveguide wafer comprises a first substrate, a passivation layer arranged on the first substrate, and a first waveguide structure and a metal electrode arranged in the passivation layer, the metal electrodes are arranged on both sides of the first waveguide structure, the upper side of the first waveguide structure is covered with a first waveguide cladding, and a first pad hole is arranged on the upper side of the metal electrode; the waveguide film comprises a second substrate, a buried oxide layer arranged on the second substrate, and a second waveguide structure arranged on the upper side of the buried oxide layer, second pad holes are arranged on both sides of the second waveguide structure, the upper side of the second waveguide structure is covered with a second waveguide cladding, the second waveguide cladding is bonded to the first waveguide cladding, the position of the second waveguide structure corresponds to the position of the first waveguide structure, and the position of the second pad hole corresponds to the position of the first pad hole.

[0007] In a second aspect, an embodiment of the present application further provides a method for preparing a composite waveguide structure, for preparing the composite waveguide structure as described in the first aspect, the method comprising:

[0008] Sequentially preparing a metal electrode and a first waveguide structure on the passivation layer of the first substrate, wherein the metal electrodes are arranged on both sides of the first waveguide structure;

[0009] Preparing and planarizing a first waveguide cladding for the first waveguide structure;

[0010] Opening a hole above the metal electrode to form a first pad hole to obtain a first waveguide wafer;

[0011] preparing an electro-optic material substrate wafer, wherein the electro-optic material substrate wafer comprises a second substrate, a buried oxide layer and an electro-optic material film arranged in layers;

[0012] Patterning the electro-optical material film to form a second waveguide structure, and making the position of the second waveguide structure correspond to the position of the first waveguide structure through layout design;

[0013] preparing and planarizing a second waveguide cladding for the second waveguide structure;

[0014] The second waveguide cladding layer and the buried oxide layer are opened to form a second pad hole, and the position of the second pad hole is made to correspond to the position of the first pad hole through layout design to obtain a second waveguide wafer;

[0015] bonding the first waveguide wafer to the second waveguide wafer through the first waveguide cladding and the second waveguide cladding;

[0016] The second substrate is removed.

[0017] According to a specific implementation of the embodiment of the present application, the step of sequentially preparing a metal electrode and a first waveguide structure on a passivation layer of a first substrate includes:

[0018] depositing a first passivation layer on the first substrate;

[0019] depositing a metal film on the first passivation layer;

[0020] Patterning the metal film through a patterning process to form the metal electrode;

[0021] Depositing a second passivation layer and planarizing it, and depositing a Si Nx film on the second passivation layer;

[0022] The Si Nx film is processed by a patterning process to form the first waveguide structure.

[0023] According to a specific implementation of the embodiment of the present application, the step of preparing and flattening the first waveguide cladding of the first waveguide structure includes:

[0024] Depositing the first waveguide cladding based on a CVD process;

[0025] A planarization process is performed through a chemical mechanical polishing process, so that the thickness of the first waveguide cladding layer above the first waveguide structure is reduced to a first preset thickness.

[0026] According to a specific implementation of the embodiment of the present application, the step of opening a hole above the metal electrode to form a first pad hole includes:

[0027] The second passivation layer and the first waveguide cladding layer above the metal electrode are opened by dry etching to form the first pad hole.

[0028] According to a specific implementation of the embodiment of the present application, patterning the electro-optical material film to form a second waveguide structure includes:

[0029] The electro-optic material film is patterned by a dry etching process of inductively coupled plasma-reactive ion etching to form the second waveguide structure.

[0030] According to a specific implementation of the embodiment of the present application, the preparing and flattening the second waveguide cladding of the second waveguide structure includes:

[0031] Depositing the second waveguide cladding layer based on a CVD process;

[0032] A chemical mechanical polishing process is used to perform a planarization process, so that the thickness of the second waveguide cladding layer above the second waveguide structure is reduced to a second preset thickness.

[0033] According to a specific implementation manner of the embodiment of the present application, the sum of the first preset thickness and the second preset thickness is less than 150 nm.

[0034] According to a specific implementation of the embodiment of the present application, bonding the first waveguide wafer to the second waveguide wafer includes:

[0035] sequentially cleaning and plasma activating the first waveguide wafer and the second waveguide wafer;

[0036] Aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonded device;

[0037] The pre-bonded device is annealed to complete the bonding.

[0038] According to a specific implementation of the embodiment of the present application, removing the second substrate includes:

[0039] The second substrate is removed by grinding or chemical mechanical polishing.

[0040] Beneficial effects:

[0041] The composite waveguide structure and preparation method thereof in the embodiments of the present application, according to the W2W bonding alignment relationship, indirectly align the pad windows on the first waveguide wafer and the second waveguide wafer through layout design, so that no front-end process processing such as photolithography etching and thin film preparation is required after W2W, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process; fully utilizing the flexibility advantage of independent processing of the first waveguide wafer and the second waveguide wafer, improving the process structure compatibility between the bonding area and the non-bonding area, such as the waveguide cladding thickness between the LN-Si Nx layers in the bonding area and the Si Nx waveguide cladding thickness in the non-bonding area can be differentiated according to design requirements.

[0042] In addition, compared with the D2W bonding method, the present application reduces the risk of LN chip falling off during the removal of the Si substrate of LN, and can directly remove the Si substrate through chemical mechanical polishing, avoiding the problems of low processing efficiency and damage to SiNx waveguide devices caused by wet etching, while simplifying the process flow; compared with the D2W bonding method, the LN chip size of the present application can be smaller, thereby improving the integration of the optical chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 is a schematic diagram of a composite waveguide structure according to an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of a process for preparing a composite waveguide structure according to an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of preparing a first passivation layer according to an embodiment of the present invention;

[0047] Figure 4 A schematic diagram of preparing a metal electrode according to an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of preparing a second passivation layer according to an embodiment of the present invention;

[0049] Figure 6 A schematic diagram of a Si Nx waveguide structure prepared according to an embodiment of the present invention;

[0050] Figure 7 A schematic diagram of preparing a first waveguide cladding according to an embodiment of the present invention;

[0051] Figure 8 A schematic diagram of preparing a first pad hole according to an embodiment of the present invention;

[0052] Fig. 9 A schematic diagram of preparing an electro-optical material substrate wafer according to an embodiment of the present invention;

[0053] Fig.10 A schematic diagram of preparing an LN waveguide structure according to an embodiment of the present invention;

[0054] Fig.11 A schematic diagram of preparing a second waveguide cladding according to an embodiment of the present invention;

[0055] Fig.12 A schematic diagram of preparing a second pad hole according to an embodiment of the present invention;

[0056] Fig.13 FIG. 4 is a schematic diagram of bonding a first waveguide wafer and a second waveguide wafer according to an embodiment of the present invention.

[0057] In the figure: 1. first substrate; 2. silicon dioxide film; 3. metal electrode; 4. first waveguide structure; 5. first pad hole; 6. electro-optical material film; 7. second substrate; 8. buried oxide layer; 9. second waveguide structure; 10. second pad hole. DETAILED DESCRIPTION

[0058] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0059] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0060] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0061] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0062] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0063] In a first aspect, the present application provides a composite waveguide structure, referring to Figure 1The composite waveguide structure includes a first waveguide wafer and a waveguide film bonded to the first waveguide wafer, wherein the first waveguide wafer includes a first substrate 1, a passivation layer arranged on the first substrate 1, and a first waveguide structure 4 and a metal electrode 3 arranged in the passivation layer, the metal electrodes 3 are arranged on both sides of the first waveguide structure 4, the upper side of the first waveguide structure 4 is covered with a first waveguide cladding, and a first pad hole 5 is arranged on the upper side of the metal electrode 3; the waveguide film includes a second substrate 7, a buried oxide layer 8 arranged on the second substrate 7, and a second waveguide structure 9 arranged on the upper side of the buried oxide layer 8, second pad holes 10 are arranged on both sides of the second waveguide structure 9, the upper side of the second waveguide structure 9 is covered with a second waveguide cladding, the second waveguide cladding is bonded to the first waveguide cladding, the position of the second waveguide structure 9 corresponds to the position of the first waveguide structure 4, and the position of the second pad hole 10 corresponds to the position of the first pad hole 5.

[0064] In a specific implementation, the waveguide film bonded to the first waveguide wafer can be a film formed by removing the second substrate from the second waveguide wafer. For example, the first waveguide wafer can be set as a SiNx waveguide wafer, and for example, the second waveguide wafer can be set as a LN waveguide wafer.

[0065] In this embodiment, the upper and lower pad holes are set correspondingly. During actual preparation, indirect alignment can be performed through photolithography layout design, so that W2W does not require front-end processing such as photolithography etching and thin film preparation, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process.

[0066] Second, refer to Figure 2 The present application also provides a method for preparing a composite waveguide structure, which is used to prepare the composite waveguide structure as described in the first aspect, and the method comprises the following steps:

[0067] Step S101, preparing a metal electrode 3 and a first waveguide structure 4 in sequence on a passivation layer of a first substrate 1, wherein the metal electrodes 3 are arranged on both sides of the first waveguide structure 4;

[0068] Step S102, preparing and planarizing a first waveguide cladding layer on the first waveguide structure 4;

[0069] Step S103, opening a hole above the metal electrode 3 to form a first pad hole 5 to obtain a first waveguide wafer;

[0070] Step S104, preparing an electro-optical material substrate wafer, wherein the electro-optical material substrate wafer comprises a second substrate 7, a buried oxide layer 8 and an electro-optical material film 6 which are stacked;

[0071] Step S105, patterning the electro-optical material film 6 to form a second waveguide structure 9, and making the position of the second waveguide structure 9 correspond to the position of the first waveguide structure 4 through layout design;

[0072] Step S106, preparing and planarizing a second waveguide cladding layer for the second waveguide structure 9;

[0073] Step S107, opening the second waveguide cladding layer and the buried oxide layer 8 to form a second pad hole 10, and making the position of the second pad hole 10 correspond to the position of the first pad hole 5 through layout design, so as to obtain a second waveguide wafer;

[0074] Step S108, bonding the first waveguide wafer to the second waveguide wafer, and bonding the first waveguide cladding to the second waveguide cladding;

[0075] Step S109, removing the second substrate 7.

[0076] In a specific implementation, the structure after removing the second substrate 7 from the second waveguide wafer is a waveguide film bonded to the first waveguide wafer. In practical applications, the first waveguide wafer, for example, can be set as a SiNx waveguide wafer, and the first waveguide structure is a SiNx waveguide structure. The second waveguide wafer, for example, can be set as an LN waveguide wafer, and the second waveguide structure is an LN waveguide structure.

[0077] In this embodiment, according to the W2W bonding alignment relationship, the pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through layout design, so that the W2W does not require front-end processing such as photolithography, etching, and thin film preparation, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process; the flexibility advantage of independent processing of the first waveguide wafer and the second waveguide wafer is fully utilized, and the process structure compatibility between the bonding area and the non-bonding area is improved. For example, the waveguide cladding thickness between the LN-SiNx layers in the bonding area and the SiNx waveguide cladding thickness in the non-bonding area can be differentiated according to design requirements.

[0078] In addition, compared with the D2W bonding method, the present application reduces the risk of LN chip falling off during the removal of the Si substrate of LN, and can directly remove the Si substrate through chemical mechanical polishing, avoiding the problems of low processing efficiency and damage to SiNx waveguide devices caused by wet etching, while simplifying the process flow; compared with the D2W bonding method, the LN chip size of the present application can be smaller, thereby improving the integration of the optical chip.

[0079] During specific implementation, the first substrate 1 and the second substrate 7 may be set as silicon substrates.

[0080] In one embodiment, referring to Figures 3 to 6The step of sequentially preparing a metal electrode 3 and a first waveguide structure 4 on the passivation layer of the first substrate 1 comprises:

[0081] A first passivation layer is deposited on the first substrate 1, such as Figure 3 As shown;

[0082] depositing a metal film on the first passivation layer;

[0083] The metal film is processed by a patterning process to form the metal electrode 3, such as Figure 4 As shown;

[0084] Deposit a second passivation layer and planarize it, such as Figure 5 As shown, a SiNx film is deposited on the second passivation layer;

[0085] The SiNx film is processed by a patterning process to form the first waveguide structure 4, as shown in FIG. Figure 6 shown.

[0086] During specific implementation, the patterning process may adopt processes such as photolithography and etching.

[0087] In a specific implementation, the first passivation layer and the second passivation layer can be respectively set as a silicon dioxide film 2. The specific preparation process of the metal electrode 3 and the first waveguide structure 4 includes:

[0088] First, a silicon dioxide film 2 is prepared on a silicon substrate, including: preparing a silicon dioxide film 2 with a thickness of 1 to 8 μm on a Si substrate by CVD or thermal oxidation growth;

[0089] The metal electrode 3 is prepared, specifically including: PVD deposition of a metal film with a thickness of 0.5 to 1.5 μm; and then forming a lead electrode structure through a patterning process such as photolithography and etching;

[0090] The second passivation layer is prepared and planarized: silicon dioxide is deposited by CVD, and then planarized by CMP until the thickness of the silicon dioxide film 2 above the metal electrode 3 is 200 to 500 nm;

[0091] SiNx film preparation and waveguide patterning: CVD deposits a SiNx film with a thickness of 100 to 500 nm and a refractive index of 1.9 to 2.2, and then forms the first waveguide structure 4 through patterning processes such as photolithography and etching.

[0092] In one embodiment, the step of preparing and planarizing the first waveguide cladding of the first waveguide structure 4 includes:

[0093] Depositing the first waveguide cladding based on a CVD process;

[0094] A planarization process is performed by a chemical mechanical polishing process, so that the thickness of the first waveguide cladding layer above the first waveguide structure 4 is reduced to a first preset thickness h1.

[0095] In a specific implementation, the first waveguide cladding is configured as a silicon dioxide film 2 , that is, the first passivation layer, the second passivation layer and the first waveguide cladding can all be configured as a silicon dioxide film 2 .

[0096] In one embodiment, the step of opening a hole above the metal electrode 3 to form the first pad hole 5 includes:

[0097] The second passivation layer and the first waveguide cladding layer above the metal electrode 3 are opened by dry etching to form the first pad hole 5 .

[0098] In specific implementation, the operation of opening a hole above the metal electrode 3 is called pad opening, and the metal pad can be exposed by dry etching of silicon dioxide. Generally, at least two first pad holes 5 are provided, for example, Figure 8 As shown in the figure, two first pad holes 5 are provided. In the actual process, the number of holes can be adjusted according to the requirements.

[0099] In specific implementation, the processing process of the first waveguide wafer in the above embodiment can be compatible with the CMOS process, thereby improving the CMOS process compatibility of the W2W heterogeneous integration method.

[0100] The processing of the second waveguide wafer is described in detail below. The processing of the second waveguide wafer can be carried out by using an external dedicated line in a CMOS process environment. For details, please refer to the following embodiment.

[0101] In the specific implementation, the electro-optical material substrate wafer is set as a thin film LN substrate wafer, which is a commercially mature thin film LN substrate, wherein the electro-optical material film 6 is an LN film with a thickness of 100nm to 500nm. The Smart-cut process is used for preparation, which is a process technology that forms a damage layer by ion implantation of bulk LN and annealing at 200 to 300°C, and then splits and falls off along the damage layer. The second substrate 7 is a Si substrate, wherein the thickness of the buried oxide layer 8 is 0.1 to 2μm, and the buried oxide layer 8 is a SiO2 film prepared by thermal oxidation growth. The specific structure of the thin film LN substrate wafer is referred to Fig. 9 .

[0102] In one embodiment, referring to Fig.10 The electro-optical material film 6 is patterned to form a second waveguide structure 9, comprising:

[0103] The electro-optic material film 6 is patterned by a dry etching process of inductively coupled plasma-reactive ion etching to form the second waveguide structure 9 .

[0104] In the specific implementation, the electro-optic material film 6 is etched by inductively coupled plasma-reactive ion etching to form the second waveguide structure 9. It should be noted that when performing the patterned photolithography layout design of this step, the position of the second waveguide structure 9 needs to be determined according to the flip alignment relationship of the subsequent W2W bonding with the first waveguide wafer, so as to achieve indirect alignment of the second waveguide structure 9 with the first waveguide structure 4 on the layout.

[0105] In one embodiment, referring to Fig.11 The step of preparing and flattening the second waveguide cladding of the second waveguide structure 9 comprises:

[0106] Depositing the second waveguide cladding layer based on a CVD process;

[0107] A planarization process is performed through a chemical mechanical polishing process, so that the thickness of the second waveguide cladding layer above the second waveguide structure 9 is reduced to a second preset thickness.

[0108] In specific implementation, the second waveguide cladding can be set to a SiO2 film, which is deposited by CVD and flattened by CMP until the thickness of the SiO2 film above the second waveguide structure 9 reaches a second preset thickness h2, and satisfies h1+h2<150nm, wherein h1 is the first preset thickness of the first waveguide cladding above the first waveguide structure 4 after the first waveguide cladding is flattened.

[0109] In one embodiment, the sum of the first preset thickness and the second preset thickness is less than 150 nm.

[0110] In one embodiment, for the formation of the second pad hole 10, refer to Fig.12 , dry-etch the second waveguide cladding and buried oxide layer 8 onto the Si substrate. The second pad hole 10 in this step needs to be indirectly aligned with the pad window on the first waveguide wafer according to the W2W bonding alignment relationship during the photolithography layout design.

[0111] In the above embodiment, the second waveguide wafer processing is realized. According to the W2W bonding alignment relationship, the pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through layout design, so that W2W does not require front-end processing such as photolithography etching and thin film preparation, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process.

[0112] The processing process of the LN-Si Nx composite waveguide is described in detail below, specifically including the following contents.

[0113] In one embodiment, referring to Fig.13 , bonding the first waveguide wafer to the second waveguide wafer, comprising:

[0114] sequentially cleaning and plasma activating the first waveguide wafer and the second waveguide wafer;

[0115] Aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonded device;

[0116] The pre-bonded device is annealed to complete the bonding.

[0117] In a specific implementation, the bonding strength can be improved by annealing. The temperature during annealing can be set to be less than 250°C. The second waveguide wafer is combined with the first waveguide wafer. Fig.13 The first pad hole 5 above the metal electrode 3 corresponds to the position of the second pad holes 10 on both sides of the second waveguide structure 9, and the second waveguide structure 9 corresponds to the first waveguide structure 4 in the bonding area.

[0118] In one embodiment, removing the second substrate 7 comprises:

[0119] The second substrate 7 is removed by grinding or chemical mechanical polishing. The structure after removing the second substrate 7 is shown in FIG. Figure 1 shown.

[0120] In this embodiment, compared with the D2W bonding method, the risk of LN chip falling off is reduced during the removal of the Si substrate of the second waveguide wafer, and the Si substrate can be directly removed by CMP, avoiding the problems of low processing efficiency and damage to SiNx waveguide devices caused by wet etching, while simplifying the process flow. In addition, compared with the D2W bonding method, the size of the LN chip can be smaller, which improves the integration of the optical chip.

[0121] In the embodiment provided by the present invention, according to the W2W bonding alignment relationship, the pad windows on the first waveguide wafer and the second waveguide wafer are indirectly aligned through layout design, so that the W2W does not require front-end processing such as photolithography etching and thin film preparation, thereby improving the compatibility of the W2W heterogeneous integration method with the CMOS process; the flexibility advantage of independent processing of the first waveguide wafer and the second waveguide wafer is fully utilized, and the process structure compatibility of the bonding area and the non-bonding area is improved. For example, the waveguide cladding thickness between the LN-SiNx layers in the bonding area and the Si Nx waveguide cladding thickness in the non-bonding area can be differentiated according to design requirements.

[0122] In addition, compared with the D2W bonding method, the present application reduces the risk of LN chip falling off during the removal of the Si substrate of LN, and can directly remove the Si substrate through chemical mechanical polishing, avoiding the problems of low processing efficiency and damage to SiNx waveguide devices caused by wet etching, while simplifying the process flow; compared with the D2W bonding method, the LN chip size of the present application can be smaller, thereby improving the integration of the optical chip.

[0123] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A composite waveguide structure, characterized in that: The invention comprises a first waveguide wafer and a waveguide film bonded to the first waveguide wafer, wherein the first waveguide wafer comprises a first substrate (1), a passivation layer arranged on the first substrate (1), and a first waveguide structure (4) and a metal electrode (3) arranged in the passivation layer, the metal electrodes (3) being arranged on both sides of the first waveguide structure (4), the upper side of the first waveguide structure (4) being covered with a first waveguide cladding, and the upper side of the metal electrode (3) being provided with a first pad hole (5); the waveguide film comprises a second substrate (7), a passivation layer arranged on the first substrate (1), and a first waveguide structure (4) and a metal electrode (3) arranged in the passivation layer. A buried oxide layer (8) is disposed on the second substrate (7) and a second waveguide structure (9) is disposed on the upper side of the buried oxide layer (8), second pad holes (10) are disposed on both sides of the second waveguide structure (9), the upper side of the second waveguide structure (9) is covered with a second waveguide cladding, the second waveguide cladding is bonded to the first waveguide cladding, the position of the second waveguide structure (9) corresponds to the position of the first waveguide structure (4), and the position of the second pad hole (10) corresponds to the position of the first pad hole (5).

2. A method for preparing a composite waveguide structure, for preparing the composite waveguide structure as claimed in claim 1, characterized in that: The method comprises: A metal electrode (3) and a first waveguide structure (4) are sequentially prepared on the passivation layer of the first substrate (1), wherein the metal electrodes (3) are arranged on both sides of the first waveguide structure (4); Preparing and flattening a first waveguide cladding layer on the first waveguide structure (4); Opening a hole above the metal electrode (3) to form a first pad hole (5) to obtain a first waveguide wafer; Prepare an electro-optical material substrate wafer, the electro-optical material substrate wafer comprising a stacked second substrate (7), a buried oxide layer (8) and an electro-optical material film (6); Patterning the electro-optical material film (6) to form a second waveguide structure (9), and making the position of the second waveguide structure (9) correspond to the position of the first waveguide structure (4) through layout design; Preparing and flattening a second waveguide cladding layer on the second waveguide structure (9); The second waveguide cladding layer and the buried oxide layer (8) are opened to form a second pad hole (10), and the position of the second pad hole (10) is made to correspond to the position of the first pad hole (5) through layout design, so as to obtain a second waveguide wafer; bonding the first waveguide wafer to the second waveguide wafer through the first waveguide cladding and the second waveguide cladding; The second substrate (7) is removed.

3. The method for preparing a composite waveguide structure according to claim 1, characterized in that: The method of sequentially preparing a metal electrode (3) and a first waveguide structure (4) on a passivation layer of a first substrate (1) comprises: Depositing a first passivation layer on the first substrate (1); depositing a metal film on the first passivation layer; Processing the metal film through a patterning process to form the metal electrode (3); Depositing a second passivation layer and planarizing it, and depositing a SiNx film on the second passivation layer; The SiNx film is patterned by a patterning process to form the first waveguide structure (4).

4. The method for preparing a composite waveguide structure according to claim 1, characterized in that: The step of preparing and flattening the first waveguide cladding of the first waveguide structure (4) comprises: Depositing the first waveguide cladding based on a CVD process; A planarization process is performed through a chemical mechanical polishing process, so that the thickness of the first waveguide cladding layer above the first waveguide structure (4) is reduced to a first preset thickness.

5. The method for preparing a composite waveguide structure according to claim 3, characterized in that: The step of opening a hole above the metal electrode (3) to form a first pad hole (5) comprises: The second passivation layer and the first waveguide cladding layer above the metal electrode (3) are opened by dry etching to form the first pad hole (5).

6. The method for preparing a composite waveguide structure according to claim 1, characterized in that: The step of patterning the electro-optical material film (6) to form a second waveguide structure (9) comprises: The electro-optical material film (6) is patterned by a dry etching process of inductively coupled plasma-reactive ion etching to form the second waveguide structure (9).

7. The method for preparing a composite waveguide structure according to claim 4, characterized in that: The step of preparing and flattening the second waveguide cladding of the second waveguide structure (9) comprises: Depositing the second waveguide cladding layer based on a CVD process; A planarization process is performed through a chemical mechanical polishing process, so that the thickness of the second waveguide cladding layer above the second waveguide structure (9) is reduced to a second preset thickness.

8. The method for preparing a composite waveguide structure according to claim 7, characterized in that: The sum of the first preset thickness and the second preset thickness is less than 150 nm.

9. The method for preparing a composite waveguide structure according to claim 1, characterized in that: The step of bonding the first waveguide wafer to the second waveguide wafer comprises: sequentially cleaning and plasma activating the first waveguide wafer and the second waveguide wafer; Aligning the first waveguide wafer and the second waveguide wafer for pre-bonding to obtain a pre-bonded device; The pre-bonded device is annealed to complete the bonding.

10. The method for preparing a composite waveguide structure according to claim 1, characterized in that: The removing of the second substrate (7) comprises: The second substrate (7) is removed by grinding or chemical mechanical polishing.

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