Display substrate and display panel

Abstract

The invention discloses a display substrate and a display panel. The display substrate is provided with a display area and a frame area, the frame area surrounds the periphery of the display area and comprises a first area and a second area, the second area is located on the side, away from the display area, of the first area, the display substrate comprises a substrate and a driving circuit, and the driving circuit is located on one side of the substrate and located in the first area; the driving circuit comprises a first wire, a second wire and a connecting wire, the first wire, the second wire and the connecting wire are sequentially stacked in the direction away from the substrate, and an insulating layer is arranged between any two adjacent wires; the connecting wire is electrically connected with the first wire and the second wire through a via hole formed in the insulating layer; the display substrate further comprises a protection structure which is located on one side of the substrate and located in the second area, and the protection structure and the connecting wires are made of the same material and arranged on the same layer. The display substrate can weaken or avoid electrochemical corrosion of water vapor to the connecting wires at the via holes, and ensures effective switching of the connecting wires at the via holes to signals.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and specifically relate to a display substrate and a display panel. Background Art

[0002] LCD (Liquid Crystal Display) has attracted widespread attention for its rich colors, small size, light weight, easy to carry, low radiation, environmental health, low power consumption, energy saving and environmental protection, high stability, long service life, large viewing angle, good viewing experience, powerful splicing function, and diverse application scenarios. Summary of the invention

[0003] In a first aspect, an embodiment of the present disclosure provides a display substrate having a display area and a frame area, wherein the frame area surrounds the periphery of the display area, the frame area includes a first area and a second area, the second area is located on a side of the first area away from the display area,

[0004] The display substrate comprises a base and a driving circuit, wherein the driving circuit is located on one side of the base and in the first area;

[0005] The driving circuit includes a first routing line, a second routing line and a connecting routing line, wherein the first routing line, the second routing line and the connecting routing line are sequentially stacked in a direction away from the substrate, and an insulating layer is provided between any two adjacent ones;

[0006] The connecting wire electrically connects the first wire and the second wire through a via hole provided in the insulating layer;

[0007] The display substrate further comprises a protection structure, which is located on one side of the base and in the second area. The protection structure and the connection wiring are made of the same material and are arranged in the same layer.

[0008] In some embodiments, the protection structure includes a plurality of protection lines, the plurality of protection lines respectively surround the display area, and the plurality of protection lines are arranged in sequence in a direction away from the display area.

[0009] In some embodiments, the protection structure includes a plurality of protection blocks, and the plurality of protection blocks are distributed around the display area.

[0010] In a direction away from the display area, there are at least two circles of the protection block;

[0011] The positions of the protection blocks in two adjacent circles are staggered.

[0012] In some embodiments, the frame area includes a first side frame, a second side frame, a third side frame and a binding side frame, the first side frame is opposite to the binding side frame, and the second side frame is opposite to the third side frame;

[0013] The protective structure is distributed on the first side frame, the second side frame and the third side frame.

[0014] In some embodiments, at least part of the insulating layer further extends to the second region.

[0015] At least some of the protection structures are located at different distances from the substrate.

[0016] In some embodiments, it further includes a ground line located in the first area, and the orthographic projection of the ground line on the substrate is located between the orthographic projection of the protection structure and the driving circuit on the substrate;

[0017] Along a direction away from the display area, a portion of the protection structure close to the ground line is electrically connected to the ground line.

[0018] In some embodiments, the first routing line includes a plurality of clock signal lines, and the plurality of clock signal lines are arranged in sequence in a direction away from the display area;

[0019] Of any two adjacent clock signal lines, the length of the clock signal line closer to the display area is shorter than the length of the clock signal line farther from the display area;

[0020] The driving circuit also includes a plurality of electrode blocks, which are made of the same material and arranged on the same layer as the connecting wiring.

[0021] The plurality of electrode blocks correspond to the plurality of clock signal lines one by one, and the orthographic projections of the corresponding electrode blocks and the clock signal lines on the substrate at least partially overlap;

[0022] Among any two adjacent electrode blocks along the direction away from the display area, the overlapping area of ​​the orthographic projections of the electrode block closer to the display area and the clock signal line on the substrate is larger than the overlapping area of ​​the orthographic projections of the electrode block farther from the display area and the clock signal line on the substrate.

[0023] In some embodiments, orthographic projections of the electrode block and the via hole on the substrate do not overlap.

[0024] In some embodiments, the drive circuit includes a gate drive circuit;

[0025] The connecting wires are made of transparent metal oxide material.

[0026] In a second aspect, an embodiment of the present disclosure provides a display panel, comprising the above-mentioned display substrate.

[0027] The display substrate provided by the embodiment of the present disclosure, by arranging a protective structure in the second area, and the protective structure and the connecting wiring are made of the same material and arranged in the same layer, can make the protective structure closer to the outer edge of the frame area than the connecting wiring at the via hole. When water vapor invades from the outside of the frame area, it can preferentially react electrochemically with the protective structure located in the second area, thereby reducing or avoiding electrochemical corrosion of the connecting wiring at the via hole by water vapor, thereby ensuring effective signal transfer of the connecting wiring at the via hole, and ultimately ensuring normal display of the display substrate; at the same time, when a large electrostatic voltage accumulates at the outer edge of the frame area, the protective structure located in the second area can preferentially guide and accommodate the electrostatic voltage, thereby reducing the interference and damage of the electrostatic voltage to the driving circuit in the first area and the circuit in the display area, thereby protecting the circuits in the first area and the display area, and further ensuring normal display of the display substrate.

[0028] The display panel provided by the embodiment of the present disclosure can avoid corrosion and damage to the internal circuit of the display panel caused by water vapor intrusion by adopting the above-mentioned display substrate, and can also avoid interference and damage to the internal circuit of the display panel caused by electrostatic voltage, thereby ensuring the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0030] Figure 1a The figure is a schematic diagram of a 6Mask process flow of an array substrate in an LCD display panel in the related art.

[0031] Figure 1b The figure is a schematic diagram of the preparation of the transfer hole in the border area of ​​the display panel in the related art.

[0032] Figure 1c It is a top view schematic diagram of a part of the circuit in the border area of ​​a display panel in the related art.

[0033] Figure 1d It is a cross-sectional schematic diagram of a border area of ​​a display panel in the related art.

[0034] Figure 1e This is a photo of the 2ITO layer at the transfer hole in the frame area of ​​the display panel corroded by water vapor in the related art;

[0035] Figure 2aIt is a schematic top view of the structure of a display substrate in an embodiment of the present disclosure.

[0036] Figure 2b FIG. 1 is a schematic top view of the structure of another display substrate in an embodiment of the present disclosure.

[0037] Figure 2c It is a partial cross-sectional schematic diagram showing the border area of ​​the substrate in the embodiment of the present disclosure.

[0038] Figure 2d It is a partially enlarged top view schematic diagram showing the border area of ​​the substrate in the embodiment of the present disclosure.

[0039] Figure 3a It is a top view schematic diagram showing the distribution of clock signal lines in the border area of ​​the substrate in the embodiment of the present disclosure.

[0040] Figure 3b It is a top view schematic diagram showing the distribution of clock signal lines in the border area of ​​the substrate in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the technical solution of the embodiments of the present disclosure, a display substrate and a display panel provided by the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0042] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as being limited to the embodiments set forth in the present disclosure. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0043] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions, but are not intended to be limiting.

[0044] In the reliability evaluation of LCD display products, water vapor prevention is an important evaluation indicator. The intrusion of water vapor can easily cause metal corrosion and thus affect signal transmission during the display process, resulting in poor display.

[0045] Reference Figure 1aTaking the 6Mask process production of the array substrate in the LCD display panel as an example, the top conductive film layer of the array substrate is the 2ITO layer 5, which acts as the conductive layer of the transfer hole between different layers of metal wiring in the frame area of ​​the display panel. In the quality evaluation system of LCD display panels, 8585 (85°C, 85% humidity) and 6090 (60°C, 90% humidity) are often used to simulate the display state after long-term daily use of the display screen. In this evaluation, the 2ITO layer 5 often undergoes electrochemical reaction with the intruding water vapor and is corroded, resulting in the failure of the transfer hole signal transfer, which in turn causes poor display of the LCD display panel.

[0046] Reference Figure 1a and Figure 1b , Figure 1a This is the typical process flow chart of 6Mask array substrate. Figure 1a The diagram shows the formation process of pixels in the display area of ​​the array substrate, in which each process involves film deposition, exposure, development and etching. The first deposited film layer is the Gate layer (such as the gate line layer) 6, which is mainly used for switching signal transmission when the pixel is displayed; then an insulating layer (such as the gate line layer) is deposited. Figure 1b PVX1 layer 7 in the film); then deposit, expose, develop and etch the active layer 8; then sequentially carry out the process flow of 1ITO layer 9, SD layer 10, PVX2 layer 11 and 2ITO layer 5. The process flow of these subsequent film layers is the same as that of the previous film layers and will not be repeated. Figure 1b In the process flow of the PVX2 layer 11 in 6Mask, the insulating layer will be etched. In the case where there is no SD layer 10 protection above the PVX1 layer 7, the PVX1 layer 7 will also be etched away.

[0047] Reference Figure 1b , Figure 1c and Figure 1d The border area of ​​the display panel is mainly distributed with GOA circuits (shift register circuits, responsible for generating Gate signals for opening each row of pixels in the display area) 12. Figure 1a Taking the typical 6Mask process flow as an example, the signal line in the Gate layer 6 of the GOA circuit 12 is on the same layer as the signal line in the Gate layer in the display area, and the signal line in the SD layer 10 of the GOA circuit 12 is on the same layer as the signal line in the SD layer in the display area. Some of the signal lines in the Gate layer 6 of the GOA circuit 12 need to be connected to some of the signal lines in the SD layer 10 through the transfer hole 13 and the 2ITO layer 5 above it. For example, the clock signal line in the Gate layer 6 of the GOA circuit 12 needs to be connected to the thin film transistor circuit in the SD layer 10 of the GOA circuit 12 through the transfer hole 13 and the 2ITO layer 5 above it.

[0048] In the related art, refer to Figure 1e , the array substrate and the color film substrate need to go through a series of processes such as box alignment to form a complete display panel. Figure 1c and Figure 1d , the 2ITO layer 5 of the array substrate frame area 101 is covered with a sealant 14 for sealing the array substrate and the color film substrate. External water vapor easily intrudes from the contact surface between the sealant 14 and the array substrate, and reacts electrochemically with the 2ITO layer 5 at the transfer hole 13 (when there is a low voltage signal on the 2ITO layer 5 at the transfer hole 13), so that the 2ITO layer 5 is severely corroded. Among them, the mechanism of corrosion of the 2ITO layer 5 by intruding water vapor is as follows: in a high temperature and high humidity environment, water vapor slowly penetrates into the display panel frame area 101, causing the 2ITO layer 5 that absorbs water vapor to gradually undergo electrochemical corrosion: when there is a low voltage signal on the 2ITO layer 5, the reaction formula of its electrochemical corrosion is: In2O3+3H2O+6e - →2In+4OH - ; 2ITO layer 5 is corroded and reduced to white single substance In (indium). In severe cases, 2ITO layer 5 is completely corroded.

[0049] At present, the common means to improve or avoid electrochemical corrosion of the 2ITO layer 5 at the transfer hole 13 is to increase the number of transfer holes 13, or to make the transfer hole 13 as far away from the outer edge of the display panel frame area 101 as possible. In addition, a conventional LCD display panel is usually provided with an electrostatic ring or grounding wire 4 on the outer side of its frame area. In order to improve the electrostatic protection capability of the electrostatic ring or grounding wire 4, the line width of the electrostatic ring or grounding wire 4 is usually set to be larger.

[0050] With the development of narrow-border technology for display panels, the above-mentioned solution of preventing water vapor intrusion and corrosion of the 2ITO layer 5 at the transfer hole 13 in the display panel border area 101 and the electrostatic protection solution often conflict with the demand for a narrow border. Currently, most designs are based on a trade-off between the narrow border and the water vapor intrusion that causes corrosion of the 2ITO layer 5 at the transfer hole 13, and between the narrow border and the improvement of electrostatic protection capabilities.

[0051] In order to solve the above problems in the related art, in a first aspect, the present embodiment provides a display substrate, referring to Figure 2a , Figure 2b , Figure 2c and Figure 2d, wherein the display substrate has a display area 100 and a frame area 101, the frame area 101 surrounds the periphery of the display area 100, the frame area 101 includes a first area 101A and a second area 101B, the second area 101B is located on a side of the first area 101A away from the display area 100, the display substrate includes a substrate 1 and a driving circuit 2, the driving circuit 2 is located on one side of the substrate 1 and is located in the first area 101A; the driving circuit 2 includes a first routing line 21, a second routing line 22 and a connecting routing line 23, the first routing line 21, the second routing line 22 and the connecting routing line 23 are sequentially stacked in a direction away from the substrate 1, and an insulating layer 24 is arranged between any two adjacent ones; the connecting routing line 23 is electrically connected to the first routing line 21 and the second routing line 22 through a via 240 opened in the insulating layer 24; the display substrate also includes a protective structure 3, which is located on one side of the substrate 1 and is located in the second area 101B, and the protective structure 3 and the connecting routing line 23 are made of the same material and are arranged on the same layer.

[0052] Among them, the protection structure 3 and the connecting wiring 23 are arranged on the same layer, which means that the protection structure 3 and the connecting wiring 23 are prepared simultaneously through a single patterning process. In the display substrate, the protection structure 3 and the connecting wiring 23 can be located on the surface of the same film layer or on the surfaces of different film layers, that is, the protection structure 3 and the connecting wiring 23 can be located on planes at the same height or on planes at different heights.

[0053] By arranging the protection structure 3 in the second area 101B, and the protection structure 3 and the connecting wiring 23 are made of the same material and arranged in the same layer, the protection structure 3 can be closer to the outer edge of the frame area 101 than the connecting wiring 23 at the via 240. When water vapor invades from the outside of the frame area 101, it can preferentially react electrochemically with the protection structure 3 located in the second area 101B, thereby reducing or avoiding the electrochemical corrosion of the connecting wiring 23 at the via 240 by water vapor, thereby ensuring the effective transfer of the signal by the connecting wiring 23 at the via 240, and finally ensuring the normal display of the display substrate; at the same time, when a large electrostatic voltage accumulates at the outer edge of the frame area 101, the protection structure 3 located in the second area 101B can preferentially guide and accommodate the electrostatic voltage, thereby reducing the interference and damage of the electrostatic voltage to the driving circuit 2 in the first area 101A and the circuit in the display area 100, thereby protecting the circuits in the first area 101A and the display area 100, and further ensuring the normal display of the display substrate.

[0054] In some embodiments, reference Figure 2a and Figure 2cThe protection structure 3 includes a plurality of protection lines 30, which surround the display area 100 respectively, and are arranged in sequence in a direction away from the display area 100. In this way, the plurality of protection lines 30 can form multiple consumption and blocking for the water vapor invading from the outside of the frame area 101, thereby forming multiple protection for the connection line 23 at the via hole 240, and further weakening or avoiding the electrochemical corrosion of the connection line 23 at the via hole 240 by water vapor.

[0055] In some embodiments, each protection line 30 may be a continuous and uninterrupted line, or a discontinuous and interrupted line.

[0056] In some embodiments, reference Figure 2b and Figure 2c The protection structure 3 includes a plurality of protection blocks 31, which are distributed around the display area 100. In the direction away from the display area 100, there are at least two circles of protection blocks 31; the positions of two adjacent circles of protection blocks 31 are staggered. In this way, at least two circles of protection blocks 31 can form multiple consumption and blocking of water vapor invading from the outside of the frame area 101, thereby forming multiple protections for the connection wiring 23 at the via hole 240, and further weakening or avoiding electrochemical corrosion of the connection wiring 23 at the via hole 240 by water vapor.

[0057] In some embodiments, the orthographic projection shape of the protection block 31 on the substrate 1 can be any shape such as a rectangle, a circle, an ellipse, a polygon, etc., as long as the protection block 31 can consume and block the invading water vapor.

[0058] In some embodiments, the frame area 101 includes a first side frame 101c, a second side frame 101d, a third side frame 101e and a binding side frame 101f, the first side frame 101c and the binding side frame 101f are opposite, and the second side frame 101d and the third side frame 101e are opposite; the protective structure 3 is distributed on the first side frame 101c, the second side frame 101d and the third side frame 101e. The binding side frame 101f is distributed with various circuit traces for binding and connecting with the peripheral circuit board. Since the binding side frame 101f is not provided with a transfer via, and the binding side frame 101f does not need to be packaged by a sealing glue, there is no need to set a protective structure 3 on the binding side frame 101f.

[0059] In some embodiments, reference Figure 2a Each protection line 30 extends from the second side frame 101d to the first side frame 101c and the third side frame 101e, forming an inverted "U" shape. Figure 2b, each circle of protection blocks 31 forms an inverted "U" shape. Multiple protection lines 30 or multiple circles of protection blocks 31 can be equivalent to multiple parallel capacitor plates, which can further timely guide and accommodate the instantaneously accumulated high electrostatic voltage, thereby further reducing the interference and damage of the electrostatic voltage to the driving circuit 2 in the first area 101A and the circuit in the display area 100.

[0060] In some embodiments, reference Figure 2c , at least part of the insulating layer 24 also extends to the second area 101B, and at least part of the distance between the protective structure 3 and the substrate 1 is different. That is, at least part of the protective structure 3 is located on the film surface at different heights on one side of the substrate 1. In this way, the surface of the protective structure 3 in the second area 101B that is away from the substrate 1 can be uneven.

[0061] In this embodiment, the display substrate can be an array substrate, which can be assembled with a color film substrate. The surface of the side of the protective structure 3 in the second area 101B of the array substrate facing away from the substrate 1 is used to set a frame-sealing glue 14 to achieve the assembly and bonding of the array substrate and the color film substrate. Since the surface of the side of the protective structure 3 in the second area 101B facing away from the substrate 1 is uneven, the contact area between the side of the protective structure 3 in the second area 101B facing away from the substrate 1 and the frame-sealing glue 14 can be increased, thereby improving the adhesion between the protective structure 3 and the frame-sealing glue 14 and reducing or avoiding the intrusion of external water vapor.

[0062] In some embodiments, reference Figure 2d , the display substrate further includes a grounding line 4, which is located in the first area 101A, and the orthographic projection of the grounding line 4 on the substrate 1 is located between the orthographic projection of the protection structure 3 and the driving circuit 2 on the substrate 1; along the direction away from the display area 100, part of the protection structure 3 close to the grounding line 4 is electrically connected to the grounding line 4. In this way, the external instantaneous large current (such as electrostatic current) can be grounded through the grounding line 4 and the part of the protection structure 3 electrically connected to the grounding line 4, thereby preventing the external instantaneous large current from damaging the driving circuit 2 and the circuit in the display area 100.

[0063] In some embodiments, reference Figure 3a and Figure 2d, the first routing line 21 includes a plurality of clock signal lines 21a, and the plurality of clock signal lines 21a are arranged in sequence in a direction away from the display area 100; of any two adjacent clock signal lines 21a, the length of the clock signal line 21a closer to the display area 100 is less than the length of the clock signal line 21a farther from the display area 100; the driving circuit 2 also includes a plurality of electrode blocks 20, which are made of the same material and arranged in the same layer as the connecting routing line 23, and the plurality of electrode blocks 20 and the plurality of clock signal lines 21a correspond one to one, and the orthographic projections of the corresponding electrode blocks 20 and the clock signal lines 21a on the substrate 1 at least partially overlap; of any two adjacent electrode blocks 20 in the direction away from the display area 100, the orthographic projection overlapping area of ​​the electrode block 20 closer to the display area 100 and the clock signal line 21a on the substrate 1 is greater than the orthographic projection overlapping area of ​​the electrode block 20 farther from the display area 100 and the clock signal line 21a on the substrate 1.

[0064] In some embodiments, the driving circuit 2 includes a shift register circuit 25, and the shift register circuit 25 includes a plurality of shift register units (i.e., GOA units), and the plurality of shift register units are cascaded in sequence, and the circuit design of each shift register unit is the same. Each shift register unit outputs a gate scanning signal, and each gate scanning signal is provided to a gate line; a plurality of gate lines are distributed in the display area 100, and each gate line is connected to the pixel circuit of a row of pixels to drive a row of pixels to turn on.

[0065] In some embodiments, the shift register circuit 25 includes 8 clock signal lines 21a, each clock signal line 21a is connected to a shift register unit, and the 8 clock signal lines 21a are respectively connected to 8 different shift register units, and the 8 different shift register units form a group, and the remaining shift register units and the 8 clock signal lines 21a are periodically connected in sequence. Figure 3b, the lengths of the eight clock signal lines 21a are different, and thus the resistances of the eight clock signal lines 21a are also different; specifically, the length of the clock signal line 21a farther from the display area 100 is greater than the length of the clock signal line 21a closer to the display area 100. Therefore, there is a large load difference between the clock signal line 21a farther from the display area 100 and the clock signal line 21a closer to the display area 100, so that the time when the clock signal on the clock signal line 21a farther from the display area 100 (such as CLK8) reaches a high level is shorter than that of the clock signal line 21a closer to the display area 100. The time for the clock signal on 1a (such as CLK1) to reach a high level is long, so that the actual start-up time of the clock signal line 21a farther away from the display area 100 is shorter than the actual start-up time of the clock signal line 21a closer to the display area 100, which leads to differences in the time for the shift register units connected to different clock signal lines 21a to output gate scanning signals, and further leads to differences in the charging voltages of pixel electrodes of pixels in different rows, and then leads to differences in the voltage differences between the pixel electrodes of pixels in different rows and their corresponding common electrodes, which ultimately leads to poor display of horizontal stripes on the display panel.

[0066] In this embodiment, based on the fact that the load of the clock signal line 21a is proportional to or equal to the product of its resistance and capacitance, by making the orthographic overlap area of ​​the electrode block 20 and the clock signal line 21a closer to the display area 100 on the substrate 1 larger than the orthographic overlap area of ​​the electrode block 20 and the clock signal line 21a farther from the display area 100 on the substrate 1, it is possible to ensure that the capacitance of the clock signal line 21a (such as CLK1) closer to the display area 100 is greater than the capacitance of the clock signal line 21a (such as CLK8) farther from the display area 100, thereby adjusting the orthographic overlap area of ​​the corresponding electrode block 20 and the clock signal line 21a to ensure that the product of the resistance and capacitance of the clock signal line 21a farther from the display area 100 is substantially equal to the product of the resistance and capacitance of the clock signal line 21a closer to the display area 100, thereby achieving the effect of compensating the load difference of different clock signal lines 21a by capacitance, thereby improving or avoiding the display of poor horizontal stripes on the display panel.

[0067] In some embodiments, the orthographic projections of the electrode block 20 and the via 240 on the substrate 1 do not overlap. Because there is an electrical signal on the connection trace 23 at the via 240 position, and no electrical signal needs to be applied to the electrode block 20, the electrode block 20 needs to be set at a position that avoids the via 240 position.

[0068] In some embodiments, the driving circuit 2 includes a gate driving circuit (ie, a shift register circuit, also known as a GOA circuit); the connecting wires 23 are made of transparent metal oxide materials, such as indium tin oxide and the like.

[0069] In some embodiments, the display substrate may be an array substrate, or a color filter substrate, or other display substrates that may be susceptible to water vapor intrusion and may cause electrochemical corrosion of the connecting traces 23 at the via holes 240 .

[0070] In some embodiments, the display substrate may be an LCD display substrate, or an OLED display substrate, or other display substrates having the above-mentioned structural characteristics.

[0071] The display substrate provided in the present embodiment, by arranging a protective structure in the second area, and the protective structure and the connecting wiring are made of the same material and arranged in the same layer, can make the protective structure closer to the outer edge of the frame area than the connecting wiring at the via hole. When water vapor invades from the outside of the frame area, it can preferentially react electrochemically with the protective structure located in the second area, thereby reducing or avoiding electrochemical corrosion of the connecting wiring at the via hole by water vapor, thereby ensuring effective signal transfer of the connecting wiring at the via hole, and ultimately ensuring the normal display of the display substrate; at the same time, when a large electrostatic voltage accumulates at the outer edge of the frame area, the protective structure located in the second area can preferentially guide and accommodate the electrostatic voltage, thereby reducing the interference and damage of the electrostatic voltage to the driving circuit in the first area and the circuit in the display area, thereby protecting the circuits in the first area and the display area, and further ensuring the normal display of the display substrate.

[0072] In a second aspect, an embodiment of the present disclosure provides a display panel, comprising the above-mentioned display substrate.

[0073] The display panel, by adopting the display substrate in the above embodiment, can avoid corrosion damage to the internal circuit of the display panel caused by water vapor intrusion, and can also avoid interference and damage to the internal circuit of the display panel caused by static electricity voltage, thereby ensuring the display quality of the display panel.

[0074] The display panel provided in the embodiments of the present disclosure may be an LCD panel, an LCD television, an LCD billboard, an OLED panel, an OLED television, an OLED billboard, a display, a mobile phone, a navigator, or any other product or component with a display function.

[0075] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a display area and a frame area, wherein the frame area surrounds the periphery of the display area, the frame area comprises a first area and a second area, the second area is located on a side of the first area away from the display area, The display substrate comprises a base and a driving circuit, wherein the driving circuit is located on one side of the base and in the first area; The driving circuit includes a first routing line, a second routing line and a connecting routing line, wherein the first routing line, the second routing line and the connecting routing line are sequentially stacked in a direction away from the substrate, and an insulating layer is provided between any two adjacent ones; The connecting wire electrically connects the first wire and the second wire through a via hole provided in the insulating layer; It is characterized in that The display substrate further comprises a protection structure, which is located on one side of the base and in the second area. The protection structure and the connection wiring are made of the same material and are arranged in the same layer.

2. The display substrate according to claim 1, characterized in that: The protection structure includes a plurality of protection wirings, the plurality of protection wirings respectively surround the display area, and the plurality of protection wirings are arranged in sequence in a direction away from the display area.

3. The display substrate according to claim 1, characterized in that: The protection structure includes a plurality of protection blocks, and the plurality of protection blocks are distributed around the display area. In a direction away from the display area, there are at least two circles of the protection block; The positions of the protection blocks in two adjacent circles are staggered.

4. The display substrate according to claim 2 or 3, characterized in that: The frame area includes a first side frame, a second side frame, a third side frame and a binding side frame, the first side frame is opposite to the binding side frame, and the second side frame is opposite to the third side frame; The protective structure is distributed on the first side frame, the second side frame and the third side frame.

5. The display substrate according to claim 2 or 3, characterized in that: At least part of the insulating layer also extends to the second region, At least some of the protection structures are located at different distances from the substrate.

6. The display substrate according to claim 2 or 3, characterized in that: It also includes a ground line, which is located in the first area, and the orthographic projection of the ground line on the substrate is located between the orthographic projection of the protection structure and the driving circuit on the substrate; Along a direction away from the display area, a portion of the protection structure close to the ground line is electrically connected to the ground line.

7. The display substrate according to claim 1, characterized in that: The first wiring includes a plurality of clock signal lines, and the plurality of clock signal lines are arranged in sequence in a direction away from the display area; Of any two adjacent clock signal lines, the length of the clock signal line closer to the display area is shorter than the length of the clock signal line farther from the display area; The driving circuit also includes a plurality of electrode blocks, which are made of the same material and arranged on the same layer as the connecting wiring. The plurality of electrode blocks correspond to the plurality of clock signal lines one by one, and the orthographic projections of the corresponding electrode blocks and the clock signal lines on the substrate at least partially overlap; Among any two adjacent electrode blocks along the direction away from the display area, the overlapping area of ​​the orthographic projections of the electrode block closer to the display area and the clock signal line on the substrate is larger than the overlapping area of ​​the orthographic projections of the electrode block farther from the display area and the clock signal line on the substrate.

8. The display substrate according to claim 7, characterized in that: The orthographic projections of the electrode block and the via hole on the substrate do not overlap.

9. The display substrate according to claim 1, characterized in that: The driving circuit includes a gate driving circuit; The connecting wires are made of transparent metal oxide material.

10. A display panel, characterized in that: A display substrate comprising any one of claims 1 to 9.

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