Band-gap reference circuit

Abstract

A source electrode of a PMOS tube M1, a source electrode of a PMOS tube M2, a source electrode of a PMOS tube M3 and a source electrode of a PMOS tube M7 are all connected to a power supply end, a drain electrode of the PMOS tube M1, a grid electrode of the PMOS tube M1 and a grid electrode of the PMOS tube M2 are all connected to a drain electrode of an NMOS tube M4, a drain electrode of the PMOS tube M2, a grid electrode of the PMOS tube M3 and a grid electrode of the PMOS tube M7 are all connected to a drain electrode of an NMOS tube M5, a source electrode of the NMOS tube M4 is connected with an emitting electrode of a PNP tube Q1, and a drain electrode of the NMOS tube M5 is connected with an emitting electrode of a PNP tube Q1. The source electrode of the NMOS tube M5 is connected with the emitting electrode of the PNP tube Q2, the source electrode of the NMOS tube M6 is connected with the emitting electrode of the PNP tube Q3, the drain electrode of the PMOS tube M7 is connected with the emitting electrode of the PNP tube Q4, the connection point of the drain electrode of the PMOS tube M7 and the emitting electrode of the PNP tube Q4 is used as a reference voltage end Vref, and the collector electrode of the PNP tube Q1, the base electrode of the PNP tube Q1, the base electrode of the PNP tube Q2, the collector electrode of the PNP tube Q2, the base electrode of the PNP tube Q2, the base electrode of the PNP tube Q2, the base electrode of the PNP tube Q3, the collector electrode of the PNP tube Q3, the The PSR of the reference voltage can be improved on the premise that the power supply voltage is not increased, and it can be guaranteed that the voltage reference source is accurate and reliable.

Description

Technical Field

[0001] The invention relates to a reference voltage circuit, and in particular to a bandgap reference circuit. Background Art

[0002] With the rapid development of electronic information technology, especially in emerging application fields such as artificial intelligence (AI), human-computer interaction and the Internet of Things (IoT), the demand for high-precision, low-power electronic systems has exploded. In order to accurately predict and respond to changes in the external environment, electronic systems need to extract useful information through precise analog-to-digital conversion (ADC), efficient data processing and analysis, and advanced machine learning algorithms. In this process, ensuring the accuracy of analog-to-digital conversion is particularly critical. For this purpose, a stable voltage reference source that is not affected by input voltage, ambient temperature and process fluctuations is an indispensable component to achieve this goal. Therefore, bandgap reference sources, as circuit modules that provide such stable voltage or current, have been widely used in standard CMOS processes.

[0003] However, with the continuous expansion of the portable electronic device market and the continuous improvement of system integration (SOC), low power consumption and low power supply voltage have become important considerations in the design of the next-generation chips. Traditional bandgap reference circuits are limited by their inherent structural characteristics and often find it difficult to maintain the stability of the reference voltage and the power supply rejection ratio (PSR) while reducing power consumption.

[0004] An existing bandgap reference circuit is as follows Figure 2 As shown, this circuit mainly ensures that the currents of the three branches are equal by the MOS tube on the top. However, the output impedance of the single-layer MOS tube is insufficient. The change of the power supply voltage will make the voltages at points X and Y no longer equal, and the current copy is inaccurate. When the deviated current flows through the resistor R2, the voltage drop on the resistor R2 will also deviate, and the bandgap reference voltage will be greatly affected by the power supply voltage.

[0005] Another existing bandgap reference circuit is Figure 3 As shown, it is a common-source common-gate bandgap reference circuit. Due to the common-source common-gate structure, its output impedance is large enough, and the change of the power supply voltage has little effect on the X and Y points, so that the current copy is more accurate, and the fluctuation of the power supply voltage has a relatively small effect on the bandgap reference voltage. However, this structure finds that the power supply voltage is higher. In existing electronic circuits, as the power supply voltage becomes lower and lower, the limitations of this circuit gradually become apparent. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a bandgap reference circuit which can improve the PSR of the reference voltage without increasing the power supply voltage and ensure the voltage reference source is accurate and reliable, in view of the deficiencies of the prior art.

[0007] In order to solve the above technical problems, the present invention adopts the following technical solutions.

[0008] A bandgap reference circuit comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M7, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PNP tube Q1, a PNP tube Q2, a PNP tube Q3 and a PNP tube Q4, wherein the source of the PMOS tube M1, the source of the PMOS tube M2, the source of the PMOS tube M3 and the source of the PMOS tube M7 are all connected to a power supply end, the drain of the PMOS tube M1, the gate of the PMOS tube M1 and the gate of the PMOS tube M2 are all connected to the drain of the NMOS tube M4, the drain of the PMOS tube M2, the gate of the PMOS tube M3 and the gate of the PMOS tube M7 are all connected to the drain of the NMOS tube M5, the drain of the PMOS tube M3, the drain of the NMOS tube M5 and the gate of the PMOS tube M7 are all connected to the drain of the NMOS tube M5. The gate of the OS transistor M4, the gate of the NMOS transistor M5 and the gate of the NMOS transistor M6 are all connected to the drain of the NMOS transistor M6, the source of the NMOS transistor M4 is connected to the emitter of the PNP transistor Q1, the source of the NMOS transistor M5 is connected to the emitter of the PNP transistor Q2, the source of the NMOS transistor M6 is connected to the emitter of the PNP transistor Q3, the drain of the PMOS transistor M7 is connected to the emitter of the PNP transistor Q4 and the connection point of the two is used as the reference voltage terminal Vref, the collector of the PNP transistor Q1, the base of the PNP transistor Q1, the base of the PNP transistor Q2, the collector of the PNP transistor Q2, the base of the PNP transistor Q3, the collector of the PNP transistor Q3, the base of the PNP transistor Q4 and the collector of the PNP transistor Q4 are all grounded.

[0009] A resistor R1 is connected in series on the line between the source of the NMOS tube M5 and the emitter of the PNP tube Q2.

[0010] A resistor R2 is connected in series on the line between the drain of the PMOS tube M7 and the emitter of the PNP tube Q4.

[0011] The connection point between the drain of the PMOS tube M7 and the resistor R2 serves as a reference voltage terminal Vref.

[0012] The connection point between the drain of the PMOS transistor M1 , the gate of the PMOS transistor M1 , the gate of the PMOS transistor M2 , and the drain of the NMOS transistor M4 serves as the first node A.

[0013] The connection point between the drain of the PMOS transistor M2, the gate of the PMOS transistor M3, the gate of the PMOS transistor M7 and the drain of the NMOS transistor M5 serves as the second node B.

[0014] The connection points among the drain of the PMOS tube M3, the gate of the NMOS tube M4, the gate of the NMOS tube M5, the gate of the NMOS tube M6 and the drain of the NMOS tube M6 serve as the third node C.

[0015] The bandgap reference circuit disclosed in the present invention is an improvement on the traditional bandgap reference circuit. By adding three specially designed transistors to the traditional circuit, a circuit topology with higher output impedance is constructed. This new circuit structure can not only effectively improve the PSR of the circuit, but also significantly reduce the required power supply voltage, thereby broadening the application range of the circuit. Compared with the traditional method of using a common source and common gate structure to improve the output impedance, the structure proposed in the present invention significantly reduces the power supply voltage requirement by reducing the number of transistor stacking layers (from six layers to three layers) while maintaining a similar effect. In addition, this circuit structure not only reduces power consumption, but also improves the reliability and stability of the circuit, and better meets the application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The schematic diagram of the bandgap reference circuit of the present invention;

[0017] Figure 2 It is a schematic diagram of a bandgap reference circuit in the prior art;

[0018] Figure 3 This is another schematic diagram of a bandgap reference circuit in the prior art. DETAILED DESCRIPTION

[0019] The present invention is described in more detail below with reference to the accompanying drawings and embodiments.

[0020] The present invention discloses a bandgap reference circuit, see Figure 1, which includes a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M7, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PNP tube Q1, a PNP tube Q2, a PNP tube Q3 and a PNP tube Q4, wherein the source of the PMOS tube M1, the source of the PMOS tube M2, the source of the PMOS tube M3 and the source of the PMOS tube M7 are all connected to the power supply end, the drain of the PMOS tube M1, the gate of the PMOS tube M1 and the gate of the PMOS tube M2 are all connected to the drain of the NMOS tube M4, the drain of the PMOS tube M2, the gate of the PMOS tube M3 and the gate of the PMOS tube M7 are all connected to the drain of the NMOS tube M5, the drain of the PMOS tube M3, the drain of the NMOS tube M The gate of the NMOS tube M4, the gate of the NMOS tube M5 and the gate of the NMOS tube M6 are all connected to the drain of the NMOS tube M6, the source of the NMOS tube M4 is connected to the emitter of the PNP tube Q1, the source of the NMOS tube M5 is connected to the emitter of the PNP tube Q2, the source of the NMOS tube M6 is connected to the emitter of the PNP tube Q3, the drain of the PMOS tube M7 is connected to the emitter of the PNP tube Q4 and the connection point between the two is used as the reference voltage terminal Vref, the collector of the PNP tube Q1, the base of the PNP tube Q1, the base of the PNP tube Q2, the collector of the PNP tube Q2, the base of the PNP tube Q3, the collector of the PNP tube Q3, the base of the PNP tube Q4 and the collector of the PNP tube Q4 are all grounded.

[0021] In the above circuit, three transistors, namely, PMOS tube M1, PMOS tube M2 and PMOS tube M3, are added on the basis of the traditional circuit. Since the sizes of PMOS tube M1, PMOS tube M2 and PMOS tube M3 are the same, and the sizes of NMOS tube M4, NMOS tube M5 and NMOS tube M6 are also the same, the currents flowing through these transistors are ensured to be consistent. This design makes the voltages at point X and point Y equal, thereby ensuring the stability and accuracy of the circuit.

[0022] Furthermore, a resistor R1 is connected in series on the line between the source of the NMOS tube M5 and the emitter of the PNP tube Q2. A resistor R2 is connected in series on the line between the drain of the PMOS tube M7 and the emitter of the PNP tube Q4. The connection point between the drain of the PMOS tube M7 and the resistor R2 serves as a reference voltage terminal Vref.

[0023] In this embodiment, different Vbe voltages are generated by specially designed PNP transistors Q1 and Q2 (the same current flows through these transistors but the emitter areas are different). This difference generates a current proportional to △Vbe on resistor R1. The final output voltage Vout can be expressed as the value of Vbe3 plus (△Vbe / R1)*R2. By adjusting the ratio of R1 and R2, the zero temperature coefficient characteristic of the output voltage can be achieved, thereby further improving the stability and accuracy of the circuit.

[0024] As a preferred embodiment, the connection point between the drain of the PMOS tube M1, the gate of the PMOS tube M1, the gate of the PMOS tube M2 and the drain of the NMOS tube M4 is used as the first node A. The connection point between the drain of the PMOS tube M2, the gate of the PMOS tube M3, the gate of the PMOS tube M7 and the drain of the NMOS tube M5 is used as the second node B. The connection point between the drain of the PMOS tube M3, the gate of the NMOS tube M4, the gate of the NMOS tube M5, the gate of the NMOS tube M6 and the drain of the NMOS tube M6 is used as the third node C.

[0025] The above circuit structure has good self-regulation ability. At the same time, when the voltage at point A is reduced due to external interference, the voltage at point B will increase accordingly, thereby causing the voltage at point C to decrease. This change causes the voltage at point A to rise again through a feedback mechanism, thereby quickly eliminating the disturbance. In addition, the above self-regulation characteristics are not available in traditional structures, which further enhances the stability and reliability of the circuit.

[0026] The bandgap reference circuit disclosed in the present invention is an improvement on the traditional bandgap reference circuit. By adding three specially designed transistors to the traditional circuit, a circuit topology with higher output impedance is constructed. This new circuit structure can not only effectively improve the PSR of the circuit, but also significantly reduce the required power supply voltage, thereby broadening the application range of the circuit. Compared with the traditional method of using a common source and common gate structure to improve the output impedance, the structure proposed in the present invention significantly reduces the power supply voltage requirement by reducing the number of transistor stacking layers (from six layers to three layers) while maintaining a similar effect. In addition, this circuit structure not only reduces power consumption, but also improves the reliability and stability of the circuit, and better meets the application requirements.

[0027] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions or improvements made within the technical scope of the present invention should be included in the scope of protection of the present invention.

Claims

1. A bandgap reference circuit, characterized in that: The invention comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M7, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PNP tube Q1, a PNP tube Q2, a PNP tube Q3 and a PNP tube Q4, wherein the source of the PMOS tube M1, the source of the PMOS tube M2, the source of the PMOS tube M3 and the source of the PMOS tube M7 are all connected to the power supply end, the drain of the PMOS tube M1, the gate of the PMOS tube M1 and the gate of the PMOS tube M2 are all connected to the drain of the NMOS tube M4, the drain of the PMOS tube M2, the gate of the PMOS tube M3 and the gate of the PMOS tube M7 are all connected to the drain of the NMOS tube M5, the drain of the PMOS tube M3, the drain of the NMOS tube M4 The gate of the NMOS tube M5 and the gate of the NMOS tube M6 are all connected to the drain of the NMOS tube M6, the source of the NMOS tube M4 is connected to the emitter of the PNP tube Q1, the source of the NMOS tube M5 is connected to the emitter of the PNP tube Q2, the source of the NMOS tube M6 is connected to the emitter of the PNP tube Q3, the drain of the PMOS tube M7 is connected to the emitter of the PNP tube Q4 and the connection point between the two is used as the reference voltage terminal Vref, the collector of the PNP tube Q1, the base of the PNP tube Q1, the base of the PNP tube Q2, the collector of the PNP tube Q2, the base of the PNP tube Q3, the collector of the PNP tube Q3, the base of the PNP tube Q4 and the collector of the PNP tube Q4 are all grounded.

2. The bandgap reference circuit according to claim 1, wherein: A resistor R1 is connected in series on the line between the source of the NMOS tube M5 and the emitter of the PNP tube Q2.

3. The bandgap reference circuit according to claim 1, wherein: A resistor R2 is connected in series on the line between the drain of the PMOS tube M7 and the emitter of the PNP tube Q4.

4. The bandgap reference circuit according to claim 3, characterized in that: The connection point between the drain of the PMOS tube M7 and the resistor R2 serves as a reference voltage terminal Vref.

5. The bandgap reference circuit according to claim 1, wherein: The connection point between the drain of the PMOS transistor M1 , the gate of the PMOS transistor M1 , the gate of the PMOS transistor M2 , and the drain of the NMOS transistor M4 serves as the first node A.

6. The bandgap reference circuit according to claim 1, wherein: The connection point between the drain of the PMOS transistor M2, the gate of the PMOS transistor M3, the gate of the PMOS transistor M7 and the drain of the NMOS transistor M5 serves as the second node B.

7. The bandgap reference circuit according to claim 1, wherein: The connection points among the drain of the PMOS tube M3, the gate of the NMOS tube M4, the gate of the NMOS tube M5, the gate of the NMOS tube M6 and the drain of the NMOS tube M6 serve as the third node C.

Images