Band-gap reference detection circuit

Abstract

The invention discloses a band-gap reference detection circuit, which belongs to the field of integrated circuits and comprises a PMOS (P-channel Metal Oxide Semiconductor) tube M0, a PMOS tube M1, a PMOS tube M2, an NMOS (N-channel Metal Oxide Semiconductor) tube M3, a triode Q0 and a Schmidt buffer, the device is used for detecting whether the band-gap reference works normally or not, and whether the band-gap reference enters a normal working state or not is determined by comparing the current I2 with the current I3. When the band-gap reference works normally, a signal that BGOK is equal to 1 is given, a follow-up circuit can decide whether to work or not according to the BGOK signal, working state errors of other circuits caused by inaccuracy of a reference source in the power-on process are avoided, an IC is prevented from giving wrong data, the working reliability of the IC is improved, the circuit is simple, and loss is small.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a bandgap reference detection circuit. Background Art

[0002] If you want to get a precise signal in an integrated circuit, you always need a precise voltage or current, and a precise voltage or current is usually obtained through a bandgap reference. Bandgap references are widely used in integrated circuits due to their excellent temperature stability.

[0003] During the chip power-on process, the bandgap reference source needs time to establish a normal working state. The reference voltage at this time is incorrect, so a signal needs to be generated to indicate whether the bandgap reference is working normally. The subsequent circuit will not start working until the signal is valid. Summary of the invention

[0004] The object of the present invention is to provide a bandgap reference detection circuit to solve the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention provides a bandgap reference detection circuit, comprising: a PMOS tube M0, a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, a triode Q0, and a Schmitt buffer; The source of the PMOS tube M1 and the source of the PMOS tube M2 are both connected to the power supply voltage VDD, the gate of the PMOS tube M1 and the gate of the PMOS tube M2 are both connected to the bias voltage VBP, the drain of the PMOS tube M1 is simultaneously connected to the emitter of the transistor Q0 and the gate of the PMOS tube M0, the drain of the PMOS tube M2 is connected to the source of the PMOS tube M0; the drain of the PMOS tube M0 is simultaneously connected to the input end of the Schmitt buffer and the drain of the NMOS tube M3, the gate of the NMOS tube M3 is connected to the bias voltage VBN, and the source of the NMOS tube M3, the base and the collector of the transistor Q0 are all grounded VSS.

[0006] In one embodiment, the operating modes of the bandgap reference detection circuit include: During the power-on process, the VDD voltage is low. Due to the exponential characteristics of the current and voltage of the transistor Q0, VBE0 is first established during the power-on process. Since the source voltage VS0 of the PMOS tube M0 - the emitter voltage VBE0 of the transistor Q0 is less than the threshold voltage of the PMOS tube M0, the PMOS tube M0 is in the off state, and the current I2 flowing through the PMOS tube M2 is 0. The small current of the NMOS tube M3 will pull down the input signal VFLG of the Schmitt buffer, and the output signal BG_OK of the Schmitt buffer is 0; Normal operation, when the VDD voltage continues to rise, the source voltage VS0 of the PMOS tube M0 - the emitter voltage VBE0 of the transistor Q0 is greater than the threshold voltage of the PMOS tube M0, the PMOS tube M0 is in the on state, and when the current I2 flowing through the PMOS tube M2> the current I3 flowing through the NMOS tube M3, the input signal VFLG voltage of the Schmitt buffer will be pulled up, and the output signal BG_OK of the Schmitt buffer is 1.

[0007] The present invention provides a bandgap reference detection circuit, which is used to detect whether a bandgap reference works normally. When the bandgap reference works normally, a signal BG_OK=1 is given, so as to avoid errors in the working states of other circuits due to inaccurate reference sources during power-on, avoid erroneous data given by IC, and improve the reliability of IC operation. The circuit is simple and the loss is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 The present invention provides a schematic diagram of the structure of a bandgap reference detection circuit. DETAILED DESCRIPTION

[0009] The following is a further detailed description of a bandgap reference detection circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0010] The present invention provides a bandgap reference detection circuit, the structure of which is as follows Figure 1 As shown, it includes a PMOS tube M0, a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, a transistor Q0, and a Schmitt buffer; the source of the PMOS tube M1 and the source of the PMOS tube M2 are both connected to VDD, the gate of the PMOS tube M1 and the gate of the PMOS tube M2 are both connected to VBP, the drain of the PMOS tube M1 is simultaneously connected to the emitter of the transistor Q0 and the gate of the PMOS tube M0, and the drain of the PMOS tube M2 is connected to the source of the PMOS tube M0; the drain of the PMOS tube M0 is simultaneously connected to the input end of the Schmitt buffer and the drain of the NMOS tube M3, the gate of the NMOS tube M3 is connected to VBN, and the source of the NMOS tube M3, the base and the collector of the transistor Q0 are all grounded to VSS.

[0011] Among them, VDD is the voltage required for the normal operation of the circuit, VBP is the bias voltage of the bandgap reference to generate the PTAT current, VBN is the NMOS bias voltage generated by the bandgap reference, VBE0 is the emitter voltage of the transistor Q0, VS0 is the source voltage of the PMOS tube M0, and VFLG gives the signal BG_OK for the normal operation of the bandgap reference through the Schmitt buffer. I1 is the current flowing through the PMOS tube M1, I2 is the current flowing through the PMOS tube M2, and I3 is the current flowing through the NMOS tube M3. In normal operation, the mirror currents of the PMOS tubes M1 and M2 are greater than the mirror current of the NMOS tube M3. The working mode of this circuit is described in detail as follows: 1. During the power-on process, the VDD voltage is low. Due to the exponential characteristics of the current and voltage of the transistor Q0, VBE0 can be established first during the power-on process. At this time, since VS0-VBE0 is less than the threshold voltage of the PMOS tube M0, the PMOS tube M0 is in the off state, and the current I2 = 0. At this time, the small current of the NMOS tube M3 will pull down VFLG, and BG_OK = 0.

[0012] 2. Normal operation: when the VDD voltage continues to rise and VS0-VBE0 is greater than the threshold voltage of the PMOS tube M0, the PMOS tube M0 is in the on state. When I2>I3, the VFLG voltage will be pulled up and a signal of BG_OK=1 will be given.

[0013] The present invention provides a bandgap reference detection circuit, which is used to detect whether the bandgap reference is working normally, and determines whether the bandgap reference enters a normal working state by comparing the magnitudes of currents I2 and I3. After the bandgap reference is working normally, a BG_OK flag signal is given, and the subsequent circuit can decide whether to work according to the BG_OK signal, thereby avoiding giving wrong data during the power-on process, thereby ensuring the normal operation of the entire IC.

[0014] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A bandgap reference detection circuit, characterized in that: include: PMOS tube M0, PMOS tube M1, PMOS tube M2, NMOS tube M3, transistor Q0, Schmitt buffer; The source of the PMOS tube M1 and the source of the PMOS tube M2 are both connected to the power supply voltage VDD, the gate of the PMOS tube M1 and the gate of the PMOS tube M2 are both connected to the bias voltage VBP, the drain of the PMOS tube M1 is simultaneously connected to the emitter of the transistor Q0 and the gate of the PMOS tube M0, the drain of the PMOS tube M2 is connected to the source of the PMOS tube M0; the drain of the PMOS tube M0 is simultaneously connected to the input end of the Schmitt buffer and the drain of the NMOS tube M3, the gate of the NMOS tube M3 is connected to the bias voltage VBN, and the source of the NMOS tube M3, the base and the collector of the transistor Q0 are all grounded VSS.

2. The bandgap reference detection circuit according to claim 1, characterized in that: The working modes of the bandgap reference detection circuit include: During the power-on process, the VDD voltage is low. Due to the exponential characteristics of the current and voltage of the transistor Q0, VBE0 is first established during the power-on process. Since the source voltage VS0 of the PMOS tube M0 - the emitter voltage VBE0 of the transistor Q0 is less than the threshold voltage of the PMOS tube M0, the PMOS tube M0 is in the off state, and the current I2 flowing through the PMOS tube M2 is 0. The small current of the NMOS tube M3 will pull down the input signal VFLG of the Schmitt buffer, and the output signal BG_OK of the Schmitt buffer is 0; Normal operation, when the VDD voltage continues to rise, the source voltage VS0 of the PMOS tube M0 - the emitter voltage VBE0 of the transistor Q0 is greater than the threshold voltage of the PMOS tube M0, the PMOS tube M0 is in the on state, and when the current I2 flowing through the PMOS tube M2> the current I3 flowing through the NMOS tube M3, the input signal VFLG voltage of the Schmitt buffer will be pulled up, and the output signal BG_OK of the Schmitt buffer is 1.

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