Voltage reference circuit, reference voltage generation method and electronic equipment

Abstract

The invention provides a voltage reference circuit, a reference voltage generation method and electronic equipment. The voltage reference circuit comprises a bias sub-circuit, a negative temperature sub-circuit, a positive temperature sub-circuit, a first node, a power supply end, a grounding end and a reference voltage output end, the bias sub-circuit is respectively coupled with the first node, the power supply end and the grounding end and is used for generating bias current; the negative temperature sub-circuit is respectively coupled with the power supply end, the grounding end and the first node and is used for generating a first voltage with a negative temperature coefficient; and the positive temperature sub-circuit is respectively coupled with the power supply end, the first node and the reference voltage output end, and is used for generating a second voltage with a positive temperature coefficient, obtaining a reference voltage with a zero temperature coefficient according to the first voltage and the second voltage, and transmitting the reference voltage to the reference voltage output end. The circuit is simple in structure and small in layout area.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuit design, and in particular to a voltage reference circuit, a method for generating a reference voltage, and an electronic device. Background Art

[0002] A voltage reference circuit usually refers to a highly stable voltage source used as a voltage reference in a circuit.

[0003] With the continuous increase in the scale of integrated circuits, especially the development of system integration technology (SOC), it has also become an indispensable basic circuit in large-scale and ultra-large-scale integrated circuits and almost all digital analog systems.

[0004] In the existing voltage reference circuit design, the reference voltage is usually designed by utilizing the characteristics that the VBE (base-emitter voltage) of the BJT (bipolar junction transistor) device has a negative temperature coefficient and the base-emitter difference is proportional to the absolute temperature. However, there are problems such as complex structure and large layout area. Summary of the invention

[0005] The embodiments of the present invention provide a voltage reference circuit, a method for generating a reference voltage and an electronic device to solve the problems of a complex structure and a large layout area in the existing voltage reference circuit.

[0006] In order to solve the above-mentioned technical problems, the present invention is achieved as follows:

[0007] In a first aspect, an embodiment of the present invention provides a voltage reference circuit, comprising: a bias subcircuit, a negative temperature subcircuit, a positive temperature subcircuit, a first node, a power supply terminal, a ground terminal and a reference voltage output terminal;

[0008] A bias subcircuit, coupled to the first node, the power supply terminal and the ground terminal respectively, for generating a bias current;

[0009] A negative temperature sub-circuit, coupled to the power supply terminal, the ground terminal and the first node respectively, for generating a first voltage with a negative temperature coefficient;

[0010] A positive temperature sub-circuit is coupled to the power supply terminal, the first node and the reference voltage output terminal respectively, and is used to generate a second voltage with a positive temperature coefficient, and is also used to obtain a reference voltage with a zero temperature coefficient based on the first voltage and the second voltage, and transmit the reference voltage to the reference voltage output terminal.

[0011] Optionally,

[0012] The negative temperature subcircuit comprises: a first transistor and a second transistor;

[0013] The positive temperature sub-circuit comprises: a third transistor and a fourth transistor;

[0014] The gate of the first transistor is coupled to the power supply, the first electrode of the first transistor is coupled to the ground terminal; the second electrode of the first transistor is coupled to the first node;

[0015] The gate of the second transistor and the drain of the second transistor are both coupled to the power supply; the source of the second transistor is coupled to the first node;

[0016] The gate of the third transistor is coupled to the power supply; the source of the third transistor is coupled to the first node; the drain of the third transistor is coupled to the reference voltage output terminal;

[0017] The gate of the fourth transistor and the drain of the fourth transistor are both coupled to the power supply; the source of the fourth transistor is coupled to the reference voltage output terminal;

[0018] Among them, the threshold voltage value of the first transistor is less than the threshold voltage value of the second transistor, the threshold voltage value of the third transistor is equal to the threshold voltage value of the fourth transistor; the width-to-length ratio of the second transistor is less than the width-to-length ratio of the first transistor; the width-to-length ratio of the fourth transistor is greater than the width-to-length ratio of the third transistor; the first transistor, the second transistor, the third transistor and the fourth transistor are in a subthreshold state.

[0019] Optionally,

[0020] The channel length of the first transistor is smaller than the channel length of the second transistor,

[0021] and / or,

[0022] A channel length of the third transistor is equal to a channel length of the fourth transistor.

[0023] Optionally,

[0024] The channel length d1 of the first transistor satisfies: 0.15 μm≤d1≤0.35 μm; and / or,

[0025] The channel length d2 of the second transistor satisfies: 0.9 μm≤d2≤1.1 μm; and / or,

[0026] The channel length d3 of the third transistor and the fourth transistor satisfies: 0.9 μm≤d3≤1.1 μm.

[0027] Optionally,

[0028] At least one of the first transistor, the second transistor, the third transistor, and the fourth transistor includes an enhancement mode gallium nitride HEMT transistor.

[0029] Optionally,

[0030] The bias subcircuit includes: a fifth transistor;

[0031] The gate of the fifth transistor is coupled to the power supply; the first electrode of the fifth transistor is coupled to the ground terminal; and the second electrode of the fifth transistor is coupled to the first node.

[0032] Optionally,

[0033] The bias subcircuit includes: a resistor unit;

[0034] The first end of the resistance unit is coupled to the power source and the first node respectively; the second end of the resistance unit is coupled to the ground end.

[0035] Optionally, it further includes: a first resistance unit and a second resistance unit;

[0036] The first end of the first resistor unit is coupled to the gate of the first transistor, the gate of the second transistor, and the second electrode of the second transistor respectively, and the second end of the first resistor unit is coupled to the power source;

[0037] A first end of the second resistance unit is coupled to the gate of the third transistor, the gate of the fourth transistor, and the second electrode of the fourth transistor respectively, and a second end of the second resistance unit is coupled to the power source.

[0038] In a second aspect, an embodiment of the present invention provides a method for generating a reference voltage, which is applied to a voltage reference circuit as described in any one of the first aspects.

[0039] The bias subcircuit generates a bias current;

[0040] The negative temperature subcircuit generates a first voltage having a negative temperature coefficient;

[0041] The positive temperature subcircuit generates a second voltage with a positive temperature coefficient, and is further used to obtain a reference voltage with a zero temperature coefficient according to the first voltage and the second voltage, and transmit the reference voltage to the reference voltage output terminal.

[0042] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a voltage reference circuit as described in any one of the first aspects.

[0043] In an embodiment of the present invention, a voltage reference circuit includes: a bias subcircuit, a negative temperature subcircuit, a positive temperature subcircuit, a first node, a power supply terminal, a ground terminal and a reference voltage output terminal; by superimposing a first voltage generated by the negative temperature subcircuit and a second voltage generated by the positive temperature subcircuit, a reference voltage with a zero temperature coefficient can be obtained, and the circuit structure is simple and the layout area is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0045] Figure 1 is a principle block diagram of a voltage reference circuit according to an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of the layout of a voltage reference circuit according to an embodiment of the present invention;

[0047] Figure 3 For Figure 2 A schematic structural diagram of a voltage reference circuit according to an embodiment of the present invention;

[0048] Figure 4 A schematic diagram of the relationship between the threshold voltage and the temperature coefficient of a transistor;

[0049] Figure 5 Schematic diagram of the relationship between the difference in threshold voltage and temperature coefficient of transistors. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] It should be noted that the collection, collection, updating, analysis, processing, use, transmission, storage and other aspects of user personal information involved in the technical solution of this disclosure are in compliance with the provisions of relevant laws and regulations, are used for legitimate purposes, and do not violate public order and good morals. Necessary measures are taken for user personal information to prevent illegal access to user personal information data and maintain the security of user personal information and network security.

[0052] In the technical solution of the present disclosure, words such as “connect”, “couple” or “connected” are not limited to physical or mechanical connections, but may include electrical connections.

[0053] The embodiment of the present invention provides a voltage reference circuit. Figure 1 As shown, Figure 1 : is a principle block diagram of a voltage reference circuit according to an embodiment of the present invention, the voltage reference circuit comprises: a bias subcircuit, a negative temperature subcircuit, a positive temperature subcircuit, a first node 102, a power supply terminal VDD, a ground terminal GND and a reference voltage output terminal 101;

[0054] A bias subcircuit, coupled to the first node 102, the power supply terminal VDD and the ground terminal GND respectively, for generating a bias current;

[0055] A negative temperature sub-circuit, coupled to the power supply terminal VDD, the ground terminal GND and the first node 102 respectively, for generating a first voltage with a negative temperature coefficient;

[0056] The positive temperature sub-circuit is coupled to the power supply terminal VDD, the first node 102 and the reference voltage output terminal 101 respectively, and is used to generate a second voltage with a positive temperature coefficient, and is also used to obtain a reference voltage with a zero temperature coefficient according to the first voltage and the second voltage, and transmit the reference voltage to the reference voltage output terminal 101.

[0057] In the embodiment of the present invention, the positive temperature subcircuit is used to superimpose the first voltage and the second voltage to obtain a reference voltage.

[0058] In an embodiment of the present invention, the voltage reference circuit includes: a bias subcircuit, a negative temperature subcircuit, a positive temperature subcircuit, a first node 102, a power supply terminal VDD, a ground terminal GND and a reference voltage output terminal 101; by superimposing the first voltage generated by the negative temperature subcircuit and the second voltage generated by the positive temperature subcircuit, a reference voltage with a zero temperature coefficient can be obtained, the circuit structure is simple, and the layout area is small.

[0059] In some embodiments of the present invention, optionally, see Figure 2 and Figure 3 As shown, Figure 2 is a schematic diagram of the layout of a voltage reference circuit according to an embodiment of the present invention, Figure 3 For Figure 2 A schematic structural diagram of a voltage reference circuit according to an embodiment of the present invention.

[0060] The negative temperature sub-circuit includes: a first transistor M1 and a second transistor M2;

[0061] The positive temperature sub-circuit includes: a third transistor M3 and a fourth transistor M4;

[0062] The gate of the first transistor M1 is coupled to the power supply, the first electrode of the first transistor M1 is coupled to the ground terminal GND; the second electrode of the first transistor M1 is coupled to the first node 102;

[0063] The gate of the second transistor M2 and the drain of the second transistor M2 are coupled to the power supply; the source of the second transistor M2 is coupled to the first node 102;

[0064] The gate of the third transistor M3 is coupled to the power supply; the source of the third transistor M3 is coupled to the first node 102; the drain of the third transistor M3 is coupled to the reference voltage output terminal 101;

[0065] The gate of the fourth transistor M4 and the drain of the fourth transistor M4 are coupled to the power supply; the source of the fourth transistor M4 is coupled to the reference voltage output terminal 101;

[0066] Among them, the threshold voltage value of the first transistor M1 is less than the threshold voltage value of the second transistor M2, the threshold voltage value of the third transistor M3 is equal to the threshold voltage value of the fourth transistor M4; the width-to-length ratio of the second transistor M2 is less than the width-to-length ratio of the first transistor M1; the width-to-length ratio of the fourth transistor M4 is greater than the width-to-length ratio of the third transistor M3; the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are in a subthreshold state.

[0067] In the embodiment of the present invention, the first electrode includes a source electrode, and the second electrode includes a drain electrode.

[0068] Specifically, the reference voltage V REF Based on the following formula:

[0069] V REF =V GS1 -V GS2 +V GS3 -V GS4

[0070] Among them, V GS1 is the driving voltage of the first transistor M1; V GS2 is the driving voltage of the second transistor M2; V GS3 is the driving voltage of the third transistor M3; V GS4 is the driving voltage of the fourth transistor M4.

[0071] In the subthreshold state, V GS1 -V GS2 That is the first voltage with a negative temperature coefficient, V GS3 -V GS4 That is, the second voltage with a positive temperature coefficient, the first voltage V GS1 -V GS2 and the second voltage V GS3 -V GS4 The reference voltage V is obtained by superposition REF .

[0072] In the subthreshold state, the driving voltage VGS It conforms to the following formula:

[0073]

[0074] Wherein, K is the width-to-length ratio of the transistor; I0 is a parameter determined by the transistor process; I D is the subthreshold current; V T is the thermal voltage, which is proportional to the temperature; V TH is the threshold voltage of the transistor; I0 is a parameter determined by the transistor process, I0 = μ0Cox(η - 1)V T 2 : μ0 is the electron mobility; Cox is the gate oxide capacitance per unit area; η is the subthreshold slope factor, that is, the slope of the transistor current rise in the subthreshold region.

[0075] Combined with the specific expression of the subthreshold current I D obtainable: It can be obtained that: Wherein, V TH1 is the threshold voltage of the first transistor; V TH2 is the threshold voltage of the second transistor; K1 is the width-to-length ratio of the first transistor; K2 is the width-to-length ratio of the second transistor.

[0076] In the embodiment of the present invention, the threshold voltage value of the first transistor M1 is less than the threshold voltage value of the second transistor M2, V TH1 < V TH2 , it can be obtained that V TH1 - V TH2 < 0; the width-to-length ratio of the second transistor M2 is less than the width-to-length ratio of the first transistor M1, K2 < K1, and it can be deduced that

[0077] According to Since V TH1 - V TH2 < 0 and < 0, it can be obtained that V GS1 - V GS2 < 0, that is, the first voltage V GS1 - V GS2 exhibits a negative temperature coefficient.

[0078] Combined with the specific expression of the subthreshold current I D obtainable: It can be obtained that: Wherein, v TH3 is the threshold voltage of the third transistor; V TH4 is the threshold voltage of the fourth transistor; K4 is the width-to-length ratio of the fourth transistor; K3 is the width-to-length ratio of the third transistor.

[0079] In the embodiment of the present invention, the threshold voltage value of the third transistor M3 is equal to the threshold voltage value of the fourth transistor M4, V TH3 =V TH4 , we can get V TH3 -V TH4 =0; the width-to-length ratio of the fourth transistor M4 is greater than the width-to-length ratio of the third transistor M3, K4>K3, and it can be deduced that

[0080] according to Since V TH3 -V TH4 =0 and V GS3 -V GS4 >0, that is, the second voltage V GS3 -V GS4 Positive temperature coefficient.

[0081] In summary, when the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are in a subthreshold state, the first voltage has a negative temperature coefficient, the second voltage has a positive temperature coefficient, and the first voltage and the second voltage are superimposed to obtain a reference voltage with a zero temperature coefficient.

[0082] In the embodiment of the present invention, the layout of the negative temperature sub-circuit and the positive temperature sub-circuit is realized by combining the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4, and the reference voltage is obtained by using the physical characteristics of the above transistors in the subthreshold state. The embodiment of the present invention does not need to use the BJT (bipolar transistor) device in the prior art, and the circuit structure is simple and the layout area is small.

[0083] In some embodiments of the present invention, optionally,

[0084] The channel length of the first transistor M1 is smaller than the channel length of the second transistor M2.

[0085] It should be noted that, under the transistor manufacturing process, the threshold voltage of the transistor has a negative temperature coefficient, and the smaller the channel length of the transistor, the larger the negative temperature coefficient. Therefore, the purpose of controlling the temperature coefficient can be achieved by controlling the channel length of the transistor. In the embodiment of the present invention, by setting the channel length of the first transistor M1 to be smaller than the channel length of the second transistor M2, the threshold voltage value of the first transistor M1 is smaller than the threshold voltage value of the second transistor M2, that is, V TH1 <V TH2 .

[0086] In some embodiments of the present invention, optionally,

[0087] The channel length of the third transistor M3 is equal to the channel length of the fourth transistor M4.

[0088] It should be noted that in the transistor manufacturing process, the threshold voltage of the transistor presents a negative temperature coefficient, and the smaller the channel length of the transistor, the larger the negative temperature coefficient. Therefore, the temperature coefficient can be controlled by controlling the channel length of the transistor. In the embodiment of the present invention, by setting the channel length of the third transistor M3 to be smaller than the channel length of the fourth transistor M4, the threshold voltage value of the third transistor M3 is equal to the threshold voltage value of the fourth transistor M4, that is, V TH3 =v TH4 .

[0089] In some embodiments of the present invention, optionally,

[0090] The channel length d1 of the first transistor M1 satisfies: 0.15 μm≤d1≤0.35 μm;

[0091] In some embodiments of the present invention, optionally,

[0092] The channel length d2 of the second transistor M2 satisfies: 0.9 μm≤d2≤1.1 μm;

[0093] In some embodiments of the present invention, optionally, the channel length d1 of the first transistor M1 is 0.25 μm, and the channel length d2 of the second transistor M2 is 1 μm.

[0094] See also Figure 4 As shown, Figure 4 The figure is a schematic diagram of the relationship between the threshold voltage and temperature coefficient of a transistor, which shows two curves corresponding to enhancement-mode GaN HEMT (HEMT, high electron mobility transistor) transistors with different channel lengths (0.25μm and 1μm) (the channel length of 0.25μm is a dotted line, and the channel length of 1μm is a solid line). Each curve actually represents the negative temperature coefficient of the corresponding transistor. It can be obtained that: the smaller the channel length, the more drastic the decrease in the threshold voltage of the enhancement-mode GaN HEMT transistor with increasing temperature, that is, the larger the negative temperature coefficient. See Figure 5 As shown, Figure 5 Schematic diagram of the relationship between the difference in threshold voltage and temperature coefficient of transistors, which shows the difference in threshold voltage between enhancement-mode GaN HEMT transistors with a channel length of 0.25 μm and a channel length of 1 μm.

[0095] In some embodiments of the present invention, optionally,

[0096] The channel length d3 of the third transistor M3 and the fourth transistor M4 satisfies: 0.9 μm≤d3≤1.1 μm.

[0097] The channel lengths d1 and d2 can satisfy the requirement that the threshold voltage of the first transistor M1 is smaller than the threshold voltage of the second transistor M2 (i.e., V TH1 <V TH2 ), ensuring the physical properties of the transistor are stable and the manufacturing cost is low. Correspondingly, the channel length of the above d3 can be set to be smaller than the channel length of the fourth transistor M4, so that the threshold voltage value of the third transistor M3 is equal to the threshold voltage value of the fourth transistor M4, that is, V TH3 =V TH4 .

[0098] In some embodiments of the present invention, optionally, see Figure 3 As shown, at least one of the first transistor M1 , the second transistor M2 , the third transistor M3 , and the fourth transistor M4 includes an enhancement mode (E-mode) gallium nitride HEMT transistor.

[0099] See also Figure 3 As shown, the enhancement mode gallium nitride HEMT transistor can be formed by p-GaN / gate-metal stacking. The first resistor unit R1 and the second resistor unit R2 can be metal resistors or active region resistors, such as TiN, AlCu, 2DEG, etc.

[0100] In the existing voltage reference circuit design, the reference voltage is designed by using the characteristics that the VBE (base-emitter voltage) of the BJT (bipolar junction transistor) device has a negative temperature coefficient and the base-emitter difference is proportional to the absolute temperature. BJT is a traditional silicon-based transistor, using BiCMOS (bimetal oxide semiconductor) or BCD (monolithic integration) technology, resulting in a complex voltage reference circuit structure, a large layout, and high power consumption. Based on this, the embodiment of the present invention adopts an enhanced gallium nitride HEMT transistor, especially the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all enhanced gallium nitride HEMT transistors, which can achieve a simpler structure, a smaller layout area, and lower power consumption than traditional silicon-based transistors. Actual test results show that the static current can reach 0.67μA, the input voltage is 5V, and the power is 3.35μW, which is superior to the performance of the voltage reference circuit based on the traditional silicon-based crystal.

[0101] In addition, the embodiment of the present invention uses an enhanced-mode gallium nitride HEMT transistor to arrange the voltage reference circuit, and also achieves a better low-temperature drift characteristic than the traditional silicon-based transistor arrangement voltage reference circuit. In particular, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all enhanced-mode gallium nitride HEMT transistors. The actual test results show that when the reference voltage is 0.743V at room temperature, the reference voltage drift is ≤5.4mV in the range of -50℃-150℃, and the temperature coefficient is 36ppm / ℃, which has a better low-temperature drift characteristic than the voltage reference circuit based on the traditional silicon-based crystal.

[0102] In addition, the reference voltage designed using BJT devices also needs to use an operational amplifier for potential clamping. Setting an operational amplifier for voltage clamping also makes the voltage reference circuit structure complex and the layout area large. In the embodiment of the present invention, when the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all enhancement-mode gallium nitride HEMT transistors, no operational amplifier is required for voltage clamping, and the structure is simple. Not setting an operational amplifier also reduces the failure rate, and the voltage reference circuit of the embodiment of the present invention has a long service life.

[0103] In some embodiments of the present invention, optionally, see Figure 2 and Figure 3 As shown, the bias subcircuit includes: a fifth transistor M5;

[0104] A gate of the fifth transistor M5 is coupled to a power source; a first electrode of the fifth transistor M5 is coupled to a ground terminal GND; and a second electrode of the fifth transistor M5 is coupled to the first node 102 .

[0105] In the embodiment of the present invention, the fifth transistor M5 is used to provide the bias current, which can ensure that the bias current has high stability, which is conducive to the voltage reference circuit outputting a stable reference voltage. In addition, in some embodiments, the fifth transistor M5 is an enhanced gallium nitride HEMT transistor, which is conducive to reducing the layout area and power consumption of the voltage reference circuit; and can reduce the interference of temperature on the bias current, ensuring that the reference voltage output by the voltage reference circuit has a low temperature drift characteristic.

[0106] In some embodiments of the present invention, optionally,

[0107] The bias subcircuit includes: a resistor unit;

[0108] A first terminal of the resistor unit is coupled to a power source and a first node 102 respectively; a second terminal of the resistor unit is coupled to a ground terminal GND.

[0109] In the embodiment of the present invention, a resistor unit is used to provide a bias current, which can effectively reduce the layout cost of the voltage reference circuit. The low cost is conducive to the large-scale application of the voltage reference circuit.

[0110] In some embodiments of the present invention, optionally, see Figure 2 and Figure 3 As shown, the voltage reference circuit further includes: a first resistance unit R1 and a second resistance unit R2;

[0111] A first end of the first resistor unit R1 is coupled to a gate of the first transistor M1, a gate of the second transistor M2, and a second electrode of the second transistor M2, respectively, and a second end of the first resistor unit R1 is coupled to a power source;

[0112] A first end of the second resistance unit R2 is coupled to the gate of the third transistor M3 , the gate of the fourth transistor M4 , and the second electrode of the fourth transistor M4 , respectively. A second end of the second resistance unit R2 is coupled to a power source.

[0113] In the embodiment of the present invention, by arranging the first resistance unit R1 and the second resistance unit R2, combined with the high resistance setting of the first resistance unit R1 and the second resistance unit R2, it is possible to ensure that the current connected to the first transistor, the second transistor, the third transistor and the fourth transistor is in the subthreshold current range, that is, the first transistor, the second transistor, the third transistor and the fourth transistor are in a subthreshold state. High resistance is to achieve the resistance value of the current connected to the first transistor, the second transistor, the third transistor and the fourth transistor in the subthreshold current range. Since transistors are affected by manufacturing processes and manufacturing tolerances, and the reference voltage to be output in the actual application process of the embodiment of the present invention is different due to demand, the first resistance unit R1 and the second resistance unit R2 cannot give a specific resistance value range here. It should be noted that the absence of a specific resistance value range should not be considered unclear.

[0114] An embodiment of the present invention provides a method for generating a reference voltage, which is applied to a voltage reference circuit of any embodiment of the present invention. The method includes:

[0115] The bias subcircuit generates a bias current;

[0116] The negative temperature subcircuit generates a first voltage having a negative temperature coefficient;

[0117] The positive temperature subcircuit generates a second voltage with a positive temperature coefficient, and is further used to obtain a reference voltage with a zero temperature coefficient according to the first voltage and the second voltage, and transmit the reference voltage to the reference voltage output terminal 101 .

[0118] An embodiment of the present invention provides an electronic device, comprising the voltage reference circuit of any one of the embodiments of the present invention.

[0119] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A voltage reference circuit, characterized in that: include: A bias subcircuit, a negative temperature subcircuit, a positive temperature subcircuit, a first node, a power supply terminal, a ground terminal and a reference voltage output terminal; A bias subcircuit, coupled to the first node, the power supply terminal and the ground terminal respectively, for generating a bias current; A negative temperature sub-circuit, coupled to the power supply terminal, the ground terminal and the first node respectively, for generating a first voltage with a negative temperature coefficient; A positive temperature sub-circuit is coupled to the power supply terminal, the first node and the reference voltage output terminal respectively, and is used to generate a second voltage with a positive temperature coefficient, and is also used to obtain a reference voltage with a zero temperature coefficient based on the first voltage and the second voltage, and transmit the reference voltage to the reference voltage output terminal.

2. The voltage reference circuit according to claim 1, wherein: The negative temperature subcircuit comprises: a first transistor and a second transistor; The positive temperature sub-circuit comprises: a third transistor and a fourth transistor; The gate of the first transistor is coupled to the power supply, the first electrode of the first transistor is coupled to the ground terminal; the second electrode of the first transistor is coupled to the first node; The gate of the second transistor and the drain of the second transistor are both coupled to the power supply; the source of the second transistor is coupled to the first node; The gate of the third transistor is coupled to the power supply; the source of the third transistor is coupled to the first node; the drain of the third transistor is coupled to the reference voltage output terminal; The gate of the fourth transistor and the drain of the fourth transistor are both coupled to the power supply; the source of the fourth transistor is coupled to the reference voltage output terminal; Among them, the threshold voltage value of the first transistor is less than the threshold voltage value of the second transistor, the threshold voltage value of the third transistor is equal to the threshold voltage value of the fourth transistor; the width-to-length ratio of the second transistor is less than the width-to-length ratio of the first transistor; the width-to-length ratio of the fourth transistor is greater than the width-to-length ratio of the third transistor; the first transistor, the second transistor, the third transistor and the fourth transistor are in a subthreshold state.

3. The voltage reference circuit according to claim 2, characterized in that: The channel length of the first transistor is smaller than the channel length of the second transistor, and / or, A channel length of the third transistor is equal to a channel length of the fourth transistor.

4. The voltage reference circuit according to claim 3, characterized in that: The channel length d1 of the first transistor satisfies: 0.15 μm≤d1≤0.35 μm; and / or, The channel length d2 of the second transistor satisfies: 0.9 μm≤d2≤1.1 μm; and / or, The channel length d3 of the third transistor and the fourth transistor satisfies: 0.9 μm≤d3≤1.1 μm.

5. The voltage reference circuit according to claim 2, wherein: At least one of the first transistor, the second transistor, the third transistor, and the fourth transistor includes an enhancement mode gallium nitride HEMT transistor.

6. The voltage reference circuit according to claim 1 or 2, characterized in that: The bias subcircuit includes: a fifth transistor; The gate of the fifth transistor is coupled to the power supply; the first electrode of the fifth transistor is coupled to the ground terminal; and the second electrode of the fifth transistor is coupled to the first node.

7. The voltage reference circuit according to claim 1 or 2, characterized in that: The bias subcircuit includes: a resistor unit; The first end of the resistance unit is coupled to the power source and the first node respectively; the second end of the resistance unit is coupled to the ground end.

8. The voltage reference circuit according to claim 2, characterized in that: Also includes: a first resistance unit and a second resistance unit; The first end of the first resistor unit is coupled to the gate of the first transistor, the gate of the second transistor, and the second electrode of the second transistor respectively, and the second end of the first resistor unit is coupled to the power source; A first end of the second resistance unit is coupled to the gate of the third transistor, the gate of the fourth transistor, and the second electrode of the fourth transistor respectively, and a second end of the second resistance unit is coupled to the power source.

9. A method for generating a reference voltage, applied to the voltage reference circuit according to any one of claims 1 to 8, characterized in that: The bias subcircuit generates a bias current; The negative temperature subcircuit generates a first voltage having a negative temperature coefficient; The positive temperature subcircuit generates a second voltage with a positive temperature coefficient, and is further used to obtain a reference voltage with a zero temperature coefficient according to the first voltage and the second voltage, and transmit the reference voltage to the reference voltage output terminal.

10. An electronic device, characterized in that: The invention comprises the voltage reference circuit as claimed in any one of claims 1 to 8.

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