High-order curvature compensation band-gap reference circuit

Abstract

The invention discloses a high-order curvature compensation band-gap reference circuit. The high-order curvature compensation band-gap reference circuit comprises a first-order band-gap reference circuit, a high-temperature area curvature compensation circuit and a starting circuit. The first-order band-gap reference voltage is realized by adopting the technologies that the voltage generated by the current of a PMOS (P-channel Metal Oxide Semiconductor) tube M4 on resistors R3 to R4 and the voltage generated by the current of a PMOS tube M6 on the resistor R4 have positive temperature coefficients, and the voltage generated by the current of a PMOS tube M5 on the resistors R3 to R4 and the voltage generated by the current of a PMOS tube M7 on the resistor R4 have negative temperature coefficients. The technology that the grid voltage of an NMOS tube M12 is increased along with temperature rise to control an NMOS tube M13 to work, and the working area of the NMOS tube M13 is gradually transited to a saturation area from a deep triode area and a triode area along with temperature rise is utilized, so that the current of a PMOS tube M14 is in temperature high-order nonlinearity, and temperature compensation is performed on first-order band-gap reference voltage; therefore, the band-gap-based voltage with high-order temperature compensation is obtained.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a high-order curvature compensation bandgap reference circuit. Background Art

[0002] The bandgap reference circuit is an important module of the integrated circuit system. The bandgap reference circuit mainly provides accurate reference voltage for the integrated circuit system, so its performance characteristics directly affect the overall performance of the integrated circuit system, which requires improving the performance characteristics of the bandgap reference circuit. Figure 1 It is a traditional reference circuit structure. PMOS tubes M1, M2 and M3 have the same channel width-to-length ratio. The emitter area of ​​PNP transistor Q2 is N times that of PNP transistor Q1. Resistors R1 and R2 are made of the same material. The output voltage V REF for Where q is the charge of the electron, k is the Boltzmann constant, T is the absolute temperature, V EB3 is the emitter-base voltage of PNP transistor Q3, N is the ratio of the emitter area of ​​PNP transistor Q2 to that of PNP transistor Q1, R 1 is the impedance of resistor R1, R 2 is the impedance of resistor R2. By optimizing the relevant parameters of the resistor, a low temperature drift reference voltage V can be obtained within a certain temperature range. REF Since the emitter-base voltage of the PNP transistor has temperature nonlinearity, the output voltage of the traditional first-order bandgap reference circuit has a high temperature drift coefficient problem, which greatly limits the application of the traditional first-order bandgap reference circuit in high-precision systems. Summary of the invention

[0003] The present invention aims to solve the above problems of the prior art. A high-order curvature compensation bandgap reference circuit is proposed. The technical solution of the present invention is as follows:

[0004] A high-order curvature compensation bandgap reference circuit comprises: a first-order bandgap reference circuit, a high-temperature region curvature compensation circuit and a start-up circuit, wherein the signal output end of the first-order bandgap reference circuit is respectively connected to the signal input ends of the high-temperature region curvature compensation circuit and the start-up circuit, the high-temperature region curvature compensation circuit is connected to the electrical signal input end of the first-order bandgap reference circuit, the signal output end of the start-up circuit is connected to the start-up signal input end of the first-order bandgap reference circuit, the first-order bandgap reference circuit generates a bandgap reference voltage; the start-up circuit enables the bandgap reference circuit to work normally and generate a bandgap reference voltage output, and the high-temperature region curvature compensation circuit compensates the bandgap reference voltage generated by the first-order bandgap reference circuit to obtain a bandgap reference voltage with a low temperature drift coefficient.

[0005] Furthermore, the first-order bandgap reference circuit includes: a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a PNP triode Q1, a PNP triode Q2, an amplifier OP1 and an amplifier OP2, wherein the source of the PMOS tube M1 is connected to the source of the PMOS tube M2, the source of the PMOS tube M3, the source of the PMOS tube M4, the source of the PMOS tube M The source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube M7 and the external power supply VDD are connected, the drain of the PMOS tube M1 is connected to the positive input terminal of the amplifier OP1 and one end of the resistor R1 respectively, the other end of the resistor R1 is connected to the collector of the PNP transistor Q1, the base of the PNP transistor Q1, the collector of the PNP transistor Q2, the base of the PNP transistor Q2, one end of the resistor R4 and the external ground wire GND respectively, the gate of the PMOS tube M1 is connected to the gate of the PMOS tube M5, the gate of the PMOS tube M6 and the gate of the PMOS tube M7 respectively. The gate of the MOS tube M7, the drain of the NMOS tube M15 and the output end of the amplifier OP1 are connected, the drain of the PMOS tube M2 is respectively connected to the inverting input end of the amplifier OP1, the inverting input end of the amplifier OP2 and the emitter of the PNP transistor Q1, and the gate of the PMOS tube M2 is respectively connected to the gate of the PMOS tube M3, the gate of the PMOS tube M4, the gate of the PMOS tube M6, the gate of the PMOS tube M8, the gate of the PMOS tube M9, the drain of the NMOS tube M16 and the input end of the amplifier OP2. The output ends of the circuit are connected, the drain of the PMOS tube M3 is respectively connected to the positive input end of the amplifier OP2 and one end of the resistor R2, the other end of the resistor R2 is connected to the emitter of the PNP transistor Q2, the drain of the PMOS tube M4 is respectively connected to the drain of the PMOS tube M5, the drain of the PMOS tube M14, one end of the resistor R3 and the circuit output end VREF, the other end of the resistor R3 is respectively connected to the other end of the resistor R4, the drain of the PMOS tube M6, the drain of the PMOS tube M7 and the gate of the NMOS tube M19.

[0006] Furthermore, the high temperature region curvature compensation circuit includes: a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, a PMOS tube M11, an NMOS tube M12, an NMOS tube M13, a PMOS tube M14, and a resistor R5, wherein the source of the PMOS tube M8 is respectively connected to the source of the PMOS tube M9, the source of the PMOS tube M11, the source of the PMOS tube M14, and the external power supply VDD, and the drain of the PMOS tube M8 is respectively connected to the gate of the NMOS tube M12 and one end of the resistor R5. The other end of the resistor R5 is respectively connected to the source of the NMOS tube M10, the source of the NMOS tube M13 and the external ground line GND, the drain of the PMOS tube M9 is respectively connected to the drain of the NMOS tube M10, the gate of the NMOS tube M10 and the gate of the NMOS tube M13, the drain of the PMOS tube M11 is respectively connected to the gate of the PMOS tube M11, the drain of the NMOS tube M12 and the gate of the PMOS tube M14, and the source of the NMOS tube M12 is connected to the drain of the NMOS tube M13.

[0007] Furthermore, the startup circuit includes: an NMOS tube M15, an NMOS tube M16, a PMOS tube M17, a PMOS tube M18 and an NMOS tube M19, wherein the source of the PMOS tube M17 is connected to the external ground line VDD, the gate of the PMOS tube M17 is respectively connected to the drain of the PMOS tube M17 and the source of the PMOS tube M18, the gate of the PMOS tube M18 is respectively connected to the drain of the PMOS tube M18, the gate of the NMOS tube M16, the gate of the NMOS tube M15 and the drain of the NMOS tube M19, and the source of the NMOS tube M15 is respectively connected to the source of the NMOS tube M16, the source of the NMOS tube M19 and the external ground line GND.

[0008] Furthermore, in the first-order bandgap reference circuit, the PMOS tube M2 and the PMOS tube M3 have the same channel width-to-length ratio, the emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1, and the low-frequency gain A of the amplifier OP1 and the amplifier OP2 is d A d >>1. PMOS tubes M1 and M5 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS tube M7 is α times that of PMOS tube M1, PMOS tubes M3 and M4 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS tube M6 is β times that of PMOS tube M2, and resistors R1, R2, R3 and R4 are made of the same material. Then the current in PMOS tubes M4, M5, M6 and M7 generates a voltage V on resistors R3 and R4. REF1 have Where R 1is the resistance value of resistor R1, R 2 is the resistance value of resistor R2, R 3 is the resistance value of resistor R3, R 4 is the resistance value of resistor R4, V EB1 is the emitter-base voltage of PNP transistor Q1, V T is the thermal voltage with a positive temperature coefficient, N is the ratio of the emitter area of ​​PNP transistor Q2 to that of PNP transistor Q1, α is the multiple of the channel width-to-length ratio of PMOS transistor M7 to that of PMOS transistor M1, and β is the multiple of the channel width-to-length ratio of PMOS transistor M6 to that of PMOS transistor M2. The emitter-base voltage V EB1 It has a negative temperature coefficient. Therefore, by optimizing the parameters of the corresponding MOS tubes and resistors, at the reference temperature T 0 Voltage V REF1 have Where T is the absolute temperature.

[0009] Furthermore, in the high temperature region curvature compensation circuit, the channel width-to-length ratio of the PMOS tube M8 is K of the PMOS tube M3. 1 times, the current I 8 The current I of PMOS tube M3 3 Yes 8 =K 1 I 3 , the gate voltage of NMOS tube M12 increases with the increase of temperature, and then as the temperature increases, NMOS tube M12 makes the working area of ​​NMOS tube M13 gradually transition from the deep triode area and triode area to the saturation area. PMOS tube M9 is exactly the same as PMOS tube M2, and the channel width-to-length ratio of PMOS tube M9 is K of PMOS tube M3. 2 times, the NMOS tube M10 and the NMOS tube M13 have the same channel width-to-length ratio. By optimizing the parameters of the MOS tube, the current I 11 for where μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 10 is the channel width-to-length ratio of the NMOS tube M10, (W / L) 13 is the channel width-to-length ratio of the NMOS tube M13, V D13 is the drain voltage of NMOS tube M13, V T is the thermovoltage with a positive temperature coefficient, K 2 is the ratio of the channel width to length ratio of the PMOS tube M9 to the PMOS tube M3, N is the ratio of the emitter area of ​​the PNP transistor Q2 to the PNP transistor Q1, T is the absolute temperature, T r1 、Tr2 With T 0 is the reference temperature, and T r2 >T r1 >T 0 The channel width-to-length ratio of the PMOS tube M14 is the K of the PMOS tube M11. 3 times, then the output voltage V REF V REF =V REF1 +(R 3 +R 4 )K 3 I 11 , where V REF1 is the voltage generated on the resistors R3 and R4 by the currents of the PMOS tubes M4, M5, M6 and M7, R 3 is the resistance value of resistor R3, R 4 is the resistance value of resistor R4, I 11 is the current of PMOS tube M11, K 3 The ratio of the channel width-to-length ratio of the PMOS tube M14 to the channel width-to-length ratio of the PMOS tube M11. 3 +R 4 )K 3 I 11 Temperature high-order nonlinearity can be effectively compensated by optimizing circuit parameters. REF1 The temperature nonlinearity and thus the low temperature drift coefficient of the bandgap reference voltage are improved.

[0010] The advantages and beneficial effects of the present invention are as follows:

[0011] The present invention provides a high-order curvature compensation bandgap reference circuit, adopts a technology that the voltage generated by the current of a PMOS tube M4 on a resistor R3 and a resistor R4 and the voltage generated by the current of a PMOS tube M6 on the resistor R4 are all positive temperature coefficient voltages, adopts a technology that the voltage generated by the current of a PMOS tube M5 on the resistor R3 and a resistor R4 and the voltage generated by the current of a PMOS tube M7 on the resistor R4 are all negative temperature coefficient voltages, performs weighted summation of the positive temperature coefficient voltage and the negative temperature coefficient voltage to generate a first-order bandgap reference voltage, utilizes a technology that the gate voltage of an NMOS tube M12 in a high-temperature region curvature compensation circuit increases with the temperature to control the operation of the NMOS tube M13 and enables the working area of ​​the NMOS tube M13 to gradually transition from a deep triode region and a triode region to a saturation region with the temperature increasing, so that the current of the PMOS tube M14 is high-order temperature nonlinear, and then performs temperature compensation on the first-order bandgap reference voltage, thereby obtaining a high-order temperature compensated bandgap base voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The present invention provides a preferred embodiment of a conventional first-order bandgap reference circuit schematic diagram;

[0013] Figure 2 A schematic diagram of a high-order curvature compensation bandgap reference circuit providing a preferred embodiment of the present invention;

[0014] Figure 3 The present invention provides a simulation diagram of the output voltage temperature characteristic of a high-order curvature compensated bandgap reference circuit according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0016] The technical solution of the present invention to solve the above technical problems is:

[0017] In the embodiment of the present application, a technology is adopted in which the voltage generated by the current of the PMOS tube M4 on the resistor R3 and the resistor R4 and the voltage generated by the current of the PMOS tube M6 on the resistor R4 are both positive temperature coefficient voltages, and a technology is adopted in which the voltage generated by the current of the PMOS tube M5 on the resistor R3 and the resistor R4 and the voltage generated by the current of the PMOS tube M7 on the resistor R4 are both negative temperature coefficient voltages, and the positive temperature coefficient voltage and the negative temperature coefficient voltage are weightedly summed to generate a first-order bandgap reference voltage, and the gate voltage of the NMOS tube M12 in the high-temperature region curvature compensation circuit increases with the increase of temperature to control the operation of the NMOS tube M13 and make the working area of ​​the NMOS tube M13 gradually transition from the deep triode region and the triode region to the saturation region with the increase of temperature, so that the current of the PMOS tube M14 is a high-order temperature nonlinearity, and then the first-order bandgap reference voltage is temperature compensated, so as to obtain a high-order temperature compensated bandgap base voltage.

[0018] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0019] Example

[0020] A high-order curvature compensated bandgap reference circuit, such as Figure 2 As shown, it includes a first-order bandgap reference circuit 1, a high-temperature region curvature compensation circuit 2 and a start-up circuit 3;

[0021] Among them, the signal output end of the first-order bandgap reference circuit 1 is respectively connected to the signal input end of the high-temperature area curvature compensation circuit 2 and the start-up circuit 3, the high-temperature area curvature compensation circuit 2 is connected to the electrical signal input end of the first-order bandgap reference circuit 1, and the signal output end of the start-up circuit 3 is connected to the start-up signal input end of the first-order bandgap reference circuit 1. The first-order bandgap reference circuit 1 generates a bandgap reference voltage; the start-up circuit 3 enables the bandgap reference circuit to work normally and generate a bandgap reference voltage output, and the high-temperature area curvature compensation circuit compensates for the bandgap reference voltage generated by the first-order bandgap reference circuit 1 to obtain a bandgap reference voltage with a low temperature drift coefficient.

[0022] The startup circuit 3 only works when the bandgap reference circuit is powered on. When the bandgap reference circuit is started up, the startup circuit stops working, thereby avoiding the influence of the startup circuit on the subsequent circuits.

[0023] As a preferred technical solution, Figure 2As shown, the first-order bandgap reference circuit 1 includes: a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a PNP triode Q1, a PNP triode Q2, an amplifier OP1 and an amplifier OP2, wherein the source of the PMOS tube M1 is connected to the source of the PMOS tube M2, the source of the PMOS tube M3, the source of the PMOS tube M4, the source of the PMOS tube M The source of the PMOS tube M5, the source of the PMOS tube M6, the source of the PMOS tube M7 and the external power supply VDD are connected, the drain of the PMOS tube M1 is connected to the positive input terminal of the amplifier OP1 and one end of the resistor R1 respectively, the other end of the resistor R1 is connected to the collector of the PNP transistor Q1, the base of the PNP transistor Q1, the collector of the PNP transistor Q2, the base of the PNP transistor Q2, one end of the resistor R4 and the external ground wire GND respectively, the gate of the PMOS tube M1 is connected to the gate of the PMOS tube M5, the gate of the PMOS tube M6 and the gate of the PMOS tube M7 respectively. The gate of the MOS tube M7, the drain of the NMOS tube M15 and the output end of the amplifier OP1 are connected, the drain of the PMOS tube M2 is respectively connected to the inverting input end of the amplifier OP1, the inverting input end of the amplifier OP2 and the emitter of the PNP transistor Q1, and the gate of the PMOS tube M2 is respectively connected to the gate of the PMOS tube M3, the gate of the PMOS tube M4, the gate of the PMOS tube M6, the gate of the PMOS tube M8, the gate of the PMOS tube M9, the drain of the NMOS tube M16 and the input end of the amplifier OP2. The output ends of the circuit are connected, the drain of the PMOS tube M3 is respectively connected to the positive input end of the amplifier OP2 and one end of the resistor R2, the other end of the resistor R2 is connected to the emitter of the PNP transistor Q2, the drain of the PMOS tube M4 is respectively connected to the drain of the PMOS tube M5, the drain of the PMOS tube M14, one end of the resistor R3 and the circuit output end VREF, the other end of the resistor R3 is respectively connected to the other end of the resistor R4, the drain of the PMOS tube M6, the drain of the PMOS tube M7 and the gate of the NMOS tube M19.

[0024] The high temperature area curvature compensation circuit 2 includes: a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, a PMOS tube M11, an NMOS tube M12, an NMOS tube M13, a PMOS tube M14, and a resistor R5, wherein the source of the PMOS tube M8 is respectively connected to the source of the PMOS tube M9, the source of the PMOS tube M11, the source of the PMOS tube M14 and the external power supply VDD, and the drain of the PMOS tube M8 is respectively connected to the gate of the NMOS tube M12 and one end of the resistor R5 The other end of the resistor R5 is respectively connected to the source of the NMOS tube M10, the source of the NMOS tube M13 and the external ground line GND, the drain of the PMOS tube M9 is respectively connected to the drain of the NMOS tube M10, the gate of the NMOS tube M10 and the gate of the NMOS tube M13, the drain of the PMOS tube M11 is respectively connected to the gate of the PMOS tube M11, the drain of the NMOS tube M12 and the gate of the PMOS tube M14, and the source of the NMOS tube M12 is connected to the drain of the NMOS tube M13.

[0025] The startup circuit 3 includes: an NMOS tube M15, an NMOS tube M16, a PMOS tube M17, a PMOS tube M18 and an NMOS tube M19, wherein the source of the PMOS tube M17 is connected to the external ground line VDD, the gate of the PMOS tube M17 is respectively connected to the drain of the PMOS tube M17 and the source of the PMOS tube M18, the gate of the PMOS tube M18 is respectively connected to the drain of the PMOS tube M18, the gate of the NMOS tube M16, the gate of the NMOS tube M15 and the drain of the NMOS tube M19, and the source of the NMOS tube M15 is respectively connected to the source of the NMOS tube M16, the source of the NMOS tube M19 and the external ground line GND.

[0026] The amplifier OP1 and the amplifier OP2 in the high-order curvature compensation bandgap reference circuit are prior art.

[0027] In the first-order bandgap reference circuit 1, the PMOS tube M2 and the PMOS tube M3 have the same channel width-to-length ratio, the emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1, and the low-frequency gain A of the amplifier OP1 and the amplifier OP2 is d A d >>1, then the current I of PMOS tube M1 1 The current I of PMOS tube M3 3 for

[0028]

[0029] In the formula, R 1 is the resistance value of resistor R1, R 2 is the resistance value of resistor R2, V EB1is the emitter-base voltage of PNP transistor Q1, V T is a thermal voltage with a positive temperature coefficient, N is the ratio of the emitter area of ​​the PNP transistor Q2 to that of the PNP transistor Q1. PMOS tubes M1 and M5 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS tube M7 is α times that of PMOS tube M1, PMOS tubes M3 and M4 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS tube M6 is β times that of PMOS tube M2, and resistors R1, R2, R3 and R4 are made of the same material, then the voltage V generated by the current in PMOS tubes M4, M5, M6 and M7 on resistors R3 and R4 is REF1 have

[0030]

[0031] In the formula, R 1 is the resistance value of resistor R1, R 2 is the resistance value of resistor R2, R 3 is the resistance value of resistor R3, R 4 is the resistance value of resistor R4, V EB1 is the emitter-base voltage of PNP transistor Q1, V T is the thermal voltage with a positive temperature coefficient, N is the ratio of the emitter area of ​​PNP transistor Q2 to that of PNP transistor Q1, α is the multiple of the channel width-to-length ratio of PMOS transistor M7 to that of PMOS transistor M1, and β is the multiple of the channel width-to-length ratio of PMOS transistor M6 to that of PMOS transistor M2. Among them, the emitter-base voltage V EB1 It has a negative temperature coefficient. Therefore, by optimizing the parameters of the corresponding MOS tubes and resistors, at the reference temperature T 0 Voltage V REF1 have Where T is the absolute temperature.

[0032] In the high temperature region curvature compensation circuit 2, the channel width-to-length ratio of the PMOS tube M8 is K of the PMOS tube M3. 1 times, then the gate voltage of NMOS tube M12 is V G12 for

[0033]

[0034] In the formula, R 2 is the resistance value of resistor R2, R 5 is the resistance value of resistor R5, K 1 The channel width-to-length ratio of the PMOS tube M8 is a multiple of that of the PMOS tube M3. Tis the thermal voltage with a positive temperature coefficient, and N is the ratio of the emitter area of ​​the PNP transistor Q2 to that of the PNP transistor Q1. The gate voltage V G12 As the temperature increases, the NMOS tube M12 makes the working area of ​​the NMOS tube M13 gradually transition from the deep triode area and the triode area to the saturation area. The PMOS tube M9 is exactly the same as the PMOS tube M2. The channel width-to-length ratio of the PMOS tube M9 is K of the PMOS tube M3. 2 times, the NMOS tube M10 and the NMOS tube M13 have the same channel width-to-length ratio. By optimizing the parameters of the MOS tube, the current I 11 for

[0035]

[0036] where μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 10 is the channel width-to-length ratio of the NMOS tube M10, (W / L) 13 is the channel width-to-length ratio of the NMOS tube M13, V D13 is the drain voltage of NMOS tube M13, V T is the thermovoltage with a positive temperature coefficient, K 2 is the ratio of the channel width to length ratio of the PMOS tube M9 to the PMOS tube M3, and N is the channel width to length ratio of the PNP transistor Q 2 With PNP transistor Q 1 The ratio of the emitter area, T is the absolute temperature, T r1 、T r2 With T 0 is the reference temperature, and T r2 >T r1 >T 0 The channel width-to-length ratio of the PMOS tube M14 is the K of the PMOS tube M11. 3 times, then the output voltage V REF for

[0037] V REF =V REF1 +(R 3 +R 4 )K 3 I 11 (6)

[0038] Where V REF1 is the voltage generated on the resistors R3 and R4 by the currents of the PMOS tubes M4, M5, M6 and M7, R 3is the resistance value of resistor R3, R 4 is the resistance value of resistor R4, I 11 is the current of PMOS tube M11, K 3 is the ratio of the channel width-to-length ratio of the PMOS tube M14 to the channel width-to-length ratio of the PMOS tube M11. 3 +R 4 )K 3 I 11 Temperature high-order nonlinearity can be effectively compensated by optimizing circuit parameters. REF1 The temperature nonlinearity and thus the low temperature drift coefficient of the bandgap reference voltage are improved.

[0039] Figure 3 is the output voltage V of a high-order curvature compensation bandgap reference circuit of the present invention REF The temperature characteristic simulation curve of the bandgap reference circuit is shown in Figure 1, where the horizontal axis is the temperature T and the vertical axis is the output voltage of the bandgap reference circuit. The simulation results show that within the temperature range of -40℃ to 125℃, the output voltage V REF The temperature coefficient is only 6.83ppm / ℃.

[0040] In the above embodiment of the present application, a high-order curvature compensation bandgap reference circuit includes a first-order bandgap reference circuit, a high-temperature region curvature compensation circuit and a startup circuit. The embodiment of the present application adopts a technology that the voltage generated by the current of the PMOS tube M4 on the resistor R3 and the resistor R4 and the voltage generated by the current of the PMOS tube M6 on the resistor R4 are both positive temperature coefficient voltages, and adopts a technology that the voltage generated by the current of the PMOS tube M5 on the resistor R3 and the resistor R4 and the voltage generated by the current of the PMOS tube M7 on the resistor R4 are both negative temperature coefficient voltages, and the positive temperature coefficient voltage and the negative temperature coefficient voltage are weighted and summed to generate a first-order bandgap reference voltage, and the gate voltage of the NMOS tube M12 in the high-temperature region curvature compensation circuit increases with the increase of temperature to control the operation of the NMOS tube M13 and make the working area of ​​the NMOS tube M13 gradually transition from the deep triode region and the triode region to the saturation region with the increase of temperature, so that the current of the PMOS tube M14 is a temperature high-order nonlinearity, and then the first-order bandgap reference voltage is temperature compensated, so as to obtain a high-order temperature compensated bandgap base voltage.

[0041] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high-order curvature compensation bandgap reference circuit, characterized in that: include: A first-order bandgap reference circuit (1), a high-temperature region curvature compensation circuit (2) and a start-up circuit (3), wherein the signal output end of the first-order bandgap reference circuit (1) is respectively connected to the signal input ends of the high-temperature region curvature compensation circuit (2) and the start-up circuit (3); the high-temperature region curvature compensation circuit (2) is connected to the electrical signal input end of the first-order bandgap reference circuit (1); the signal output end of the start-up circuit (3) is connected to the start-up signal input end of the first-order bandgap reference circuit (1); the first-order bandgap reference circuit (1) generates a bandgap reference voltage; the start-up circuit (3) enables the bandgap reference circuit to work normally and generate a bandgap reference voltage output; the high-temperature region curvature compensation circuit (2) compensates the bandgap reference voltage generated by the first-order bandgap reference circuit (1) to obtain a bandgap reference voltage with a low temperature drift coefficient.

2. A high-order curvature compensation bandgap reference circuit according to claim 1, characterized in that: The first-order bandgap reference circuit (1) comprises: a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, a PMOS tube M4, a PMOS tube M5, a PMOS tube M6, a PMOS tube M7, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a PNP triode Q1, a PNP triode Q2, an amplifier OP1 and an amplifier OP2, wherein the source of the PMOS tube M1 is respectively connected to the source of the PMOS tube M2, the source of the PMOS tube M3, the source of the PMOS tube M4, the source of the PMOS tube M5 The source of the PMOS tube M6, the source of the PMOS tube M7 and the external power supply VDD are connected, the drain of the PMOS tube M1 is connected to the positive input terminal of the amplifier OP1 and one end of the resistor R1, the other end of the resistor R1 is connected to the collector of the PNP transistor Q1, the base of the PNP transistor Q1, the collector of the PNP transistor Q2, the base of the PNP transistor Q2, one end of the resistor R4 and the external ground wire GND, the gate of the PMOS tube M1 is connected to the gate of the PMOS tube M5, the gate of the PMOS tube M6 and the gate of the PMOS tube M7. The gate of the OS transistor M7, the drain of the NMOS transistor M15 and the output end of the amplifier OP1 are connected, the drain of the PMOS transistor M2 is respectively connected to the inverting input end of the amplifier OP1, the inverting input end of the amplifier OP2 and the emitter of the PNP transistor Q1, and the gate of the PMOS transistor M2 is respectively connected to the gate of the PMOS transistor M3, the gate of the PMOS transistor M4, the gate of the PMOS transistor M6, the gate of the PMOS transistor M8, the gate of the PMOS transistor M9, the drain of the NMOS transistor M16 and the input end of the amplifier OP2. The output ends of the circuit are connected, the drain of the PMOS tube M3 is respectively connected to the positive input end of the amplifier OP2 and one end of the resistor R2, the other end of the resistor R2 is connected to the emitter of the PNP transistor Q2, the drain of the PMOS tube M4 is respectively connected to the drain of the PMOS tube M5, the drain of the PMOS tube M14, one end of the resistor R3 and the circuit output end VREF, the other end of the resistor R3 is respectively connected to the other end of the resistor R4, the drain of the PMOS tube M6, the drain of the PMOS tube M7 and the gate of the NMOS tube M19.

3. The high-order curvature compensation bandgap reference circuit according to claim 1, characterized in that: The high temperature region curvature compensation circuit (2) comprises: a PMOS tube M8, a PMOS tube M9, an NMOS tube M10, a PMOS tube M11, an NMOS tube M12, an NMOS tube M13, a PMOS tube M14, and a resistor R5, wherein the source of the PMOS tube M8 is respectively connected to the source of the PMOS tube M9, the source of the PMOS tube M11, the source of the PMOS tube M14 and an external power supply VDD, and the drain of the PMOS tube M8 is respectively connected to the gate of the NMOS tube M12 and one end of the resistor R5. The other end of the resistor R5 is respectively connected to the source of the NMOS tube M10, the source of the NMOS tube M13 and the external ground line GND, the drain of the PMOS tube M9 is respectively connected to the drain of the NMOS tube M10, the gate of the NMOS tube M10 and the gate of the NMOS tube M13, the drain of the PMOS tube M11 is respectively connected to the gate of the PMOS tube M11, the drain of the NMOS tube M12 and the gate of the PMOS tube M14, and the source of the NMOS tube M12 is connected to the drain of the NMOS tube M13.

4. The high-order curvature compensation bandgap reference circuit according to claim 1, characterized in that: The startup circuit (3) comprises: an NMOS tube M15, an NMOS tube M16, a PMOS tube M17, a PMOS tube M18 and an NMOS tube M19, wherein the source of the PMOS tube M17 is connected to an external power supply VDD, the gate of the PMOS tube M17 is respectively connected to the drain of the PMOS tube M17 and the source of the PMOS tube M18, the gate of the PMOS tube M18 is respectively connected to the drain of the PMOS tube M18, the gate of the NMOS tube M16, the gate of the NMOS tube M15 and the drain of the NMOS tube M19, and the source of the NMOS tube M15 is respectively connected to the source of the NMOS tube M16, the source of the NMOS tube M19 and an external ground line GND.

5. The high-order curvature compensation bandgap reference circuit according to claim 2, characterized in that: In the first-order bandgap reference circuit (1), the PMOS transistor M2 and the PMOS transistor M3 have the same channel width-to-length ratio, the emitter area of ​​the PNP transistor Q2 is N times that of the PNP transistor Q1, and the low-frequency gain A of the amplifier OP1 and the amplifier OP2 is d Yes d >>1. PMOS tubes M1 and M5 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS tube M7 is α times that of PMOS tube M1, PMOS tubes M3 and M4 have the same channel width-to-length ratio, the channel width-to-length ratio of PMOS tube M6 is β times that of PMOS tube M2, and resistors R1, R2, R3 and R4 are made of the same material. Then the current in PMOS tubes M4, M5, M6 and M7 generates a voltage V on resistors R3 and R4. REF1 have Where R1 is the resistance value of resistor R1, R2 is the resistance value of resistor R2, R3 is the resistance value of resistor R3, R4 is the resistance value of resistor R4, V EB1 is the emitter-base voltage of PNP transistor Q1, V T is the thermal voltage with a positive temperature coefficient, N is the ratio of the emitter area of ​​PNP transistor Q2 to that of PNP transistor Q1, α is the channel width-to-length ratio of PMOS transistor M7, which is α times that of PMOS transistor M1, and β is the channel width-to-length ratio of PMOS transistor M6, which is β times that of PMOS transistor M2. The emitter-base voltage V EB1 It has a negative temperature coefficient. Therefore, by optimizing the parameters of the corresponding MOS tubes and resistors, the voltage V at the reference temperature T0 is REF1 have Where T is the absolute temperature.

6. The high-order curvature compensation bandgap reference circuit according to claim 3, characterized in that: In the high temperature region curvature compensation circuit (2), the channel width-to-length ratio of the PMOS tube M8 is K1 times that of the PMOS tube M3, and the current I8 of the PMOS tube M8 and the current I3 of the PMOS tube M3 are I8=K1I3, then the gate voltage of the NMOS tube M12 increases with the increase of temperature, and then with the increase of temperature, the NMOS tube M12 makes the working area of ​​the NMOS tube M13 gradually transition from the deep triode area and the triode area to the saturation area, so that the current of the PMOS tube M11 is a temperature high-order nonlinearity. The PMOS tube M9 is exactly the same as the PMOS tube M2, and the channel width-to-length ratio of the PMOS tube M9 is K2 times that of the PMOS tube M3. The NMOS tube M10 and the NMOS tube M13 have the same channel width-to-length ratio. By optimizing the parameters of the MOS tubes, the current I of the PMOS tube M11 11 for where μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, (W / L) 10 is the channel width-to-length ratio of the NMOS tube M10, (W / L) 13 is the channel width-to-length ratio of the NMOS tube M13, V T is the thermal voltage with a positive temperature coefficient, K2 is the ratio of the channel width to length ratio of the PMOS tube M9 and the PMOS tube M3, N is the ratio of the emitter area of ​​the PNP transistor Q2 and the PNP transistor Q1, V D13 is the drain voltage of NMOS tube M13, R2 is the resistance value of resistor R2, T is the absolute temperature, T r1 , T r2 With T0 as the reference temperature, and T r2 >T r1 >T0.

7. A high-order curvature compensated bandgap reference circuit according to any one of claims 5 to 6, characterized in that: The channel width-to-length ratio of the PMOS tube M14 is K3 times that of the PMOS tube M11. Then the output voltage V REF V REF =V REF +(R3+R4)K3I 11 , where V REF1 is the voltage generated on the resistors R3 and R4 by the currents of the PMOS tubes M4, M5, M6 and M7, R3 is the resistance value of the resistor R3, R4 is the resistance value of the resistor R4, I 11 is the current of the PMOS tube M11, and K3 is the ratio of the channel width-to-length ratio of the PMOS tube M14 to the channel width-to-length ratio of the PMOS tube M11. Factor (R3+R4)K3I 11 Temperature high-order nonlinearity can be effectively compensated by optimizing circuit parameters. REF1 The temperature nonlinearity of the bandgap reference voltage is reduced, thereby generating a low temperature drift coefficient.

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