Current source circuit and communication chip

Abstract

The invention provides a current source circuit and a communication chip. The current source circuit comprises a current source unit and a current processing unit which are connected in sequence, the current source unit is used for providing current; the current processing unit comprises a first voltage dividing element, a first transistor, a second transistor, a third transistor and a first operational amplifier; one end of the first voltage dividing element is connected with the output end of the current source unit, and the other end is connected with the drain electrode of the first transistor and the positive input end of the first operational amplifier; the source electrode of the first transistor is connected with power supply voltage, and the grid electrode is connected with the grid electrode of the second transistor and one end of the first voltage-dividing element; the source electrode of the second transistor is connected with the power supply voltage, and the drain electrode is connected with the source electrode of the third transistor and the reverse input end of the first operational amplifier; the grid electrode of the third transistor is connected with the output end of the first operational amplifier, and the drain electrode serves as the output end of the current processing unit. According to the technical scheme, when the power supply voltage changes, the output current can be kept stable, and the precision is high.

Description

Technical Field

[0001] The present invention relates to the technical field of current sources, and in particular to a current source circuit and a communication chip. Background Art

[0002] With the continuous evolution of wireless communication technology, modulation technology is rapidly updated, and many cutting-edge technologies such as RU (multiple resource units), MLO (multi-link operation), and MU-MIMO (multiple input and multiple output) are introduced. The signal-to-noise ratio and linearity of communication systems are also more stringent. This means that the RF power amplifier in the communication system needs to have high linearity in a wider power range and be able to support the increasing signal packet length.

[0003] In an RF power amplifier, a precise bias current that does not vary with the power supply voltage is required to provide a suitable operating point so that the RF power amplifier can operate at high efficiency while maintaining high linearity.

[0004] A conventional CMOS current source is composed of an operational amplifier, a MOS transistor, and a resistor. In this structure, the reference voltage Vref connected to the operational amplifier has the characteristic of not changing with temperature and power supply voltage. The current generated by the conventional CMOS current source is in a certain proportional relationship with the reference voltage Vref. In theory, this structure can output a current that does not change with temperature and power supply voltage. However, due to the existence of the channel length modulation effect, when the power supply voltage changes, the drain-source voltage of the MOS transistor will also change, causing the current source output current Iref to deviate from the ideal value. Summary of the invention

[0005] The present invention provides a current source circuit and a communication chip to solve the problem that the current in the existing current source changes with the power supply voltage and the output is unstable.

[0006] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0007] According to a first aspect of the present invention, there is provided a current source circuit, comprising: a current source unit and a current processing unit connected in sequence; wherein:

[0008] The current source unit is used to provide current;

[0009] The current processing unit includes: a first voltage dividing element, a first transistor, a second transistor, a third transistor, and a first operational amplifier;

[0010] One end of the first voltage divider element is connected to the output end of the current source unit, and the other end thereof is interconnected with the drain of the first transistor and the positive input end of the first operational amplifier;

[0011] The source of the first transistor is connected to a power supply voltage, and the gate thereof is interconnected with the gate of the second transistor and one end of a first voltage dividing element;

[0012] The source of the second transistor is connected to a power supply voltage, and the drain thereof is interconnected with the source of the third transistor and the inverting input terminal of the first operational amplifier;

[0013] The gate of the third transistor is connected to the output end of the first operational amplifier, and the drain of the third transistor serves as the output end of the current processing unit.

[0014] Optionally, the maximum input voltage of the first operational amplifier is close to the power supply voltage.

[0015] Optionally, the voltage divider element includes: a fourth transistor; its drain serves as one end of the voltage divider element, its source serves as the other end of the voltage divider element; and its gate is also connected to its drain.

[0016] Optionally, the voltage-dividing element includes: a first resistor, one end of which serves as one end of the voltage-dividing element, and the other end of which serves as the other end of the voltage-dividing element.

[0017] Optionally, the current source unit includes: a second operational amplifier, a fifth transistor, and a second resistor; wherein,

[0018] The positive input terminal of the second operational amplifier is connected to the reference voltage, the negative input terminal thereof is connected to one end of the second resistor, and the output terminal thereof is connected to the gate of the fifth transistor;

[0019] The source of the fifth transistor is connected to one end of the second resistor, and the drain of the fifth transistor serves as the output end of the current source unit;

[0020] The other end of the second resistor is grounded;

[0021] The current source unit further includes: a current source, an output end of which is connected to one end of the second resistor; and the current source has a positive temperature coefficient.

[0022] Optionally, the current source unit further includes: a current mirror array connected between the output end of the current source and one end of the second resistor;

[0023] The current mirror array comprises:

[0024] a main transistor, whose drain is connected to the output end of the current source and whose drain is connected to the power supply voltage;

[0025] A plurality of mirror transistors, when connected, form a current mirror with the main transistor;

[0026] A plurality of switch control units correspond one to one with the mirror transistors and are used to control whether the mirror transistors are connected.

[0027] Optionally, the switch control unit includes:

[0028] a first switching element connected between the gate of the mirror transistor and the gate of the main transistor;

[0029] a second switching element connected between the gate of the mirror transistor and a power supply voltage;

[0030] The conduction signals of the first switch element and the second switch element are in anti-phase relationship with each other; specifically, when the first switch element is turned on and the second switch element is turned off, the corresponding mirror transistor is connected, and when the first switch element is turned off and the second switch element is turned on, the corresponding mirror transistor is not connected.

[0031] Optionally, also include:

[0032] An output buffer unit is connected to the output end of the current amplifying unit and is used to protect the current processing unit from being broken down when the current source unit is turned off.

[0033] Optionally, the output buffer unit includes: a sixth transistor, whose source is connected to the output end of the current processing unit, whose drain serves as the output end of the output buffer unit, and whose gate is connected to the bias circuit;

[0034] The bias circuit is used to provide a bias voltage for the gate of the sixth transistor; when the current source unit is working, the bias circuit is configured to make the sixth transistor in a deep linear region; when the current tube is turned off, the bias circuit is configured to make the sixth transistor in an off state.

[0035] Optionally, the output buffer unit further includes: a second voltage dividing element connected between the output end of the current source processing unit and the sixth transistor, or connected between the sixth transistor and the output end of the output buffer unit.

[0036] According to a second aspect of the present invention, there is provided a communication chip, comprising: a current source circuit as described in any one of the above items.

[0037] The current source circuit and communication chip provided by the present invention have a ratio between the output current processed by the current processing unit and the output current of the current source unit, which is the ratio of the equivalent resistance of the first transistor to the equivalent resistance of the second transistor; the positive input terminal and the reverse input terminal of the second operational amplifier are respectively connected to the drain of the first transistor and the drain of the second transistor, and the drain voltage of the first transistor and the drain voltage of the second transistor are clamped, and the positive input terminal and the reverse input terminal of the first operational amplifier are respectively connected to the drain of the first transistor and the drain of the second transistor, and the drain voltage of the first transistor and the drain voltage of the second transistor are clamped, so that the current flowing through the first transistor is proportionally amplified, and the influence of the channel length modulation effect is reduced; therefore, the output current processed by the current processing unit can remain constant when the power supply voltage changes, and has high precision; therefore, when it is applied to a radio frequency power amplifier, it can provide a more precise bias control for the radio frequency power amplifier, thereby improving the performance of the radio frequency power amplifier.

[0038] When the HBT tube in the RF power amplifier is working, the junction temperature will increase due to the self-heating effect of the transistor, which will seriously affect the performance; however, the output current Iref provided by the existing current source structure has a zero temperature coefficient characteristic, which makes it impossible to compensate when the junction temperature of the RF power amplifier increases. The power gain of the RF power amplifier will change with the increase of the junction temperature, and the output will be unstable; in an optional scheme of the present invention, by setting a current source in the current source unit, its output current has a certain positive temperature characteristic, and then the output current of the current source unit has a certain negative temperature characteristic. When the junction temperature increases, the bias current can be reduced to achieve temperature compensation, so that the junction temperature remains relatively stable, thereby achieving better dynamic EVM characteristics.

[0039] In an optional solution of the present invention, by setting a current mirror array in the current source unit, the number of connected mirror transistors can be controlled by a switch control unit, and then the current value of the current source unit and its negative temperature coefficient can be controlled; by controlling the negative temperature coefficient, the current source circuit can adapt to a wider range of temperature changes and achieve better temperature compensation.

[0040] In an optional solution of the present invention, by providing an output buffer unit at the output end of the current processing unit, the current processing unit can be protected from breakdown when the current source unit is turned off. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0042] Figure 1 is a schematic diagram of a current source circuit according to an embodiment of the present invention;

[0043] Figure 2 is a schematic diagram of a current source circuit according to an embodiment of the present invention;

[0044] Figure 3 is a schematic diagram of a current source circuit of a preferred embodiment of the present invention;

[0045] Figure 4 is a schematic diagram of a current source circuit according to an embodiment of the present invention;

[0046] Figure 5 is a schematic diagram of a current source circuit according to an embodiment of the present invention;

[0047] Figure 6 is a schematic diagram of a current source circuit of a preferred embodiment of the present invention;

[0048] Figure 7 is a schematic diagram of a current source and a current mirror array according to a preferred embodiment of the present invention;

[0049] Figure 8 is a schematic diagram of a current source circuit of a preferred embodiment of the present invention;

[0050] Fig. 9 is a schematic diagram of a current source circuit of a preferred embodiment of the present invention;

[0051] Fig.10 is a schematic diagram of a current source circuit of a preferred embodiment of the present invention;

[0052] Fig.11 is a schematic diagram of a current source circuit of a preferred embodiment of the present invention;

[0053] Fig.12 is a schematic diagram of a current source circuit of a preferred embodiment of the present invention;

[0054] Fig.13 is a schematic diagram of a current source circuit of a preferred embodiment of the present invention;

[0055] Description of reference numerals:

[0056] 10-current source unit;

[0057] 20-current processing unit;

[0058] 30-Current mirror array;

[0059] 40-Output buffer unit. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] In the description of the specification of the present invention, it is necessary to understand that the orientation or position relationship indicated by the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc. is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0062] In the description of the present specification, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0063] In the description of the present invention, "plurality" means a plurality, such as two, three, four, etc., unless otherwise clearly and specifically defined.

[0064] In the description of the present invention, unless otherwise clearly specified and limited, the term "connection" and other terms should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0065] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0066] As described in the background technology, the existing CMOS current source is composed of an operational amplifier, a MOS transistor and a resistor. In this structure, the reference voltage Vref connected to the operational amplifier has the characteristic of not changing with temperature and power supply voltage. The current generated by the CMOS current source is in a certain proportional relationship with the reference voltage Vref. In theory, the structure can output a current that does not change with temperature and power supply voltage. However, due to the existence of the channel length modulation effect, when the power supply voltage changes, the drain-source voltage of the MOS transistor will also change, so that the current source output current Iref deviates from the ideal value.

[0067] In view of this, the present invention provides a current source circuit, which includes: a current source unit 10 and a current processing unit 20 connected in sequence, please refer to Figure 1 .

[0068] The current source unit 10 is used to provide current.

[0069] The current processing unit 20 includes: a first voltage divider, a first transistor M1, a second transistor M2, a third transistor M3, and a first operational amplifier A1. One end of the first voltage divider is connected to the output end of the current source unit 10 (node ​​V1 in the figure), and the other end thereof is interconnected with the drain of the first transistor M1 and the positive input end of the first operational amplifier A1; that is, the other end of the voltage divider is connected to the drain of the first transistor, and the first operational positive input end is connected to the node V2 between the voltage divider and the first transistor. The source of the first transistor M1 is connected to the power supply voltage VCC, and its gate is interconnected with the gate of the second transistor and one end of the first voltage divider. The source of the second transistor M2 is connected to the power supply voltage VCC, and its drain is interconnected with the source of the third transistor M3 and the reverse input end of the first operational amplifier A1; that is, the drain of the second transistor M2 is connected to the source of the third transistor M3, and the reverse input end of the first operational amplifier A1 is connected to the node V3 between the second transistor M2 and the third transistor M3. The gate of the third transistor M3 is connected to the output terminal of the first operational amplifier A1 , and the drain of the third transistor M3 serves as the output terminal of the current processing unit 20 .

[0070] In the current source circuit provided by the above embodiment of the present invention, the first transistor is connected to the output end of the current source unit through the first voltage divider element. By properly setting the first voltage divider element, the first transistor M1 is in the linear region, which can be equivalent to a resistor R M1 , whose value can be expressed as:

[0071]

[0072] Among them, u p represents the mobility, C ox Represents the gate oxide capacitance per unit area, V effRepresents the overdrive voltage, W 1 Represents the transistor width, L 1 Represents the length of the transistor.

[0073] Furthermore, the positive input terminal of the first operational amplifier A1 is connected to the node V2 to generate a voltage V2, and the negative input terminal thereof is connected to the node V3 to generate a voltage V3. Therefore, the voltages of the nodes V2 and V3 are equal, that is,:

[0074] V2=V3

[0075] Furthermore, the source of the second transistor M2 is connected to the power supply voltage VCC, the drain thereof is connected to the node V3, and the gate thereof is connected to the gate of the first transistor and one end of the first voltage divider element; therefore, the second transistor M2 is also in the linear region and can be equivalent to a resistor R M2 , whose value can be expressed as:

[0076]

[0077] Among them, u p represents the mobility, C ox Represents the gate oxide capacitance per unit area, V eff Represents the overdrive voltage, W 2 Represents the transistor width, L 2 Represents the length of the transistor.

[0078] Furthermore, the first operational amplifier A1, the first transistor M1, the second transistor M2, and the third transistor M3 form a loop; the ratio of the current passing through the first transistor M1 to the current passing through the second transistor M2 is inversely proportional to the equivalent resistance value of the first transistor and the equivalent resistance value of the second transistor, that is,

[0079]

[0080] Therefore, the output current of the current source circuit (ie, the output current of the current processing unit) I out is the output current I of the current source unit 1 Linear change; when R M1 >R M2 When out For I 1 Linear amplification.

[0081] The first operational amplifier A1 clamps the voltages of the first node V1 and the second node V2, so that the currents on the proportional transistor equivalent resistors RM1 and RM2 are also proportional to each other, thereby making the output reference current I out It is only related to the ratio of the transistor equivalent resistance RM3 and RM4, so that the output current I outIt can keep constant when the power supply voltage VCC changes, has high accuracy, and avoids the influence of channel length modulation effect.

[0082] Furthermore, the first operational amplifier A1 is an amplifier having a certain gain A v1 , when the current source is working, the impedance looking upward from the drain of the third transistor is:

[0083] R M3 =g m3 r o2 r o3 A v1

[0084] Among them, g m3 is the transconductance of the third transistor M3, r o2 、r o3 are the output impedances of the second transistor M2 and the third transistor M3, A v1 is the gain of the first operational amplifier.

[0085] Furthermore, the first operational amplifier A1 increases the output impedance R of the current source. out , when the third transistor M3 enters the linear region due to excessive output swing, the output impedance R out It will not decay too quickly, thus further stabilizing the output current I out , increasing the output current accuracy.

[0086] In one embodiment, the voltage divider element may be in the form of a transistor, such as comprising: a fourth transistor M4; its drain serves as one end of the voltage divider element, its source serves as the other end of the voltage divider element; its gate is also connected to its drain, please refer to Figure 2 .

[0087] Preferably, when the voltage divider element is in the form of a transistor, a resistor R may be further provided between the drain of the transistor and the output end of the current source unit. Figure 3 , the gate oscillation signal of the transistor can be eliminated.

[0088] In another embodiment, the voltage divider element may be in the form of a resistor, such as comprising: a first resistor R1, one end of which serves as one end of the voltage divider element, and the other end of which serves as the other end of the voltage divider element, please refer to Figure 4 .

[0089] Preferably, the input voltage range of the first operational amplifier A1 is close to the power supply voltage VCC, so as to increase the swing of the output voltage.

[0090] In one embodiment, the current source unit 10 includes: a second operational amplifier A2, a fifth transistor M5, and a second resistor R2. Figure 5The positive input terminal of the second operational amplifier A2 is connected to the reference voltage Vref, the reverse input terminal is connected to one end of the second resistor R2, and the output terminal is connected to the gate of the fifth transistor M5. The source of the fifth transistor M5 is connected to one end of the second resistor R2, and the drain thereof serves as the output terminal of the current source unit. The other end of the second resistor is grounded.

[0091] Preferably, the reference voltage Vref connected to the non-inverting input terminal of the second operational amplifier A2 is configured to have a characteristic that does not change with changes in power supply voltage and temperature, which can be achieved by a bandgap reference circuit.

[0092] In a preferred embodiment, the current source unit 10 further includes: a current source Ip, whose output end is connected to one end of the second resistor R2, please refer to Figure 6 . This current source has a positive temperature coefficient.

[0093] In the above embodiment, when the current source circuit is working, M5 is turned on, the voltage of the reverse input terminal of the second operational amplifier A2 is the same as the voltage of its forward input terminal, one end of the second resistor R2 is connected to the reverse input terminal of the second operational amplifier A2, and the forward input terminal of the second operational amplifier A2 is connected to the reference voltage Vref; therefore, the voltage V R2 =Vref.

[0094] The output end of the current source Ip is connected to one end of the second resistor R2, and current is injected into the second resistor R2. At this time, the current on the second resistor R2 can be expressed as:

[0095] I R2 =I 1 +I p

[0096] The output current I of the first current source unit 10 1 It can be expressed as:

[0097]

[0098] The reference voltage Vref is a zero temperature coefficient voltage, and the output current Ip of the current source is a positive temperature coefficient current. Therefore, the output current Ip of the current source unit is 1 It has a negative temperature coefficient characteristic, which can reduce the bias current to achieve temperature compensation when the junction temperature of the RF power amplifier increases, so that the junction temperature remains relatively stable, thereby achieving better dynamic EVM characteristics.

[0099] In a preferred embodiment, the current source unit further includes: a current mirror array, see Figure 7The current mirror array includes: a main transistor M0, whose drain is connected to the output end of the current source IPTAT and the drain is connected to the power supply voltage Vdd; a plurality of mirror transistors M1'-MN', which, when the mirror transistor is connected, form a current mirror with the main transistor M0 to linearly copy the current of the current source; a plurality of switch control units, which correspond to the mirror transistors one by one and are used to control whether the mirror transistors are connected. The switch control unit can control the connection of different or different numbers of mirror transistors, and can achieve multiple current values ​​and negative temperature coefficients.

[0100] In one embodiment, the switch control unit includes: a first switch element S, a second switch element S′, see Figure 7 The plurality of mirror transistors M1'-MN' correspond to the plurality of first switch elements S1-SN and the plurality of second switch elements S1'-SN'. The first switch element S is connected between the gate of the mirror transistor M' and the gate of the main transistor M0; the second switch element S' is connected between the gate of the mirror transistor M' and the power supply voltage Vdd.

[0101] The implementation principle is: the conduction signals of the first switch element and the second switch element are in anti-phase relationship with each other; specifically, when the first switch element S is turned on and the second switch element S' is turned off, the corresponding mirror transistor is connected, and when the first switch element S is turned off and the second switch element S' is turned on, the corresponding mirror transistor is not connected.

[0102] In a preferred embodiment, the current source circuit further includes: an output buffer unit 40, please refer to Figure 8 It is used to protect the current processing unit from breakdown when the current source unit is turned off. Specifically, it can be realized by means of a switch element, which is turned on when the current source unit is working and turned off when the current source unit is turned off.

[0103] In one implementation, the output buffer unit may be implemented by a transistor, such as the sixth transistor M6, see Fig. 9 , its source is connected to the output end of the current processing unit, its drain is used as the output end of the output buffer unit, that is, the output end Iout of the current source circuit, and its gate is connected to the bias circuit. The bias circuit is used to provide a bias voltage Vb1 for the gate of the sixth transistor; when the current source unit is working, the bias circuit is configured to turn on the sixth transistor M6, preferably, M6 can be in a deep linear region, so as to minimize the impact on the output swing; when the current source unit is turned off, the bias circuit is configured to turn off the sixth transistor.

[0104] In practice, the bias circuit may include: a third resistor R3 connected between the gate and the source of the sixth transistor, see Fig.10When the current source unit is working, the bias circuit provides a bias voltage for the gate of the sixth transistor, so that the sixth transistor is in a deep linear region; when the current source unit is turned off, the bias circuit does not provide a bias voltage for the gate of the sixth transistor, and due to the effect of the third resistor, the gate and source voltages of the sixth transistor are equal, and the sixth transistor is in an off state.

[0105] In a preferred embodiment, the output buffer unit may include two or more cascaded transistors, which can provide a better and more reliable output buffering effect. Fig.11 As shown, two transistors are taken as an example. On the basis of the sixth transistor M6, a seventh transistor M7 is also included. The gate of the seventh transistor M7 is also connected to the bias circuit, and its source is connected to the drain of the sixth transistor M6, and its drain serves as the output end of the output buffer unit, that is, the output end Iout of the current source circuit. The bias circuit is also used to provide a bias voltage Vb2 for the gate of the seventh transistor; when the current source unit is working, the bias circuit is configured to turn on the seventh transistor M7, preferably, M7 can be in a deep linear region, so as to minimize the impact on the output swing; when the current source unit is turned off, the bias circuit is configured to turn off the seventh transistor M7.

[0106] In practice, the bias circuit may include: a fourth resistor R4 connected between the gate and the source of the seventh transistor, see Fig.12 When the current source unit is working, the bias circuit provides a bias voltage for the gate of the seventh transistor, so that the seventh transistor is in a deep linear region; when the current source unit is turned off, the bias circuit does not provide a bias voltage for the gate of the seventh transistor, and due to the effect of the fourth resistor, the gate and source voltages of the seventh transistor are equal, and the seventh transistor is in an off state.

[0107] In a preferred embodiment, the output buffer unit may further include: a second voltage dividing element, see Fig.13 , which is connected between the output terminal of the current processing unit and the sixth transistor M6.

[0108] In different embodiments, the second voltage dividing element may also be connected between the sixth transistor M6 and the output terminal Iout of the output buffer unit.

[0109] Preferably, the second voltage divider element can be implemented in the form of a transistor, that is, the output buffer unit includes two transistors connected in series. When the current source is turned off, the increase in the number of transistors connected in series in the output buffer unit can make the drain-source voltage distribution of each transistor more uniform, improve reliability, and make the current processing unit less likely to be broken down.

[0110] In different embodiments, the number of series-connected transistors in the output buffer unit may be more than two, which will not be described in detail here.

[0111] In different embodiments, the second voltage dividing element may also be implemented in the form of a resistor, a diode, etc.

[0112] In one embodiment, a communication chip is further provided, which includes the current source circuit described in any of the above embodiments.

[0113] In the description of this specification, the description with reference to the terms "an implementation", "an example", "a specific implementation process", "an example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A current source circuit, characterized in that: include: A current source unit and a current processing unit connected in sequence; wherein, The current source unit is used to provide current; The current processing unit includes: a first voltage dividing element, a first transistor, a second transistor, a third transistor, and a first operational amplifier; One end of the first voltage divider element is connected to the output end of the current source unit, and the other end thereof is interconnected with the drain of the first transistor and the positive input end of the first operational amplifier; The source of the first transistor is connected to a power supply voltage, and the gate thereof is interconnected with the gate of the second transistor and one end of a first voltage dividing element; The source of the second transistor is connected to a power supply voltage, and the drain thereof is interconnected with the source of the third transistor and the inverting input terminal of the first operational amplifier; The gate of the third transistor is connected to the output end of the first operational amplifier, and the drain of the third transistor serves as the output end of the current processing unit.

2. The current source circuit according to claim 1, characterized in that: The maximum input voltage of the first operational amplifier is close to the power supply voltage.

3. The current source circuit according to claim 1, characterized in that: The voltage-dividing element comprises: a fourth transistor; a drain of which serves as one end of the voltage-dividing element, a source of which serves as the other end of the voltage-dividing element; and a gate of which is also connected to the drain.

4. The current source circuit according to claim 1, characterized in that: The voltage dividing element includes: a first resistor, one end of which serves as one end of the voltage dividing element, and the other end of which serves as the other end of the voltage dividing element.

5. The current source circuit according to any one of claims 1 to 4, characterized in that: The current source unit includes: a second operational amplifier, a fifth transistor, and a second resistor; wherein, The positive input terminal of the second operational amplifier is connected to the reference voltage, the negative input terminal thereof is connected to one end of the second resistor, and the output terminal thereof is connected to the gate of the fifth transistor; The source of the fifth transistor is connected to one end of the second resistor, and the drain of the fifth transistor serves as the output end of the current source unit; The other end of the second resistor is grounded; The current source unit further includes: a current source, an output end of which is connected to one end of the second resistor; and the current source has a positive temperature coefficient.

6. The current source circuit according to claim 5, characterized in that: The current source unit further includes: a current mirror array connected between the output end of the current source and one end of the second resistor; The current mirror array comprises: a main transistor, whose drain is connected to the output end of the current source and whose drain is connected to the power supply voltage; A plurality of mirror transistors, when connected, form a current mirror with the main transistor; A plurality of switch control units correspond one to one with the mirror transistors and are used to control whether the mirror transistors are connected.

7. The current source circuit according to claim 6, characterized in that: The switch control unit comprises: a first switching element connected between the gate of the mirror transistor and the gate of the main transistor; a second switching element connected between the gate of the mirror transistor and a power supply voltage; The conduction signals of the first switch element and the second switch element are in anti-phase relationship with each other; specifically, when the first switch element is turned on and the second switch element is turned off, the corresponding mirror transistor is connected, and when the first switch element is turned off and the second switch element is turned on, the corresponding mirror transistor is not connected.

8. The current source circuit according to any one of claims 1 to 4, characterized in that: Also includes: An output buffer unit is connected to the output end of the current amplifying unit and is used to protect the current processing unit from being broken down when the current source unit is turned off.

9. The current source circuit according to claim 8, characterized in that: The output buffer unit comprises: a sixth transistor, whose source is connected to the output end of the current processing unit, whose drain serves as the output end of the output buffer unit, and whose gate is connected to the bias circuit; The bias circuit is used to provide a bias voltage for the gate of the sixth transistor; when the current source unit is working, the bias circuit is configured to make the sixth transistor in a deep linear region; when the current tube is turned off, the bias circuit is configured to make the sixth transistor in an off state.

10. The current source circuit according to claim 9, characterized in that: The output buffer unit further includes: a second voltage dividing element connected between the output end of the current source processing unit and the sixth transistor, or connected between the sixth transistor and the output end of the output buffer unit.

11. A communication chip, characterized in that: include: A current source circuit as claimed in any one of claims 1 to 10.

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