Data transmission method and device for EBC bus and LBE bus, and medium

Abstract

The invention belongs to the field of embedded computing systems and devices, and discloses a data transmission method and device for an EBC bus and an LBE bus and a medium, the method comprises the steps that a programmable logic device is arranged between a first device and a second device, and the programmable logic device sends an access request to the first device according to the access request output by the first device; establishing a communication link between the EBC bus of the first device and the LBE bus of the second device; the second equipment outputs a bus response signal to the first equipment through the programmable logic device according to the access request; and performing data read-write operation according to the read-write control signal, and controlling the communication link between the EBC bus of the first equipment and the LBE bus of the second equipment to be disconnected after the read-write operation is completed. By means of the method, asynchronous bus communication between the integrated EBC interface module and the integrated LBE bus interface module can be achieved.

Description

Technical Field

[0001] The present invention belongs to the field of embedded computing systems and devices, and relates to data transmission technology between different buses, and specifically to a data transmission method, device and medium between an EBC bus and an LBE bus. Background Art

[0002] As a universal bus interface standard, LBE bus is widely used in embedded computers, which can realize the communication between the master device and various slave devices. As a universal parallel bus interface, EBC bus is widely used in processors.

[0003] With the rapid development of embedded computing systems, they have the characteristics of high integration, complex technology and integration of multiple interfaces. For example, the EBC bus interface built into the processor module cannot directly communicate with the slave device with the LBE bus interface due to the difference in bus protocols. There is currently no technology suitable for mutual conversion between the two interfaces, which makes it difficult to solve the problem of direct communication of this asynchronous bus communication. Summary of the invention

[0004] In order to solve the technical problem that it is difficult to directly transmit data between two devices due to different bus protocols, the present invention discloses a data transmission method between an EBC bus and an LBE bus, the method comprising the following steps:

[0005] S1. A programmable logic device is provided between a first device and a second device, wherein the programmable logic device establishes a communication link between an EBC bus of the first device and an LBE bus of the second device according to an access request output by the first device;

[0006] S2. The second device outputs a bus response signal to the first device through the programmable logic device according to the received access request;

[0007] S3, performing a data read operation or a data write operation between the first device and the second device according to a read / write control signal of the second device;

[0008] S4. After the read operation or the write operation is completed, the programmable logic device controls the communication link between the EBC bus of the first device and the LBE bus of the second device to be disconnected.

[0009] In an optional embodiment, in the above step S1, the programmable logic device establishes a communication link between the EBC bus of the first device and the LBE bus of the second device according to the access request output by the first device, including:

[0010] S11, after power-on, the first device outputs an access request for accessing the second device, the programmable logic device judges the chip select signal ECS of the first device according to the access request, and sets the chip select signal XCS of the second device to be valid when the chip select signal ECS is valid;

[0011] S12. The programmable logic device sets the cycle command signal XCMD and the bus address signal XCYC of the second device to be valid in sequence according to the bus access address output by the first device, thereby completing the establishment of the communication link between the EBC bus and the LBE bus.

[0012] In an optional embodiment, in the above step S2, the second device outputs a bus response signal to the first device through the programmable logic device according to the received access request, including:

[0013] S21, after the second device receives the access request, the programmable logic device starts timing;

[0014] S22, when the programmable logic device receives the bus response signal output by the second device within the timing cycle, the programmable logic device outputs the response signal to the first device;

[0015] S23: When the programmable logic device does not receive the bus response signal output by the second device within a timing period, it automatically generates a response signal and outputs it to the first device.

[0016] In an optional embodiment, in the above step S3, performing a data read operation or a data write operation between the first device and the second device according to a read / write control signal of the second device includes:

[0017] The programmable logic device judges the read / write control signal of the second device. When the read / write control signal is at a low level, the first device performs a read operation on the second device. When the read / write control signal is at a high level, the first device performs a write operation on the second device.

[0018] In an optional embodiment, in the above step S4, after the read operation or the write operation is completed, the programmable logic device controls the communication link between the EBC bus of the first device and the LBE bus of the second device to be disconnected, including:

[0019] S41, after the read operation or the write operation is completed, the first device sets the chip select signal ECS to be invalid according to the response signal READY output by the programmable logic device;

[0020] S42, the programmable logic device sets the bus address signal XCYC, the cycle command signal XCMD and the chip select signal XCS of the second device to be invalid in sequence, so that the communication link between the EBC bus and the LBE bus is disconnected.

[0021] In an optional embodiment, the first device is a central processing module, and the second device is any one or more of an analog input and output module, a high-speed serial interface module, and an electronic disk interface control module.

[0022] In an optional embodiment, a level conversion module is provided between the programmable logic device and the second device.

[0023] In an optional embodiment, the programmable logic device is FPGA or CPLD.

[0024] An embodiment of the present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements any of the above-mentioned data transmission methods of the EBC bus and the LBE bus, which can solve the technical problem that direct data transmission is difficult between two devices due to different bus protocols.

[0025] An embodiment of the present invention also provides a computer-readable storage medium, which stores a computer program for executing any of the above-mentioned data transmission methods of the EBC bus and the LBE bus, which can solve the technical problem that it is difficult to directly transmit data between two devices due to different bus protocols.

[0026] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least: the data transmission method of the EBC bus and the LBE bus of the present invention, through the design of programmable logic devices and control logic, makes the transmission between different bus data reliable and effective, easy to operate, saves time, and can realize mutual conversion between two different bus interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A logic flow chart of a data transmission method between an EBC bus and an LBE bus disclosed in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the connection between the first device, the second device and the programmable logic device disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] The following describes the implementation methods of the present application through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and the features of the embodiments can be combined with each other in the absence of conflict. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0032] The data transmission method of the embodiment of the present invention is used to realize data transmission between devices with different bus protocols, wherein the first device (which can also be called the master device) is a central processing module such as a CPU module, which can select a HKPS6101 processor and has an EBC bus interface, and the second device (which can also be called the slave device) is any one of an analog input and output module AIO, a high-speed serial interface module HS I and an electronic disk interface control module ED I, which has an LBE bus, and the second device can be one or more.

[0033] Among them, the protocol of the LBE bus interface is: data bus 16 bits (XD15-XD0), address bus 32 bits (XA15-XA0), control bus (XCMD, XCYC), chip select signal XCS, bus response signal XWAIT. The protocol of the EBC bus interface is: data bus 16 bits (EBCO_EXT_DATA15-EBCO_EXT_DATA0), chip select signal ECS, address bus 32 bits (EBCO_EXT_ADDR31-EBCO_EXT_ADDR 0), read and write signal EBCO_EXT_OE, bus response signal EBCO_EXT_READY.

[0034] The method of the present invention sets a programmable logic device between a first device and a second device, wherein the programmable logic device can be selected from FPGA or CPLD, and realizes data transmission between the two devices through the programmable logic device. At the same time, a level conversion module can be set between the programmable logic device and the second device, and the level conversion of the signal between the two buses is realized through the level conversion module.

[0035] This embodiment discloses a data transmission method between an EBC bus and an LBE bus. Figure 1 and Figure 2 As shown, Figure 1 It is a logic flow chart of the data transmission method between the EBC bus and the LBE bus. Figure 2 The method comprises the following steps:

[0036] S1. A programmable logic device is provided between a first device and a second device, wherein the programmable logic device establishes a communication link between an EBC bus of the first device and an LBE bus of the second device according to an access request output by the first device;

[0037] S2. The second device outputs a bus response signal to the first device through the programmable logic device according to the received access request;

[0038] S3, performing a data read operation or a data write operation between the first device and the second device according to a read / write control signal of the second device;

[0039] S4. After the read operation or the write operation is completed, the programmable logic device controls the communication link between the EBC bus of the first device and the LBE bus of the second device to be disconnected.

[0040] In an optional embodiment, in the above step S1, the programmable logic device establishes a communication link between the EBC bus of the first device and the LBE bus of the second device according to the access request output by the first device, including:

[0041] S11, after power-on, the first device outputs an access request for accessing the second device, the programmable logic device judges the chip select signal ECS of the first device according to the access request, and sets the chip select signal XCS of the second device to be valid when the chip select signal ECS is valid;

[0042] S12. The programmable logic device sets the cycle command signal XCMD and the bus address signal XCYC of the second device to be valid in sequence according to the bus access address output by the first device, thereby completing the establishment of the communication link between the EBC bus and the LBE bus.

[0043] In an optional embodiment, in the above step S2, the second device outputs a bus response signal to the first device through the programmable logic device according to the received access request, including:

[0044] S21, after the second device receives the access request, the programmable logic device starts timing;

[0045] S22, when the programmable logic device receives the bus response signal output by the second device within the timing cycle, the programmable logic device outputs the response signal to the first device;

[0046] S23: When the programmable logic device does not receive the bus response signal output by the second device within a timing period, it automatically generates a response signal and outputs it to the first device.

[0047] In an optional embodiment, in the above step S3, performing a data read operation or a data write operation between the first device and the second device according to a read / write control signal of the second device includes:

[0048] The programmable logic device judges the read / write control signal of the second device. When the read / write control signal is at a low level, the first device performs a read operation on the second device. When the read / write control signal is at a high level, the first device performs a write operation on the second device.

[0049] In an optional embodiment, in the above step S4, after the read operation or the write operation is completed, the programmable logic device controls the communication link between the EBC bus of the first device and the LBE bus of the second device to be disconnected, including:

[0050] S41, after the read operation or the write operation is completed, the first device sets the chip select signal ECS to be invalid according to the response signal READY output by the programmable logic device;

[0051] S42, the programmable logic device sets the bus address signal XCYC, the cycle command signal XCMD and the chip select signal XCS of the second device to be invalid in sequence, so that the communication link between the EBC bus and the LBE bus is disconnected.

[0052] This embodiment describes in detail the data transmission process between the EBC bus of the master device and the LBE bus of the slave device through the following examples. Figure 1 As shown, the following steps are included:

[0053] Step 1: After the system is powered on, the CPU of the master device is reset, and the state machine solidified in the programmable logic device is started. The master device can send an access request to a slave device according to data requirements;

[0054] Step 2: The programmable logic device sets the bus address signal XCYC and the cycle command signal XCMD of the LBE bus of the slave device to be invalid, and waits for the master device to initiate access;

[0055] Step 3: After the master device initiates access, it pulls down its chip select signal ECS (i.e., sets it to be valid), and at the same time controls the chip select signal XCS of the slave device to be pulled down (i.e., set it to be valid) through the programmable logic device, and sends the bus access address to the second device;

[0056] Step 4: The programmable logic device pulls down the periodic command signal XCMD of the slave device (i.e., the command is valid) and latches the bus command;

[0057] Step 5: The programming logic device pulls down the bus address signal XCYC of the slave device (i.e., the address is valid) and latches the bus address;

[0058] Step 6: If the slave device is ready to transmit data, it returns a bus response signal XWAIT to the first device within the set time and proceeds to step 8; if it does not respond within the set time, it proceeds to step 7 (after receiving the access request, the slave device does not return a response signal for a long time, which may be caused by a failure of the slave device);

[0059] Step 7: The bus counter of the programmable logic device starts timing. If no bus response signal XWAI T is received within the timing period, it indicates that the bus has timed out. Then the programmable logic device automatically generates a response signal XWAI T and returns it to the master device.

[0060] Step 8, the programmable logic device determines the read operation and the write operation. When the read / write control signal XWR of the slave device is judged to be at a low level, it is a read operation, and when it is at a high level, it is a write operation; if it is a read operation, it proceeds to step 9, and if it is a write operation, it proceeds to step 12;

[0061] Step 9, read operation (master device reads data): send data on the LBE bus of the slave device to the EBC bus. After the data is sent, the programmable logic device sends a control EBC bus to the master device to return a response signal READY;

[0062] Step 10, after the master device EBC bus receives the READY signal, the master device sets the EBC chip select signal to be invalid;

[0063] Step 11, the programmable logic device invalidates XCYC, XCMD, and XCS of the slave device in sequence, returns to the initial state of the bus, and waits for the transmission command (i.e., returns to step 2);

[0064] Step 12, write operation: send the data on the EBC bus of the master device to the LBE bus, and at the same time, the programmable logic device sends the EBC bus return response signal READY to the master device;

[0065] Step 13, after the EBC bus receives the READY signal, the master device pulls up the EBC chip select;

[0066] Step 14: The programmable logic device sequentially pulls up XCYC, XCMD, and XCS of the slave device to return to the initial state of the bus and wait for the transmission command (i.e., returns to step 2).

[0067] The embodiments of the present invention achieve the following technical effects: the data transmission method of the EBC bus and the LBE bus of the present invention, through the design of programmable logic devices and control logic, makes the transmission of data between different buses reliable and effective, easy to operate, saves time, and can realize mutual conversion between two different bus interfaces.

[0068] In this embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, any of the above-mentioned data transmission methods between the EBC bus and the LBE bus is implemented.

[0069] Specifically, the computer device may be a computer terminal, a server or a similar computing device.

[0070] In this embodiment, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program for executing any of the above-mentioned data transmission methods between the EBC bus and the LBE bus.

[0071] Specifically, computer-readable storage media include permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer-readable storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable storage media does not include transitory media such as modulated data signals and carrier waves.

[0072] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, and optionally, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the embodiments of the present invention are not limited to any specific combination of hardware and software.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A data transmission method between an EBC bus and an LBE bus, characterized in that: include: A programmable logic device is provided between the first device and the second device, wherein the programmable logic device establishes a communication link between the EBC bus of the first device and the LBE bus of the second device according to an access request output by the first device; The second device outputs a bus response signal to the first device through the programmable logic device according to the received access request; Performing a data read operation or a data write operation between the first device and the second device according to a read / write control signal of the second device; After the read operation or the write operation is completed, the programmable logic device controls the communication link between the EBC bus of the first device and the LBE bus of the second device to be disconnected.

2. The data transmission method between the EBC bus and the LBE bus according to claim 1, characterized in that: The programmable logic device establishes a communication link between an EBC bus of the first device and an LBE bus of the second device according to the access request output by the first device, including: After power-on, the first device outputs an access request for accessing the second device, and the programmable logic device judges the chip select signal ECS of the first device according to the access request, and sets the chip select signal XCS of the second device to be valid when the chip select signal ECS is valid; The programmable logic device sets the cycle command signal XCMD and the bus address signal XCYC of the second device to be valid in sequence according to the bus access address output by the first device, thereby completing the establishment of the communication link between the EBC bus and the LBE bus.

3. The data transmission method between the EBC bus and the LBE bus according to claim 1, characterized in that: The second device outputs a bus response signal to the first device through the programmable logic device according to the received access request, including: After the second device receives the access request, the programmable logic device starts timing; When the programmable logic device receives the bus response signal output by the second device within the timing cycle, the programmable logic device outputs the response signal to the first device; When the programmable logic device does not receive the bus response signal output by the second device within a timing cycle, it automatically generates a response signal and outputs it to the first device.

4. The data transmission method between the EBC bus and the LBE bus according to claim 1, characterized in that: Performing a data read operation or a data write operation between the first device and the second device according to a read / write control signal of the second device, including: The programmable logic device judges the read / write control signal of the second device. When the read / write control signal is at a low level, the first device performs a read operation on the second device. When the read / write control signal is at a high level, the first device performs a write operation on the second device.

5. The data transmission method between the EBC bus and the LBE bus according to claim 1, characterized in that: After the read operation or the write operation is completed, the programmable logic device controls the communication link between the EBC bus of the first device and the LBE bus of the second device to be disconnected, including: After the read operation or the write operation is completed, the first device sets the chip select signal ECS to be invalid according to the response signal READY output by the programmable logic device; The programmable logic device sets the bus address signal XCYC, the cycle command signal XCMD and the chip select signal XCS of the second device to be invalid in sequence, so that the communication link between the EBC bus and the LBE bus is disconnected.

6. The data transmission method between the EBC bus and the LBE bus according to claim 1, characterized in that: The first device is a central processing module, and the second device is any one or more of an analog input and output module, a high-speed serial interface module, and an electronic disk interface control module.

7. The data transmission method between the EBC bus and the LBE bus according to claim 1, characterized in that: A level conversion module is provided between the programmable logic device and the second device.

8. The data transmission method between the EBC bus and the LBE bus according to claim 1, characterized in that: The programmable logic device is FPGA or CPLD.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the data transmission method between the EBC bus and the LBE bus according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program for executing the data transmission method between the EBC bus and the LBE bus according to any one of claims 1 to 8.

Images