Shared LLC cache optimization management method based on multi-core processor

Abstract

According to the shared LLC cache optimization management method based on the multi-core processor, exclusive shared LLC is divided for virtual machines with specific requirements, especially virtual machines with high real-time requirements, the memory access bandwidth of the virtual machines is dynamically adjusted, and meanwhile memory access operations of other virtual machines with low priorities are blocked, so that the memory access efficiency of the virtual machines is improved. And the real-time performance of the memory access response of the virtual machine with specific requirements is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of cache management of a multi-core processor embedded operating system, and in particular to a shared LLC cache optimization management method based on a multi-core processor. Background Art

[0002] The main function of cache is to reduce the delay caused by accessing memory. It has the characteristics of fast speed and small capacity. When the processor issues a memory access request, it first searches the cache. If it hits, the data in the cache is directly returned to the processor; if it is missing, the corresponding data must be read from the memory into the cache first, and then returned to the processor. Cache mainly uses the principle of locality of program operation, and the cache is faster than the main memory. The data that the processor will use in the near future is transferred into the cache, and the processor can directly obtain the data from the cache. However, due to the limited capacity of the cache, it is necessary to replace the original data in the cache so as to continuously transfer the data from the main memory into the cache. When the cache is missing, the processor still needs to wait for the data to be loaded from the main memory.

[0003] In order to take advantage of spatial locality, the cache storage body exchanges information with the main memory in blocks (cache blocks or cache lines) as the smallest unit. In current hardware design, the size of a cache line is usually 64 or 128 bytes, and a single cache line contains information such as a tag bit, a valid bit, and a data block. The main memory and cache are divided into the same block size, and the mapping between the memory block and the cache line is achieved by hashing the memory address. If the cache line after address mapping can establish a corresponding relationship with the main memory block required by the processor, then the cache hits, otherwise a cache miss occurs. In the case of a miss, the main memory block where the data is located will be called into the cache. If the cache is full at this time, a replacement strategy must be adopted to update the corresponding position of the cache.

[0004] The goal of cache management technology is to decide which cache lines to keep in order to minimize cache misses. Therefore, the effectiveness of cache management technology depends on how accurately it evaluates which cache lines are least likely to be accessed recently and should be replaced by new data when cache replacement occurs. Ideally, the optimal replacement algorithm OPT can obtain future memory access sequences offline to give the optimal replacement plan. However, actual LLC management technology can only heuristically predict future data reuse through past LLC access situations. Typical cache management technology sets relative priorities for cache lines in a given cache set. The relative priority of a cache line indicates the possibility of it being re-referenced in the future. Different cache management technologies set priorities in different ways. When a cache hit or miss event occurs, the cache management technology adjusts the priority.

[0005] In the past, access to cache on multiple cores was mostly managed using a paging control method to reduce cache conflicts between processes on different cores. Later, technologies such as cache partitioning, replacement algorithms, bypass technology, and data layout were used to optimize the management of shared LLCs and improve the performance of LLC access. Since Professor Zhang Xiaodong proposed using page coloring technology to improve LLC performance in 2008, page coloring technology has received widespread attention and has been widely used in shared cache partitions in academia. In addition, Intel has applied page coloring technology to modern CPUs to improve LLC performance.

[0006] For a multi-core heterogeneous processor formed by a CPU and a GPU, the last level cache (LLC) forms a shared storage hierarchy between the CPU and the GPU, which can accelerate data transmission between them. However, once a cache miss occurs in an application, especially a last level cache miss, it needs to access the off-chip main memory additionally, causing unnecessary overhead and reducing system performance. Fang Juan et al. (LLC Buffer Management Strategy Based on Heterogeneous Multi-cores, Journal of Beijing University of Technology, Vol. 45, No. 5) proposed a buffer-for-GPU (BFG) LLC buffer management strategy based on heterogeneous multi-cores to address the problem that a large amount of shared last level cache space is occupied by GPU applications in a CPU-GPU heterogeneous multi-core architecture, resulting in reduced system performance. This strategy establishes a GPU-specific buffer with the same structure on the GPU side of the shared last level cache L2 cache (LLC). Cache-insensitive GPU messages directly access the buffer instead of the LLC, and then a replacement strategy suitable for the GPU is used to filter GPU stream requests and free up LLC space for CPU applications.

[0007] When each core is under high load, resource contention and data consistency problems will obviously appear in the multi-core architecture. Since each core has unlimited access to the shared cache and each core has equal status, when the load is high, the core's access demand for the shared cache increases, that is, a large number of cache reads and writes are required. At this time, the cache is under high load, and the core's operation on the cache will trigger the cache replacement mechanism. In the process of replacing the cache line, it is very likely that the data cached in the shared cache of other cores will be replaced. When other cores try to access the content that should be in the shared cache, they will encounter a cache miss, and then need to access the memory controller to trigger the memory data cache mechanism, cache the pages in the memory into the cache through the bus, and then cause a new cache replacement process. This process is repeated, making the system's cache behavior more unpredictable. In addition, due to the potential behavior of cores expelling each other's data, it will cause pipeline delays and increase memory access, which will put pressure on the shared memory bus and make the memory access bandwidth a system performance bottleneck. In order to improve the performance of the system, unnecessary cache misses should be avoided as much as possible. At the same time, on-chip shared resources such as shared cache and memory access bandwidth should be reasonably and effectively monitored and controlled to ensure that the virtual machines or tasks running on the corresponding cores can obtain appropriate resources, thereby ensuring that the worst response time of the virtual machines or tasks can be effectively estimated and real-time support can be provided.

[0008] In the actual operation of VMM (Virtual Machine Manager), multiple VMs are often running on the VMM, and these VMs will try their best to utilize the resources provided by the hardware processor. The last-level cache LLC on the processor chip will face contention among the virtual machines. Summary of the invention

[0009] The technical problem to be solved by the technical solution of the present invention is that the conflict and competition of on-chip shared resources easily lead to the degradation of virtualization performance, thereby affecting the real-time performance of the virtual machine.

[0010] The technical solution of the present invention provides a shared LLC cache optimization management method based on a multi-core processor, comprising the following steps:

[0011] When the memory pages used by the virtual machine are mapped to the LLC, they are concentrated in a specific area, and the memory page allocator of the multi-core embedded operation is modified and called, thereby allocating a corresponding exclusive LLC for the virtual machine;

[0012] Obtain the processor cycles, number of instructions executed, and number of LLC misses inside the processor, and calculate the parameter values ​​of LLC miss and memory access bandwidth of the virtual machine;

[0013] Determine whether the virtual machine is a virtual machine with special requirements;

[0014] If not, determine whether the parameter value of the memory access bandwidth exceeds the preset bandwidth value. If not, run according to the parameter values ​​of LLC miss and memory access bandwidth. If exceeded, schedule the virtual machine to the group congestion queue.

[0015] If yes, determine whether the parameter value of LLC miss exceeds the maximum value of LLC miss reserved initial value;

[0016] If it exceeds, the memory bandwidth is temporarily increased by no more than 20% of the maximum value of the LLC miss initial reserved value for 10ms, and then the parameter value of the memory bandwidth before the increase is restored, and the system runs according to the parameter values ​​of LLC miss and memory bandwidth;

[0017] If not, determine whether the LLC miss parameter value is lower than the LLC miss reserved initial value minimum;

[0018] If it is not less than that, it will run according to the parameter values ​​of LLC miss and memory access bandwidth;

[0019] If it is lower, the memory bandwidth is temporarily reduced by no more than 10% of the minimum value of the LLC miss reserved initial value for 10ms, and then the parameter value of the memory bandwidth before the increase is restored, and the operation is carried out according to the parameter values ​​of LLC miss and memory bandwidth.

[0020] Preferably, a performance monitoring unit is used to obtain the processor cycle, the number of executed instructions and the number of LLCmisses inside the processor.

[0021] Preferably, the maximum value of the LLC miss reserved initial value is 60%, and the minimum value of the LLC miss reserved initial value is 5%.

[0022] Preferably, the parameter value of the LLC miss is directly obtained through the Perf tool and compared with the parameter value of the LLC miss of the computing virtual machine. If the comparison is consistent, the subsequent determination of whether the virtual machine is a virtual machine for special requirements is carried out. If they are inconsistent, the parameter value of the LLC miss of the virtual machine is directly obtained and recalculated through the Perf tool for comparison.

[0023] Preferably, the LLC size, the Cache Line size and the LLC way number are obtained; the number of Cache Lines in the LLC is converted, and the memory page corresponding to each Cache Set in the virtual machine is obtained according to the LLC coloring partition and the memory map.

[0024] The technical solution of the present invention proposes a shared LLC cache optimization management method based on a multi-core processor. By allocating exclusive shared LLC to virtual machines with specific needs, especially virtual machines with high real-time requirements, and dynamically adjusting their memory access bandwidth, while blocking the memory access operations of other virtual machines with low priority, the real-time performance of the memory access response of virtual machines with specific needs is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flowchart of a shared LLC cache optimization management method based on a multi-core processor is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0027] In view of the fact that virtual machines (VMs) on a multi-core platform compete with each other for the shared LLC on the processor chip, resulting in an increase in the shared LLC miss rate, thereby affecting the response time of the virtual machine and reducing the real-time performance of the system, an embodiment of the present invention provides a shared LLC cache optimization management method based on a multi-core processor, the basic idea of ​​which is to divide the shared cache for a specific virtual machine according to the rationality of the tasks running on the virtual machine, and reserve appropriate memory access bandwidth for it so that the performance of the specific virtual machine can still be guaranteed when the system is highly loaded. By properly dividing the cache, different virtual machines can use shared caches in different ranges or avoid a certain cache from being used by virtual machines other than a specific virtual machine.

[0028] Since the overall load of the system does not remain unchanged during operation, but is in a changing process, in order to avoid the possibility of waste of reserved on-chip resources, compared with statically setting the reserved values ​​of LLC and memory access bandwidth during the entire system execution cycle, a dynamic method is used to set their values. During the operation of the system, there are often sudden accesses to the memory bus, such as branch prediction errors, or too few LLCs allocated to the virtual machine, resulting in an increase in the LLC miss rate. The more LLCs a virtual machine occupies, the lower the probability of LLC miss, the fewer times the memory is accessed, and the faster the response time. The basic idea of ​​dynamic setting is to reserve a part of the available bandwidth value for temporary adjustment when reserving memory access bandwidth. When the LLC miss rate of a virtual machine is detected to be increased, some additional memory access bandwidth is temporarily allocated to it for use and then recycled. Similarly, when the LLC hit rate of a virtual machine is very high and it hardly needs to access memory, reserving too much memory access bandwidth for it will cause waste. In this case, part of its memory access bandwidth quota is released to the idle memory access bandwidth for use by other virtual machines.

[0029] The embodiment of the present invention provides a shared LLC cache optimization management method based on a multi-core processor, the steps are as follows:

[0030] 1) Modify and call the memory page allocator of multi-core embedded operation to allocate physical addresses of a specific format to a specific virtual machine, so that the memory pages used by the virtual machine will eventually be concentrated in a specific area when mapped to the LLC without affecting other LLC spaces, thereby realizing LLC partition control for different virtual machines.

[0031] 2) Use the performance monitoring unit (PMU) provided by the hardware to sample and monitor the processor cycles, number of instructions executed, number of LLC misses, and other events inside the processor, and calculate the values ​​of parameters such as LLC miss and memory access bandwidth of the virtual machines running in the system. The value of LLC miss can also be directly obtained through the Perf tool.

[0032] 3) For virtual machines that prioritize real-time performance, when it is detected that its LLC miss is very high (for example, 60%) or the memory access bandwidth exceeds the reserved initial value, a part of the memory access bandwidth is temporarily increased for this virtual machine (generally not more than 20% of the reserved initial value), which lasts for 10ms and then returns to the original value; when it is detected that the LLC miss value is very low (for example, 5%) and the memory access bandwidth is less than the reserved initial value, a part of the memory access bandwidth of this virtual machine is temporarily reduced (generally not more than 10% of the reserved initial value), which lasts for 10ms and then returns to the original value.

[0033] 4) For other virtual machines with low priority, when it is detected that its memory access bandwidth exceeds the set value, the Credit scheduling algorithm is used to schedule this virtual machine to the blocking queue to prevent it from further occupying the memory access bandwidth.

[0034] The LLC partition control is complex to implement, including the complexity of hardware and software design. To implement LLC partition control, you first need to know the LLC information of the current machine, the most important of which is the size of the LLC and the size of the Cache Line. You also need to know the number of ways of the LLC. On this basis, you can calculate the specific number of Cache Sets in the LLC, and then find the number of physical memory pages corresponding to each Cache Set based on the LLC coloring partition (Cache Coloring) and the memory mapping diagram (Memory Mapping Layout). Therefore, when the virtual machine requests a memory page, the kernel returns the appropriate physical page obtained according to the LLC control when searching for the page, thereby ensuring that the mapping area of ​​this virtual machine in the LLC is exclusive to it.

[0035] An embodiment of the present invention proposes a shared LLC cache optimization management method based on a multi-core processor, which has the following beneficial effects: by reserving and dividing specific shared cache areas for virtual machines with specific needs, LLC division based on virtual machine granularity is realized, thereby avoiding the situation where multiple virtual machines compete for LLC and cause additional LLC misses, and by dynamically adjusting the memory access bandwidth of each virtual machine, the multi-core virtualization platform can ensure that specific virtual machines enjoy a certain amount of shared resources when the overall system load is large, thereby ensuring their response time and improving the real-time performance of the system.

Claims

1. A shared LLC cache optimization management method based on a multi-core processor, characterized in that: The following steps are involved: When the memory pages used by the virtual machine are mapped to the LLC, they are concentrated in a specific area, and the memory page allocator of the multi-core embedded operation is modified and called, thereby allocating a corresponding exclusive LLC for the virtual machine; Obtain the processor cycles, number of instructions executed, and number of LLC misses inside the processor, and calculate the parameter values ​​of LLCmiss and memory access bandwidth of the virtual machine; Determine whether the virtual machine is a virtual machine with special requirements; If not, determine whether the parameter value of the memory access bandwidth exceeds the preset bandwidth value. If not, run according to the parameter values ​​of LLC miss and memory access bandwidth. If exceeded, schedule the virtual machine to the group congestion queue. If yes, determine whether the parameter value of LLC miss exceeds the maximum value of LLC miss reserved initial value; If it exceeds, the memory bandwidth is temporarily increased by no more than 20% of the maximum value of the LLC miss initial reserved value for 10ms, and then the parameter value of the memory bandwidth before the increase is restored, and the system runs according to the parameter values ​​of LLC miss and memory bandwidth; If not, determine whether the LLC miss parameter value is lower than the LLC miss reserved initial value minimum; If it is not less than that, it will run according to the parameter values ​​of LLC miss and memory access bandwidth; If it is lower, the memory bandwidth is temporarily reduced by no more than 10% of the minimum value of the LLC miss reserved initial value for 10ms, and then the parameter value of the memory bandwidth before the increase is restored, and the operation is carried out according to the parameter values ​​of LLC miss and memory bandwidth.

2. A shared LLC cache optimization management method based on a multi-core processor as claimed in claim 1, characterized in that: The performance monitoring unit is used to obtain the processor cycles, the number of instructions executed, and the number of LLC misses inside the processor.

3. A shared LLC cache optimization management method based on a multi-core processor as claimed in claim 1, characterized in that: The maximum value of the LLC miss reserved initial value is 60%, and the minimum value of the LLC miss reserved initial value is 5%.

4. The method for optimizing and managing a shared LLC cache based on a multi-core processor according to claim 1, characterized in that: The parameter value of the LLC miss is directly obtained through the Perf tool and compared with the parameter value of the LLC miss of the computing virtual machine. If the comparison is consistent, the subsequent determination of whether the virtual machine is a virtual machine for special requirements is carried out. If they are inconsistent, the parameter value of the LLC miss of the virtual machine is directly obtained and recalculated through the Perf tool for comparison.

5. The method for optimizing and managing a shared LLC cache based on a multi-core processor according to claim 1, characterized in that: include: Get LLC size, Cache Line size and LLC ways; The number of Cache Lines in LLC is converted, and the memory page corresponding to each Cache Set in the virtual machine is obtained according to LLC coloring partitioning and a memory map.

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