Full-detail modeling large cascaded H bridge application real-time simulation method and system

Abstract

The invention relates to a full-detail modeling large cascade H bridge application real-time simulation method and system, and the method comprises the steps: carrying out the equivalent segmentation of a large cascade H bridge system topology into a plurality of equivalent circuits, replacing the segmented cascade H bridge topology with a controlled voltage source, and measuring the current of the controlled voltage source as feedback; a power grid main circuit is wholly replaced by a controlled current source, and voltages at two ends are measured as feedback; a circuit breaker is added in a main circuit topology, bypass switches are added in a cascaded H-bridge topology, and a logic control program is designed to control on and off of each switch; the divided equivalent circuits respectively run in the FPGA of each simulator, and the logic control program runs in the CPU of the simulator; and data interaction is carried out between the simulators through optical fiber communication. Compared with the prior art, the method can achieve the precise simulation of each working condition of the large-scale cascaded H bridge system, and achieves the full-physical IO interaction controller hardware-in-loop testing of the large-scale cascaded H bridge application of full-detail modeling.

Description

Technical Field

[0001] The present invention relates to the technical field of real-time simulation of power converters, and in particular to a real-time simulation method and system for large-scale cascade H-bridge applications with full-detail modeling. Background Art

[0002] Cascade topology converter is a new type of high-voltage high-power converter with the advantages of large transmission power, high system efficiency, and good waveform quality. It is widely used in high-voltage direct current transmission, new energy generation, reactive power compensation, high-voltage inverters and other fields. Large cascade H-bridge systems such as chain SVG, high-voltage direct-mounted energy storage, MMC and high-voltage inverters generally have the characteristics of many switching elements and high power. Building a physical platform for testing has the problems of high cost, long cycle, high risk, and difficult to reproduce working conditions. Therefore, semi-physical simulation platforms are usually used for testing and verification in cascade topology applications. However, for traditional stand-alone real-time simulators, they are limited by FPGA simulation resources, and the system topology that can be supported is limited. In addition, the physical IO interface of a single device is limited, and it is impossible to realize hardware-in-the-loop testing of full physical IO interaction between large cascade topology systems and controllers. If the dedicated cascade topology modeling and optical fiber communication solutions on the market are used, although a single device can realize cascade topology system simulation, it still cannot fully meet the full physical IO test requirements of industrial users, and the system topology is relatively fixed and single, and it is impossible to realize the user's customized design of the topology. Summary of the invention

[0003] The purpose of the present invention is to overcome the problems of limited topology size and limited physical IO channels supported by the above-mentioned existing single simulator and to provide a large-scale cascade H-bridge application real-time simulation method and system with full-detail modeling.

[0004] The purpose of the present invention can be achieved by the following technical solutions:

[0005] As a first aspect of the present invention, a real-time simulation method for a large-scale cascaded H-bridge application is provided, the method steps comprising:

[0006] The circuit topology of the large cascade H-bridge system is equivalently divided into a main system circuit topology and a plurality of subsystem circuit topologies, wherein the main system circuit topology is a power grid system, and the subsystem circuit topology is a cascade H-bridge system;

[0007] Using controlled voltage sources and controlled current sources to perform equivalent replacement on the equivalently divided circuits, using multiple controlled voltage sources to equivalently replace each subsystem circuit topology in the main system circuit; using controlled current sources to equivalently replace the main system circuit in the subsystem circuit;

[0008] Measure the branch current of the controlled voltage source in the main system circuit and give it to the controlled current source input in the corresponding subsystem circuit; measure the voltage across the controlled current source and give it to the corresponding controlled voltage source input in the main system circuit;

[0009] A circuit breaker is provided for each controlled voltage source branch in the main system equivalent circuit, and a bypass switch is connected in parallel across the controlled current source in each subsystem circuit;

[0010] Construct a circuit breaker state logic judgment module to judge the current working state of each cascaded H-bridge branch based on the PWM signal, branch voltage, branch current and submodule capacitor voltage of the cascaded H-bridge equivalent circuit in each subsystem, and control the on and off of the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit according to different working states;

[0011] The main system circuit topology and several subsystem circuit topologies after equivalent segmentation are loaded into each simulator respectively, and the circuit breaker state logic judgment module is loaded into the simulator; data exchange is carried out between each simulator through optical fiber communication, and data exchange is carried out between each simulator and the controller through physical IO, realizing hardware-in-the-loop simulation of full physical IO of large-scale cascaded H-bridge system.

[0012] As a preferred technical solution, the circuit topology of the large cascaded H-bridge system is divided according to the specific cascade number of the cascaded H-bridge system and the topology size and IO channel number supported by the stand-alone simulator: for the system with an actual cascade number of n levels, the maximum simulation cascade scale supported by the stand-alone simulator is m levels, and the system topology is divided into at least n / m equivalent circuits. If n / m is not an integer, it is rounded up.

[0013] As a preferred technical solution, the equivalent division is to divide each phase of the large cascade H-bridge system circuit topology into a subsystem cascade H-bridge equivalent circuit or into multiple subsystem cascade H-bridge equivalent circuits.

[0014] As an optimal technical solution, the switching states of the circuit breaker in the main system circuit topology and the bypass switch in the cascaded H-bridge equivalent circuit of the corresponding subsystem are opposite, that is, when the circuit breaker in the main circuit is turned on, the bypass switch in the corresponding cascaded H-bridge equivalent circuit is turned off; when the circuit breaker in the main circuit is turned off, the bypass switch in the cascaded H-bridge equivalent circuit of the corresponding subsystem is turned on.

[0015] As a preferred technical solution, the circuit breaker state logic determination module is constructed to determine the current working state of each cascaded H-bridge branch as follows:

[0016] The circuit breaker state logic judgment module detects whether there is a PWM signal in the branch of the cascaded H-bridge equivalent circuit of each subsystem. If there is a PWM signal, it is judged that the cascaded H-bridge branch is in the PWM working state; if no PWM signal is detected, it means that the cascaded H-bridge is in an uncontrolled rectification or high-impedance state, and the next step of judgment is carried out;

[0017] If no PWM signal is detected, the circuit breaker state logic judgment module will detect whether the cascaded H-bridge branch current is zero-crossing. If it is not zero-crossing, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if it is zero-crossing, the next step of judgment is required;

[0018] If the circuit breaker state logic judgment module detects that the current of the cascaded H-bridge branch passes through zero, the circuit breaker in the control main circuit is disconnected, and the branch voltage of the cascaded H-bridge equivalent circuit is compared with the sum of the capacitor voltage. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, it is judged that the cascaded H-bridge branch is in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, it is judged that the cascaded H-bridge branch is in a high-impedance state.

[0019] As a preferred technical solution, the on and off of the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit are controlled according to different working states, as follows:

[0020] When the circuit breaker state logic judgment module determines that the cascaded H-bridge branch is in the PWM working state, the main system equivalent circuit breaker is controlled to be turned on, and the bypass switch of the corresponding subsystem-level cascaded H-bridge equivalent circuit is turned off, and the system is in the normal working mode;

[0021] When the circuit breaker state logic determines that the branch is in an uncontrolled rectification state, the main system equivalent circuit breaker is kept turned on, the bypass switch of the cascaded H-bridge equivalent circuit in the corresponding subsystem is turned off, and the system is in an uncontrolled rectification mode;

[0022] When the circuit breaker state logic judgment module determines that the branch is in a high-resistance state, the main system equivalent circuit breaker is controlled to be turned off, and the bypass switch of the corresponding subsystem-level intermediate H-bridge equivalent circuit is turned on to short-circuit the equivalent controlled current source.

[0023] As a preferred technical solution, the main system circuit topology and several subsystem circuit topologies after equivalent segmentation are loaded into the FPGA of each simulator respectively, and the circuit breaker state logic determination module is loaded into the simulator CPU;

[0024] The FPGA uploads the branch voltage, submodule capacitor voltage, and branch current data to the CPU, and the logic control program in the CPU sends the control instructions of each circuit breaker and bypass switch to the circuit breakers and bypass switches in the FPGA topology of each simulator;

[0025] Data is exchanged between simulators via optical fiber communication; clock synchronization lines are connected between simulators to synchronize clock signals between different devices.

[0026] As a second aspect of the present invention, there is provided a large-scale cascade H-bridge application real-time simulation system, characterized in that the system comprises a plurality of simulators;

[0027] The FPGA of the simulator is loaded with the equivalent circuit topology of the large cascade H-bridge system after segmentation, and multiple controlled voltage sources are used in the main system circuit to equivalently replace the circuit topology of each subsystem; a controlled current source is used in the subsystem circuit to equivalently replace the main system circuit, and the branch current of the controlled voltage source in the main system circuit is measured and given to the controlled current source input in the corresponding subsystem circuit; the voltage across the controlled current source is measured and given to the corresponding controlled voltage source input in the main system circuit;

[0028] The CPU of the simulator is loaded with a circuit breaker state logic determination module, which determines the current working state of each cascaded H-bridge branch based on the PWM signal, branch voltage, branch current and submodule capacitor voltage of the cascaded H-bridge equivalent circuit in each subsystem, and controls the on and off of the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit according to different working states;

[0029] Data is exchanged between simulators through optical fiber communication, and the synchronous operation of multiple simulators is ensured through clock synchronization lines; data is exchanged between simulators and controllers through physical IO, realizing hardware-in-the-loop simulation of full physical IO of large-scale cascaded H-bridge systems.

[0030] As a preferred technical solution, the circuit topology of the large cascaded H-bridge system is divided according to the specific cascade number of the cascaded H-bridge system and the topology size and IO channel number supported by the stand-alone simulator: for the system with an actual cascade number of n levels, the maximum simulation cascade scale supported by the stand-alone simulator is m levels, and the system topology is divided into at least n / m equivalent circuits. If n / m is not an integer, it is rounded up.

[0031] As a preferred technical solution, the circuit breaker state logic determination module is specifically as follows:

[0032] Detect whether there is a PWM signal in the branch of the cascaded H-bridge equivalent circuit in each subsystem circuit. If there is a PWM signal, it is determined that the cascaded H-bridge branch is in a PWM working state; if no PWM signal is detected, it means that the cascaded H-bridge is in an uncontrolled rectification or high-impedance state, and the next step of judgment is performed;

[0033] If no PWM signal is detected, the circuit breaker state logic judgment module will detect whether the cascaded H-bridge branch current is zero-crossing. If not, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if it is zero-crossing, the next step of judgment is performed;

[0034] If the logic judgment module detects that the current of the cascaded H-bridge branch passes through zero, after the circuit breaker in the control main circuit is disconnected, the branch voltage of the cascaded H-bridge equivalent circuit and the sum of the capacitor voltage are compared. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in a high-impedance state;

[0035] When the circuit breaker state logic judgment module determines that the branch is in the PWM working state, the main circuit breaker is controlled to be turned on, and the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off, and the system is in the normal working mode;

[0036] When the circuit breaker state logic determines that the branch is in an uncontrolled rectification state, the main circuit breaker is kept on, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off, and the system is in an uncontrolled rectification mode;

[0037] When the circuit breaker state logic determination module determines that the branch is in a high-resistance state, the main circuit breaker is controlled to be turned off, and the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned on to short-circuit the equivalent controlled current source.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The present invention adds a circuit breaker to the main system circuit topology after segmentation, and connects a bypass switch in parallel with the current source in the remaining cascade H-bridge equivalent circuit. Based on the PWM signal, branch voltage, branch current and submodule voltage in the circuit, the current working state of each cascade H-bridge branch is judged, and the main circuit breaker is controlled to be turned off and the bypass switch of the corresponding cascade H-bridge equivalent circuit is turned on, so as to realize accurate simulation of various working conditions of the system; and the controller hardware-in-the-loop test of the full physical IO interaction of the large-scale cascade H-bridge application with full-detail modeling is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A flow chart of a real-time simulation method for a large cascade H-bridge application modeled in full detail by the present invention;

[0041] Figure 2 Schematic diagram of the overall equivalent segmentation of the SVG system of the present invention

[0042] Figure 3 Logic block diagram of the circuit breaker state logic determination module in the present invention

[0043] Figure 4 Schematic diagram of an SVG system after equivalent segmentation in one embodiment of the present invention

[0044] Figure 5This is a waveform diagram of the real-time simulation result of a 40-level SVG system in one embodiment of the present invention, including a) grid-side voltage, b) grid-side current, and c) cascaded H-bridge capacitor voltage. DETAILED DESCRIPTION

[0045] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0046] Example 1

[0047] In view of the limited topology size and IO channels supported by existing single simulators, the present invention proposes a multi-level system parallel simulation method, which can realize the controller hardware-in-the-loop test of full physical IO interaction for large cascade H-bridge applications with full-detail modeling. Figure 1 As shown, the real-time simulation method for large-scale cascade H-bridge application with full-detail modeling proposed by the present invention includes the following steps:

[0048] Step 1: According to the scale of the cascaded H-bridge system, the entire system circuit topology is equally divided into a main system circuit topology and several subsystem circuit topologies. The main system circuit topology is defined as a power grid system, and the subsystem circuit topology is defined as a cascaded H-bridge system.

[0049] In the step 1: the circuit topology of the large cascade H-bridge system is divided according to the specific cascade number of the system and the topology size and the number of IO channels supported by the stand-alone simulator; if the actual cascade number of the system is n levels and the maximum supported simulation cascade scale of the stand-alone simulator is m levels, the system topology needs to be divided into at least n / m (if not an integer, round up) equivalent circuits;

[0050] As one of the segmentation methods, Figure 2 The figure shows the circuit segmentation diagram of the 24-level SVG system. The 24-level SVG three-phase fully detailed modeling has a total of 72 cascaded H-bridge submodules. A single simulator cannot support a topology of this scale due to resource limitations. The system is equivalently segmented, with each phase being a subsystem cascaded H-bridge equivalent circuit. Each subsystem equivalent circuit contains 24 cascaded H-bridges.

[0051] Step 2: Use the controlled voltage source and the controlled current source to perform equivalent substitution on the equivalently divided circuit. In the main system circuit, the controlled voltage source is used to replace the subsystem circuit topology, and the branch current of the controlled voltage source is measured as feedback; in the subsystem circuit, the controlled current source is used to replace the main system circuit, and the voltage across it is measured as feedback; Figure 2As shown, an ammeter is added to the three-phase controlled voltage sources A, B, and C in the main system circuit topology to measure the branch current, and a voltmeter is connected in parallel to the controlled current source in each subsystem circuit topology to measure the voltage across the two ends;

[0052] Step 3: Measure the branch current of the controlled voltage source and give it to the controlled current source input in the corresponding subsystem circuit, and measure the voltage across the controlled current source and give it to the corresponding controlled voltage source input in the main system circuit;

[0053] The step 3 comprises the following steps:

[0054] Step 3a: measuring the branch current of the controlled voltage source in the main system circuit topology, and measuring the voltage across the controlled current source in the subsystem circuit topology;

[0055] Step 3b: If Figure 2 As shown, the measured controlled voltage source branch current is transmitted to the controlled current source input in the corresponding A, B, and C three-phase subsystem circuits through optical fiber; the measured voltage at both ends of the controlled current source is transmitted to the controlled voltage source input in the main system circuit topology through optical fiber;

[0056] Step 4: Add a circuit breaker to each phase branch in the main system circuit, and connect a bypass switch in parallel across the controlled current source in each subsystem circuit;

[0057] In step 4: Figure 2 As shown, a circuit breaker is added to the main system circuit topology after segmentation, and a bypass switch is connected in parallel with the current source in the remaining cascaded H-bridge equivalent circuits; the switch states of the circuit breaker and the corresponding cascaded H-bridge equivalent circuit in the main system circuit topology are opposite, that is, when the circuit breaker of the branch in the main circuit is turned on, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off; when the circuit breaker of the branch in the main circuit is turned off, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned on;

[0058] Step 5: Collect the PWM signal and branch voltage V in the circuit bran h, branch current I branc h, submodule voltage, design circuit breaker state logic determination module;

[0059] like Figure 3 As shown, step 5 specifically includes the following steps:

[0060] Step 5a: The logic determination module detects whether there is a PWM signal in each cascade H-bridge equivalent circuit branch. If there is a PWM signal, it is determined that the cascade H-bridge branch is in a PWM working state; if no PWM signal is detected, it means that the cascade H-bridge is in an uncontrolled rectification or high-impedance state, and the next step of determination is required;

[0061] Step 5b: If no PWM signal is detected, the logic control program will detect whether the current of the cascaded H-bridge branch crosses zero. If not, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if it crosses zero, the next step of determination is required;

[0062] Step 5c: If the logic judgment module detects that the current of the cascaded H-bridge branch passes through zero, after the circuit breaker in the control main circuit is disconnected, the branch voltage of the cascaded H-bridge equivalent circuit and the sum of the capacitor voltage are compared. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in a high-impedance state;

[0063] Step 6: Determine the current working state of each cascaded H-bridge branch according to the output result of the circuit breaker state logic determination module, and control the on and off of the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit according to different working states;

[0064] like Figure 3 As shown, when the circuit breaker state logic determination module determines that the branch is in the PWM working state, the main circuit breaker is controlled to be turned on, and the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off, and the system is in the normal working mode;

[0065] When the circuit breaker state logic determines that the branch is in an uncontrolled rectification state, the main circuit breaker is kept on, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off, and the system is in an uncontrolled rectification mode;

[0066] When the circuit breaker state logic judgment module determines that the branch is in a high-resistance state, the main circuit breaker is controlled to be turned off, and the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned on to short-circuit the equivalent controlled current source, thereby avoiding the continuous increase of the branch capacitor voltage caused by the branch current not being 0 and the capacitor being continuously charged with a small current due to the simulation result not being an ideal result;

[0067] Step 7: Load the main system circuit topology and several subsystem circuit topologies after equivalent segmentation into the FPGA of each simulator respectively, and load the circuit breaker state logic judgment module into the simulator CPU. Data is exchanged between simulators through optical fiber communication, and the synchronous operation of multiple simulators is ensured through the clock synchronization line;

[0068] The step 7 comprises the following steps:

[0069] Step 7a: Figure 4 As shown, each equivalent circuit topology after segmentation is loaded into the FPGA of each simulator respectively, and the logic control program is loaded into the simulator CPU;

[0070] Step 7b: FPGA converts the branch voltage V branc h. Submodule capacitor voltage Vcap And the branch current I branc h and other data are uploaded to the CPU, and the logic control program in the CPU sends the control instructions of each circuit breaker and bypass switch to the circuit breakers and bypass switches in the FPGA topology of each simulator;

[0071] Step 7c: Each simulator is connected through an optical fiber interface. Optical fiber communication is used to transmit data between different devices in parallel simulation. Clock synchronization lines are connected between each simulator. The function of clock synchronization wiring is to synchronize clock signals between different devices to ensure that different devices run in parallel within a unified clock cycle.

[0072] Step 8: Data is exchanged between each simulator and the controller through physical IO to achieve hardware-in-the-loop simulation of full physical IO of a large cascade H-bridge system with full-detail modeling.

[0073] Example 2

[0074] This embodiment provides a specific implementation example of SVG real-time simulation using the above method, and takes a 40-level SVG system as an example to verify the performance. Simulation model parameters: three-phase grid voltage is 35kV, grid frequency is 50Hz, SVG system level is 40, grid-side inductance parameter is 9mH, capacitance parameter is 7000uF, and rated voltage is 800V.

[0075] The controller hardware-in-the-loop testing method with full physical IO interaction of a large-scale cascade H-bridge application with full-detail modeling provided by the present invention is used to divide the original SVG system into three equivalent circuits according to the equivalent division method provided by the present invention, and load them into three simulators respectively; the main system simulator and the remaining subsystem simulators transmit data via optical fiber and synchronize via a clock synchronization line; the SVG controller is connected to the real-time simulator, and data information is exchanged between the SVG controller and the real-time simulation device provided by the present invention via physical IO, thereby realizing the controller hardware-in-the-loop testing with full physical IO interaction of the SVG system with full-detail modeling.

[0076] Figure 5 Contains three sub-images, Figure 5 (a) Figure 5 (b) Figure 5 (c) are the waveforms of the simulation results of the grid-side voltage, grid-side current and cascaded H-bridge capacitor voltage sampled by the simulator host computer. Figure 5 It can be seen that this simulation method can realize hardware-in-the-loop testing of full physical IO interaction with the controller; the simulator can accurately simulate the system voltage and current, and the voltage and current waveforms have good quality. At the same time, it can accurately simulate the ripple size and balancing effect of the sub-module voltage; therefore, the controller hardware-in-the-loop testing method with full physical IO interaction of a large cascade H-bridge application with full-detail modeling will show more accurate results.

[0077] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A real-time simulation method for large-scale cascaded H-bridge applications with full-detail modeling, characterized in that: The method steps include: The circuit topology of the large cascade H-bridge system is equivalently divided into a main system circuit topology and a plurality of subsystem circuit topologies, wherein the main system circuit topology is a power grid system, and the subsystem circuit topology is a cascade H-bridge system; Using controlled voltage sources and controlled current sources to perform equivalent replacement on the equivalently divided circuits, using multiple controlled voltage sources to equivalently replace each subsystem circuit topology in the main system circuit; using controlled current sources to equivalently replace the main system circuit in the subsystem circuit; Measure the branch current of the controlled voltage source in the main system circuit and give it to the controlled current source input in the corresponding subsystem circuit; measure the voltage across the controlled current source and give it to the corresponding controlled voltage source input in the main system circuit; A circuit breaker is provided for each controlled voltage source branch in the main system equivalent circuit, and a bypass switch is connected in parallel across the controlled current source in each subsystem circuit; Construct a circuit breaker state logic judgment module to judge the current working state of each cascaded H-bridge branch based on the PWM signal, branch voltage, branch current and submodule capacitor voltage of the cascaded H-bridge equivalent circuit in each subsystem, and control the on and off of the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit according to different working states; The main system circuit topology and several subsystem circuit topologies after equivalent segmentation are loaded into each simulator respectively, and the circuit breaker state logic judgment module is loaded into the simulator; data exchange is carried out between each simulator through optical fiber communication, and data exchange is carried out between each simulator and the controller through physical IO, realizing hardware-in-the-loop simulation of full physical IO of large-scale cascaded H-bridge system.

2. A real-time simulation method for large-scale cascaded H-bridge application with full-detail modeling according to claim 1, characterized in that: The circuit topology of the large cascaded H-bridge system is divided according to the specific cascade number of the cascaded H-bridge system and the topology size and IO channel number supported by the stand-alone simulator: when the actual cascade number of the system is n, the maximum simulation cascade scale supported by the stand-alone simulator is m, and the system topology is divided into at least n / m equivalent circuits. If n / m is not an integer, it is rounded up.

3. A real-time simulation method for large-scale cascaded H-bridge application with full-detail modeling according to claim 2, characterized in that: The equivalent division is to divide each phase of the large cascade H-bridge system circuit topology into a subsystem cascade H-bridge equivalent circuit or into multiple subsystem cascade H-bridge equivalent circuits.

4. A real-time simulation method for large-scale cascade H-bridge application with full-detail modeling according to claim 1, characterized in that: The switch states of the circuit breaker in the main system circuit topology and the bypass switch in the cascaded H-bridge equivalent circuit of the corresponding subsystem are opposite, that is, when the circuit breaker in the main circuit is turned on, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off; When the circuit breaker in the main circuit is turned off, the bypass switch in the cascaded H-bridge equivalent circuit of the corresponding subsystem is turned on.

5. A real-time simulation method for large-scale cascade H-bridge application with full-detail modeling according to claim 1, characterized in that: The circuit breaker state logic determination module is constructed to determine the current working state of each cascaded H-bridge branch as follows: The circuit breaker state logic judgment module detects whether there is a PWM signal in the branch of the cascaded H-bridge equivalent circuit of each subsystem. If there is a PWM signal, it is judged that the cascaded H-bridge branch is in the PWM working state; if no PWM signal is detected, it means that the cascaded H-bridge is in an uncontrolled rectification or high-impedance state, and the next step of judgment is carried out; If no PWM signal is detected, the circuit breaker state logic judgment module will detect whether the cascaded H-bridge branch current is zero-crossing. If it is not zero-crossing, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if it is zero-crossing, the next step of judgment is required; If the circuit breaker state logic judgment module detects that the current of the cascaded H-bridge branch passes through zero, the circuit breaker in the control main circuit is disconnected, and the branch voltage of the cascaded H-bridge equivalent circuit is compared with the sum of the capacitor voltage. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, it is judged that the cascaded H-bridge branch is in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, it is judged that the cascaded H-bridge branch is in a high-impedance state.

6. A real-time simulation method for large-scale cascade H-bridge application with full-detail modeling according to claim 5, characterized in that: The control of the on and off of the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit according to different working states is as follows: When the circuit breaker state logic judgment module determines that the cascaded H-bridge branch is in the PWM working state, the main system equivalent circuit breaker is controlled to be turned on, and the bypass switch of the corresponding subsystem-level cascaded H-bridge equivalent circuit is turned off, and the system is in the normal working mode; When the circuit breaker state logic determines that the branch is in an uncontrolled rectification state, the main system equivalent circuit breaker is kept turned on, the bypass switch of the cascaded H-bridge equivalent circuit in the corresponding subsystem is turned off, and the system is in an uncontrolled rectification mode; When the circuit breaker state logic judgment module determines that the branch is in a high-resistance state, the main system equivalent circuit breaker is controlled to be turned off, and the bypass switch of the corresponding subsystem-level intermediate H-bridge equivalent circuit is turned on to short-circuit the equivalent controlled current source.

7. A real-time simulation method for large-scale cascaded H-bridge application with full-detail modeling according to claim 1, characterized in that: The main system circuit topology and several subsystem circuit topologies after equivalent segmentation are respectively loaded into the FPGA of each simulator, and the circuit breaker state logic determination module is loaded into the simulator CPU; The FPGA uploads the branch voltage, submodule capacitor voltage, and branch current data to the CPU, and the logic control program in the CPU sends the control instructions of each circuit breaker and bypass switch to the circuit breakers and bypass switches in the FPGA topology of each simulator; Data exchange between simulators is carried out through optical fiber communication; The clock synchronization lines are connected between each simulator to synchronize the clock signals between different devices.

8. A real-time simulation system for large-scale cascaded H-bridge applications with full-detail modeling, characterized in that: The system includes a plurality of simulators; The FPGA of the simulator is loaded with the equivalent circuit topology of the large cascade H-bridge system after segmentation, and multiple controlled voltage sources are used in the main system circuit to equivalently replace the circuit topology of each subsystem; a controlled current source is used in the subsystem circuit to equivalently replace the main system circuit, and the branch current of the controlled voltage source in the main system circuit is measured and given to the controlled current source input in the corresponding subsystem circuit; the voltage across the controlled current source is measured and given to the corresponding controlled voltage source input in the main system circuit; The CPU of the simulator is loaded with a circuit breaker state logic determination module, which determines the current working state of each cascaded H-bridge branch based on the PWM signal, branch voltage, branch current and submodule capacitor voltage of the cascaded H-bridge equivalent circuit in each subsystem, and controls the on and off of the circuit breaker in the main system circuit and the bypass switch in each subsystem circuit according to different working states; Data is exchanged between simulators through optical fiber communication, and the synchronous operation of multiple simulators is ensured through clock synchronization lines; data is exchanged between simulators and controllers through physical IO, realizing hardware-in-the-loop simulation of full physical IO of large-scale cascaded H-bridge systems.

9. A large-scale cascade H-bridge application real-time simulation system with full-detail modeling according to claim 8, characterized in that: The circuit topology of the large cascaded H-bridge system is divided according to the specific cascade number of the cascaded H-bridge system and the topology size and IO channel number supported by the stand-alone simulator: when the actual cascade number of the system is n, the maximum simulation cascade scale supported by the stand-alone simulator is m, and the system topology is divided into at least n / m equivalent circuits. If n / m is not an integer, it is rounded up.

10. A large-scale cascade H-bridge application real-time simulation system with full-detail modeling according to claim 8, characterized in that: The circuit breaker state logic determination module is specifically as follows: Detect whether there is a PWM signal in the branch of the cascaded H-bridge equivalent circuit in each subsystem circuit. If there is a PWM signal, it is determined that the cascaded H-bridge branch is in a PWM working state; if no PWM signal is detected, it means that the cascaded H-bridge is in an uncontrolled rectification or high-impedance state, and the next step of judgment is performed; If no PWM signal is detected, the circuit breaker state logic determination module will detect whether the cascaded H-bridge branch current is zero-crossing. If it is not zero-crossing, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; If it is zero, proceed to the next step; If the logic judgment module detects that the current of the cascaded H-bridge branch passes through zero, after the circuit breaker in the control main circuit is disconnected, the branch voltage of the cascaded H-bridge equivalent circuit and the sum of the capacitor voltage are compared. If the absolute value of the branch voltage is greater than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in an uncontrolled rectification state; if the absolute value of the branch voltage is less than the sum of the capacitor voltage, it is determined that the cascaded H-bridge branch is in a high-impedance state; When the circuit breaker state logic judgment module determines that the branch is in the PWM working state, the main circuit breaker is controlled to be turned on, and the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off, and the system is in the normal working mode; When the circuit breaker state logic determines that the branch is in an uncontrolled rectification state, the main circuit breaker is kept on, the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned off, and the system is in an uncontrolled rectification mode; When the circuit breaker state logic determination module determines that the branch is in a high-resistance state, the main circuit breaker is controlled to be turned off, and the bypass switch of the corresponding cascaded H-bridge equivalent circuit is turned on to short-circuit the equivalent controlled current source.

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