Reducing boundary width around holes in display active area

Abstract

The invention relates to reducing a boundary width around an aperture in a display active area. An electronic device may include a display having display pixels formed in an active area of the display. The display also includes a display driver circuit for driving the gate lines routed across the display. Apertures, such as through-holes, optical windows, or other inactive areas, may be formed within the active area of the display. Multiple gate lines carrying the same signal may be merged together prior to routing around the hole to help minimize routing line congestion around the boundaries of the hole. A dummy circuit may be coupled to the merge segment portion to help increase parasitic loads on the merge segment. The aperture may have a tapered shape to help maximize the size of the effective area. The aperture may have an asymmetric shape to receive a plurality of sub-display sensor components.

Description

[0001] This application is a divisional application of the invention patent application with application number 202110267768.5, application date March 12, 2021, and invention name “Reducing the border width surrounding the hole in the display effective area”. Technical Field

[0002] The present disclosure relates generally to electronic devices, and more particularly to electronic devices having displays. Background Art

[0003] Electronic devices typically include displays. Displays are typically driven using display driver circuits and gate driver circuits. The display driver circuit provides data signals to corresponding display pixels via data lines, while the gate driver circuit provides control signals via gate lines to selectively load data signals into a subset of display pixels. Display pixels are formed in a region sometimes referred to as an active area. The design of a display with a rectangular uninterrupted active area is typically simple because the data lines and gate lines can be routed across the display in a regular grid-like pattern.

[0004] However, some displays deviate from conventional active areas and may have one or more holes or inactive areas within the active area. Routing data and gate lines in such types of displays with holes in the active area may be challenging. If care is not taken, the border of the display near the hole may become overcrowded and may result in an increased border width. Summary of the invention

[0005] An electronic device may include a display having an array of display pixels formed in an active area of ​​the display. One or more inactive areas may be formed in the active area. The inactive area may be a through hole, an optical window that is not a through hole, or other types of openings in the display that do not contain pixels. The display may also include a display driver circuit configured to output a control signal to a first row control line coupled to a first row of display pixels, and to output a control signal to a second row control line coupled to a second row of display pixels, wherein the first row control line and the second row control line are merged into a segment (i.e., a merged segment) that is routed through the inactive area. The control signal may be a scan line signal, an emission line signal, an initialization line signal, a reset signal, an enable signal, a data line signal, a reference signal, or other suitable data / control signals provided simultaneously to two or more pixel rows in the active area.

[0006] If desired, a dummy circuit such as a capacitor circuit may be coupled to the merging segment and may be configured to increase parasitics on the first row control line and the second row control line. The merging segment may be coupled between the first merging node and the second fan-out / splitting node. The first node may be connected to the first row control line and the second row control line. The merging segment may be configured to split into at least a first additional row control line and a second additional row control line at the second fan-out node.

[0007] The display driver circuit may be formed on one side of the display. The display may also include additional display driver circuitry configured to output an additional control signal to a third row control line coupled to a first row of display pixels and to output an additional control signal to a fourth control line coupled to a second row of display pixels. The third row control line and the fourth row control line may be merged into an additional segment that is routed through the inactive region. If desired, three or more parallel row control lines may be connected to the merged segment.

[0008] In one suitable arrangement, the inactive area may have a substantially rounded or circular shape. In another suitable arrangement, the inactive area may have a substantially rectangular shape. In yet another suitable arrangement, the inactive area may have a symmetrical or asymmetrical tapered shape optimized to increase the size of the active area. The row lines extending horizontally across the face of the display and the column lines extending vertically across the face of the display may both extend into the hole boundary area surrounding the inactive area. The hole boundary area may define the hole boundary width and may not overlap with the active area. In another suitable arrangement, when routing around the inactive area, only the row lines may extend into the hole boundary area, while the column lines do not extend into the hole boundary area but remain in the active area. In yet another suitable arrangement, when routing around the inactive area, only the column lines may extend into the hole boundary area, while the row lines do not extend into the hole boundary area but remain in the active area. The row / column lines that remain within the active area may overlap one or more display pixels and may be formed using an upper metal layer such as an anode layer, a source-drain metal wiring layer, or one of the touch sensor layers, or using a buried metal layer formed above the substrate layer and below the low-temperature polysilicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram of an illustrative electronic device with a display according to an embodiment.

[0010] Figure 2 is a top plan view of an exemplary display in an electronic device according to an embodiment.

[0011] Figure 3 is a top plan view of a display circuit according to an embodiment showing how multiple rows of single-sided gate driver circuits may be configured to drive corresponding gate lines that are merged prior to routing around holes in the display active area.

[0012] Figure 4A is a cross-sectional side view of an exemplary through hole that may be formed in a display active area according to an embodiment.

[0013] Figure 4B is a cross-sectional side view of an exemplary optical window that may be formed in a display active area according to an embodiment.

[0014] Figure 5 is a top plan view showing how merging and splitting of gate lines may occur from both sides of a hole, according to an embodiment.

[0015] Figure 6 is a top plan view of an exemplary display circuit according to an embodiment, showing how multiple rows of single-sided gate driver circuits may be configured to drive corresponding gate lines that are merged prior to routing directly on the optical window.

[0016] Figure 7 is a diagram showing how three or more control lines may be connected together at the edge of a hole, according to an embodiment.

[0017] Fig. 8A is a top plan view showing that a dummy load circuit may be attached adjacent a smaller hole, according to an embodiment.

[0018] FIG. 8B to FIG. 8F is a diagram showing holes of different sizes and shapes that may be formed in a display active area according to some embodiments.

[0019] Fig. 9A is a top plan view showing a minimum aperture boundary envelope associated with a data line routed around the aperture, according to an embodiment.

[0020] Fig. 9B is a diagram showing how the effective area is displayed according to an embodiment Fig. 9A Top plan view of the minimum hole boundary envelope constraint shown in .

[0021] Fig. 10A is a diagram showing how reshaping of a hole may reduce the size of a minimum hole boundary envelope, according to an embodiment.

[0022] Fig. 10B is a diagram showing how a hole may be tapered asymmetrically, according to an embodiment.

[0023] Fig.11 is a top plan view of an illustrative touch sensing circuit according to an embodiment, showing how multiple rows of single-sided touch sensing circuits may be coupled to corresponding sense lines that are shorted together before being routed around holes in the active area.

[0024] Fig. 12Ais a top plan view showing row and column lines routed in a hole boundary region outside an active area according to an embodiment.

[0025] Fig. 12B is a top plan view showing row lines routed in a hole boundary region and column lines routed in an active area according to an embodiment.

[0026] Fig. 12C is a top plan view showing column lines routed in a hole boundary region and row lines routed in an active area according to an embodiment.

[0027] Fig.13 is a cross-sectional side view of an exemplary display stack structure according to an embodiment.

[0028] Fig.14 is a cross-sectional side view of an exemplary thin film transistor (TFT) layer according to an embodiment.

[0029] Fig.15 is a cross-sectional side view showing one suitable arrangement of a buried metal layer, according to an embodiment.

[0030] Fig.16 is a cross-sectional side view illustrating another suitable arrangement of a buried metal layer according to an embodiment. DETAILED DESCRIPTION

[0031] This patent application claims priority to U.S. patent application No. 17 / 145,815 filed on January 11, 2021 and U.S. Provisional Patent Application No. 63 / 001,949 filed on March 30, 2020, which are hereby incorporated by reference in their entirety.

[0032] Figure 1 An illustrative electronic device of the type that may have a display is shown in FIG. Figure 1 The electronic device 10 may be a tablet computer, a laptop computer, a desktop computer, a monitor including an embedded computer, a monitor not including an embedded computer, a display used with a computer or other equipment external to the display, a cellular phone, a media player, a watch device or other wearable electronic equipment such as a head-mounted device, or other suitable electronic device.

[0033] like Figure 1As shown, electronic device 10 may have control circuitry 16. Control circuitry 16 may include storage and processing circuitry for supporting the operation of device 10. Storage and processing circuitry may include storage devices such as hard drive storage devices, non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random access memory), etc. Processing circuitry in control circuitry 16 may be used to control the operation of device 10. The processing circuitry may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors, power management units, audio chips, application specific integrated circuits, etc.

[0034] Input-output circuitry in device 10, such as input-output devices 12, may be used to allow data to be provided to device 10, and to allow data to be provided from device 10 to external devices. Input-output devices 12 may include buttons, joysticks, scroll wheels, touch pads, keypads, keyboards, microphones, speakers, audio generators, vibrators, cameras, sensors, light-emitting diodes and other status indicators, data ports, etc. A user may control the operation of device 10 by supplying commands through the input resources of input-output devices 12, and may receive status information and other output from device 10 via the output resources of input-output devices 12.

[0035] Input-output devices 12 may include one or more displays, such as display 14. Display 14 may be a touch screen display that includes a touch sensor for acquiring touch input from a user, or display 14 may be insensitive to touch. The touch sensor of display 14 may be based on an array of capacitive touch sensor electrodes, an acoustic touch sensor structure, a resistive touch component, a force-based touch sensor structure, a light-based touch sensor, or other suitable touch sensor arrangements.

[0036] Control circuitry 16 may be used to run software on device 10, such as operating system code and application programs. During operation of device 10, software running on control circuitry 16 may use the pixel array in display 14 to display images on display 14. Display 14 may have a generally rectangular shape (i.e., display 14 may have a rectangular footprint and a rectangular perimeter edge extending around the rectangular footprint) or may have other suitable shapes. Display 14 may be planar or may have a curved profile. Display 14 may be an organic light emitting diode display, a liquid crystal display, a liquid crystal on silicon display, a micro-electromechanical system (MEM) display, or other suitable type of display.

[0037] It may be desirable to incorporate electronic components into device 10 and / or into or beneath display 14. For example, component 18 may be an audio component (e.g., a microphone, a speaker, etc.), a radio frequency component, a tactile component (e.g., a piezoelectric structure, a vibrator, etc.), may be a capacitive touch sensor component or other touch sensor structure, may be a temperature sensor, a pressure / force sensor, a magnetic sensor, a fingerprint sensor, or other sensor, or may be any other suitable type of electronic component. With one suitable arrangement that may sometimes be described herein as an example, electronic component 18 may be a light-based sensor component (e.g., an ambient light sensor, a proximity sensor, or a component that emits and / or detects visible light, infrared light, and / or ultraviolet light).

[0038] Examples of light-based components 18 that emit light include light emitting diodes (e.g., organic light emitting diodes, discrete crystalline light emitting diode dies, etc.), lasers, and lamps. Examples of light-based components that detect light include light detectors, such as photodiodes and phototransistors. If desired, some components may include both light emitters and detectors. For example, component 18 may emit infrared light and may include a light detector structure for detecting a portion of the emitted light that has been reflected from a nearby object. This type of component may be used to implement a proximity sensor.

[0039] Figure 2 FIG. 1 is a top plan (layout) diagram of an exemplary display 14 in the electronic device 10. Figure 2 As shown, the display 14 may have a pixel array 22 formed by a substrate structure such as a substrate 36. The area on the substrate 36 where the array of pixels 22 is formed is sometimes referred to as an "active area" (AA). One or more areas outside the area effective may be referred to as an inactive area or inactive area. A substrate such as substrate 36 may be formed of glass, metal, plastic, ceramic, or other substrate materials. The pixel 22 may receive a data signal via a signal path such as a data line D, and may receive one or more control signals via a control signal path such as a gate line G (sometimes referred to as a control line, a scan line, an emission enable line, a gate signal path, etc.). There may be any appropriate number of rows and columns of pixels 22 in the display 14 (e.g., tens or more, hundreds or more, or thousands or more). The pixel 22 may have different colors (e.g., red, green, and blue) to provide the display 14 with the ability to display color images. The pixel circuit in the pixel 22 may include a transistor (e.g., a thin film transistor on the substrate 36) having a gate controlled by a gate line signal on the gate line G. The terms "row" and "column" may be used to refer to any array of display pixels, and are sometimes used interchangeably (eg, gate lines may also be referred to as column lines, and data lines may be referred to as row lines).

[0040] The display driver circuit 20 may be used to control the operation of the pixel 22. The display driver circuit 20 may be formed by an integrated circuit, a thin film transistor circuit, or other suitable circuit. The thin film transistor circuits used for the display driver circuit 20 and the pixel 22 may be formed by polysilicon thin film transistors, semiconductor oxide thin film transistors (such as indium gallium zinc oxide (IGZO) transistors), or thin film transistors formed of other semiconductor materials.

[0041] The display driver circuit 20 may include display driver circuits such as a display driver circuit 20A and a gate driver circuit 20B. The display driver circuit 20A may include a display driver circuit 20A-1 formed of one or more display driver integrated circuits (e.g., a timing controller integrated circuit) and / or a thin film transistor circuit, and may include a demultiplexer circuit 20A-2 (e.g., a demultiplexer formed of a thin film transistor circuit or formed in an integrated circuit). The gate driver circuit 20B may be formed of a thin film transistor circuit or may be formed in a gate driver integrated circuit.

[0042] Display driver circuit 20A may include circuitry for communicating with system control circuitry such as a display driver circuit 20A via path 32. Figure 1 Path 32 may be formed by traces or other conductive lines on a flexible printed circuit. During normal operation, the control circuit (e.g., Figure 1 The control circuit 16 of the display 14 can provide information to the circuit 20A about the image to be displayed on the display 14. In order to display the image on the display pixel 22, the display driver circuit 20A can provide image data to the data line D while issuing control signals (e.g., clock signals, gate start pulses, etc.) to supporting display driver circuits such as the gate driver circuit 20B through the path 38. The display driver circuit 20A can also dynamically adjust the demultiplexer circuit 20A-2 by providing clock signals, selection signals and / or other control signals to the demultiplexer circuit 20A-2. If desired, the gate driver circuits can optionally be formed on more than one side of the display 14 (see, for example, the gate driver circuits 20B' formed at opposite edges of the substrate 36). In such an arrangement, the display driver circuit 20A can also issue control signals to the supporting gate driver circuits 20B' through the path 38'.

[0043] Figure 31 is a top plan view of one implementation of display 14 when viewed from the front of the display surface in a direction Z toward the XY plane, illustrating how multiple rows of single-sided gate drivers may be used to drive corresponding gate lines routed around holes in the active area. In one suitable arrangement, display 14 may be substantially coplanar with the XY plane (i.e., the display substrate is formed in a single plane). In another suitable arrangement, display 14 may alternatively be curved and protrude from the XY plane. In general, device 10 (and display 14) may exhibit any suitable shape.

[0044] exist Figure 3 In the example, the gate driver circuit 20B is formed only on one edge of the display (i.e., no gate driver circuit 20B' is formed at the right edge of the display). The gate driver circuit 20B may include a plurality of gate drivers 21 configured to drive corresponding gate lines G. The gate driver 21-1 may be configured to drive a first gate line pair coupled to a first row and a second row of display pixels 22. The gate driver 21-2 may be configured to drive a second gate line pair coupled to a third row and a fourth row of display pixels 22. The gate driver 21-3 may be configured to drive a third gate line pair coupled to a fifth row and a sixth row of display pixels 22. In Figure 3 , each individual gate driver circuit 21 may be configured to generate a corresponding row control signal A, but the waveforms output from each circuit 21 may be offset in time relative to each other. For example, circuit 21-1 may output control signal A(1); circuit 21-2 may output control signal A(2); circuit 21-3 may output control signal A(3); and so on.

[0045] In certain embodiments, a hole such as hole 300 may be formed within the display active area. Hole 300 may be at least partially or completely surrounded by the active area. The term "hole" may generally refer to an area within the active area that does not include any display pixels, and may be a through hole (e.g., an opening formed from the top surface of the display substrate all the way through the bottom surface of the display substrate), an optical window (e.g., a portion of a continuous display substrate through which light signals may still pass through the substrate), or other inactive areas.

[0046] Figure 4A is a cross-sectional side view of an exemplary through hole that may be formed in the display active area. Figure 4A As shown, the display may generally include a substrate layer 400 (which may be equivalent to a bonding Figure 2The substrate 36 described above, a thin film transistor (TFT) wiring layer 402 formed on the substrate 400, and an encapsulation layer 404 covering the TFT wiring layer 402. Display pixel structures and associated wiring lines, display driver circuits, and / or gate driver circuits can be formed within the TFT wiring layer 402. The encapsulation layer 404 may include some combination of organic layers and inorganic layers configured to help prevent moisture and / or other contaminants from penetrating into the TFT wiring layer 402.

[0047] exist Figure 4A In the example of FIG. 4 , hole 300 may be implemented as a through hole that extends completely through display substrate layer 400 (i.e., inactive region 300 may be a hole drilled or cut through the entire thickness of substrate 400). If desired, one or more components such as a combination Figure 1 The type of light sensor 18 described may be located directly below the hole 300 so that light or other signals may traverse the hole 300 to reach the sensor 18. The hole 300 may be defined by the substrate edge 490. The TFT wiring layer 402 must be formed at a minimum distance Δ from the substrate edge 490 so that the encapsulation layer 404 can be properly formed (e.g., so that the encapsulation layer 404 can be tapered). Therefore, this minimum distance Δ is sometimes referred to as a package trim margin. Therefore, the distance Δ defines the closest point at which a control line wiring segment (which is formed within the TFT wiring layer 402) can be formed relative to the edge of the hole 300.

[0048] Figure 4B FIG. 4 is a cross-sectional side view of an exemplary optical window that can be formed in a display active area according to another suitable embodiment. Figure 4B As shown, the display may generally include a substrate layer 400, a thin film transistor (TFT) wiring layer 402 formed on the substrate 400, and an encapsulation layer 404 covering the TFT wiring layer 402. The display pixel structure and associated wiring lines, display driver circuits, and / or gate driver circuits may be formed within the TFT wiring layer 402. The encapsulation layer 404 may include some combination of organic layers and inorganic layers configured to help prevent moisture and / or other contaminants from penetrating into the TFT wiring layer 402.

[0049] exist Figure 4B In the example of FIG. 4 , the hole 300 can be implemented as an optical window that allows light or other signals to pass through the substrate 400. Figure 4A The cut-through holes in the Figure 4B The optical window 300 of FIG. 300 includes a continuous substrate layer 400 that completely overlaps the window 300 (when the front of the display is viewed from above). Since there is no interruption in the substrate 400 in the inactive aperture area 300, the encapsulation layer 404 can also be formed over the aperture area 300. The presence of layers 400 and 404 will not block light or other desired signals from traversing the optical window 300.

[0050] If necessary, one or more components such as a combination Figure 1 The type of optical sensor 18 described can be located directly below the optical window 300, so that light or other signals can pass through the window 300 to reach the sensor 18. Since the substrate is not actually cut in the optical window 300 (i.e., there is no substrate edge in the optical window area), the TFT wiring layer 402 is not constrained by any packaging trim margin. Therefore, the TFT wiring layer 402 can be formed all the way to the edge of the optical window 300. Compare Figure 4A and Figure 4B , it can be seen that the TFT wiring layer 402 can be Figure 4B In the optical window configuration of the embodiment of the present invention, the control line wiring segments (which are formed within the TFT wiring layer 402) can be formed closer to the edge of the hole 300. In other words, when the hole 300 is implemented as an optical window, the control line wiring segments (which are formed within the TFT wiring layer 402) can be formed closer to the boundary of the hole 300, which can help to reduce the overall hole boundary width.

[0051] Re-reference Figure 3 , the gate lines formed above and below the inactive region 300 can be straight and can be coupled to the display pixels 22 spaced at regular intervals (see, for example, the gate lines G driven by the circuits 21-1 and 21-3). In contrast, the gate lines formed in the rows overlapping the hole 300 must be routed around the hole 300 (see, for example, the gate lines G driven by the circuit 21-2). In a conventional display with multiple rows of gate driver circuits, the two gate lines in each gate line pair would have to be routed around the border of the hole 300, resulting in routing line congestion, which would significantly increase the minimum required border width around the hole 300.

[0052] According to an embodiment, a multi-row driving scheme may have multiple routing lines merged before routing around hole 300. Figure 3 As shown, each driver circuit 21 can be a multi-row driver circuit configured to generate a control signal A (e.g., a scan line signal, an emission line signal, or other row control signal) that is simultaneously fed to two adjacent pixel rows. In other words, circuit 21 can be configured to output signal A(n) to rows n and (n+1). For example, driver circuit 21-2 can be configured to drive control signal A to a first linear / straight line segment coupled to a third row of pixels in an effective area on the left side of hole 300, and to a second linear / straight line segment coupled to a fourth row of pixels in an effective area on the left side of hole 300. The second linear segment can be merged with the first linear segment via a connection / short circuit segment 802, so that the first linear (straight line) segment and the second linear (straight line) segment are joined or merged at a node 804. From this point on, a single (merged) routing line or merged segment 805 (sometimes referred to as an intermediate routing segment) can be routed around and along the boundary of hole 300 to reach the effective area on the right side of hole 300.

[0053] A merged routing segment (which may be curved or have any suitable trajectory, depending on the shape of aperture 300) may extend from node 804 to node 806. At node 806, merged routing segment 805 may be split into a third linear segment and a fourth linear segment using fan-out segment 808. The third linear segment may be coupled to a third row of pixels in the active area to the right of aperture 300, and the fourth linear segment may be coupled to a fourth row of pixels in the active area to the right of aperture 300.

[0054] although Figure 3 Only six pixel rows are shown, but the display may generally include any number of gate driver circuits (e.g., hundreds or thousands of individual multi-row gate drivers) formed at the left and / or right edges of the display, each gate driver circuit capable of outputting gate line signals or row control signals to two or more rows of display pixels. Figure 3 The examples are merely illustrative and are not intended to limit embodiments of the present invention. In general, aperture 300 may have X and / or Y dimensions that span 2 to 10 displays, 10 to 100 pixels, hundreds or thousands of pixels, etc. (e.g., aperture 300 has a Y dimension that spans any suitable number of pixel rows and an X dimension that spans any suitable number of pixel columns). Thus, any intermediate merged segments routed around aperture 300 may potentially represent a path that is several microns to several millimeters in length that is not interrupted by pixels.

[0055] The merged wiring segment 805 connected between nodes 804 and 806 may be completely free of pixels 22 (i.e., no pixels are connected to the intermediate wiring segment routed around hole 300). Therefore, the number of pixels formed along the entirety of such a gate line may differ from the number of pixels for a gate line in a normal pixel row having pixels formed at regular, non-interrupted intervals (see Figure 3 , where the number of pixels 22 connected to the first gate line feeding the first pixel row is greater than the number of pixels connected to the third gate line feeding the third pixel row). To help match the load of the wiring lines coupled to fewer display pixels to the load on the normal gate lines, dummy circuit components such as dummy circuit 850 can be coupled to the merged wiring segments that do not contain pixels to help simulate the load of the display pixels that are not obstructed by the hole 300 formed between the merged node and the split node. Dummy circuit 850 can be a capacitor circuit, a dummy transistor structure, a dummy pixel structure, an invalid electronic component, or other suitable load component that occupies a minimum circuit area to help reduce wiring congestion around the hole 300. Intentionally providing parasitic loads in this way to balance the load between all row control lines / wiring lines can help reduce undesirable display artifacts.

[0056] The above article targets Figure 3 The merging of wiring lines at one edge of the aperture 300 and the splitting / fanning out of wiring lines at the other edge of the aperture 300 described for the multiple rows of gate driver circuits 21-2 may also be applied to multiple gate drivers 21' formed along opposite edges of the display (see, e.g. Figure 5 ).like Figure 5 As shown, the multi-gate driver 21' can be configured to output the control signal B to at least two pixel rows in parallel (for example, the circuit 21' can be configured to output the signal B(n) to rows n and (n+1). The hole 300 can be at least partially physically inserted between the circuits 21 and 21'. Figure 5 As shown, the merging of linear gate line segments originating from circuit 21' can occur at node 820, and fanning out into multiple linear gate line segments after routing around hole 300 can occur at node 822. The merged wiring segment 821 coupled between nodes 820 and 822 can help reduce routing line congestion of gate lines associated with multiple rows of driver circuits 21'. Since routing congestion determines the minimum hole border width, merging or shorting multiple rows of control lines in this manner can significantly reduce the border width around hole 300. If desired, a dummy circuit 850 can also be attached to the intermediate wiring segment 821 to facilitate load balancing.

[0057] The combined wiring lines are routed around the periphery of the hole 300 Figure 3 and Figure 5 The example is merely exemplary. When the hole 300 is implemented as a combination Figure 4A When the type of through-hole described above is implemented as another structure that prevents or prohibits routing of routing lines through the inactive hole area, routing around or around the hole 300 may be necessary. In other suitable arrangements, such as when the hole 300 is implemented as Figure 4B When an optical window of the type shown is used, the combined wiring lines can be routed directly above and through the hole area 300, such as Figure 6 In other words, the control lines routed across the hole 300 do not have to be routed along the boundaries of the hole 300 and can be kept as straight / straight line segments. Such a routing configuration can be used as long as the hole 300 is not implemented as a through-hole.

[0058] The plurality of row gate driver circuits are configured to drive control signals to pixels arranged along two adjacent rows. Figure 3 , 5 The examples of and 6 are merely exemplary and are not intended to limit the scope of the embodiments of the present invention. Generally speaking, a single peripheral driver circuit such as Figure 7The multi-row driver circuit 21 shown can be configured to simultaneously generate corresponding control signals A (e.g., scan signals, emission signals, initialization signals, reference signals, reset signals, enable signals, row control signals, column control signals, etc.) to more than two control lines (e.g., three or more row control lines in adjacent / continuous rows, three or more row control lines in non-adjacent / non-continuous rows, 4-10 row control signals in adjacent or non-adjacent rows, etc.), wherein multiple row control lines carrying the same signal waveform output from the circuit 21 are merged or connected at a short-circuit node 904, and wherein the merged single wiring segment 905 is routed around the hole 300 or directly through the hole 300.

[0059] The display 14 includes a hole 300 Figures 3 to 7 The embodiments of the present invention are merely exemplary and are not intended to limit the scope of the embodiments of the present invention. According to some embodiments, the display may include two or more holes formed in the active area (see, for example, Fig. 8A ).like Fig. 8A As shown, the display 14 may include at least a first hole 300-1 and a second hole 300-2 formed in the active area. Each of the holes 300-1 and 300-2 may correspond to a connection Figure 4A The type of through-hole, combined Figure 4B The type of optical window described above, or other inactive area that does not contain display pixels. Apertures 300-1 and 300-2 do not need to be the same size and shape. Fig. 8A In the example of FIG. 1 , holes 300 - 1 and 300 - 2 have different sizes and shapes (eg, hole 300 - 1 may be larger than hole 300 - 2 ; hole 300 - 1 may be circular, while hole 300 - 2 may be oval).

[0060] In such an arrangement, potential routing congestion near the border of the larger hole 300-1 may be more pronounced than routing congestion near the border of the smaller hole 300-2, since the smaller hole 300-2 necessarily occupies less space. Fig. 8AAs shown, the merged wiring segment connecting the node 804 in the active area to the left of the hole 300-1 to the node 806 in the active area to the right of the hole 300-2 can have more space for routing near the smaller hole 300-2 (e.g., the intermediate wiring segment connecting the nodes 804 and 806 can have a first meandering portion that needs to be routed around the hole 300-1 and a second straight portion that takes a more direct path to the node 806). Since there is more free circuit area around the smaller hole 300-2, the dummy load circuit can be physically formed near the smaller hole. For example, the first dummy load component 850A coupled to the first merged wiring segment 805 carrying the control signal A can be formed in the free space above the hole 300-2 (when viewed from the front of the display in the direction Z toward the XY plane), while the second dummy load component 850B coupled to the second merged wiring segment 821 carrying the control signal B can be formed in the free space below the hole 300-2. Therefore, in general, it may be desirable to form a dummy load circuit near, around, or at the boundary of the smaller inactive area.

[0061] In general, the one or more inactive apertures within the active area of ​​the display may have any suitable shape and / or size, and there may be any desired number of apertures of the same or different sizes / shapes. Figure 8B is a diagram showing that three or more circular holes 300 - 1 , 300 - 2 , and 300 - 3 having different sizes may be formed in an active area of ​​a display. Figure 8C is a diagram showing that two or more rectangular holes 300 - 1 and 300 - 2 (eg, holes of a shared shape) having different sizes may be formed in an active area of ​​a display. Fig.8D is a diagram showing how a display may be provided with at least two circular apertures 300-1 and 300-2, at least a square aperture 300-3 and / or a smaller triangular aperture 300-4 of the same size and shape. Fig. 8E It is shown how a display may include at least a larger aperture 300-1 having an asymmetric arc and a smaller aperture 300-2 having a circular border on one side and a rectangular border on the other side. Figure 8F Another suitable embodiment is shown in which the apertures 300 have asymmetric tapered borders (e.g., a left portion of the aperture 300 has a more elongated tapered curved border, while a right portion of the aperture 300 has a relatively shorter tapered curved border). Each aperture 300 may have one or more curved edges (e.g., a convex border or a concave border) and / or one or more straight edges.

[0062] The minimum required border width at the edge of the aperture 300 can determine how close a display pixel can be formed from the edge of the aperture, and can therefore constrain the size of the active area if the border width is too large. Fig. 9Ais a top plan view showing a minimum aperture boundary envelope 1100 associated with a data line routed around aperture 300. Fig. 9A As shown, a plurality of data lines D extending in the Y direction toward the hole 300 may need to be routed around the hole 300 (for example, a data line extending from the top of the hole 300 may have a first middle section extending westward along the top edge of the hole 300, a second middle section extending southward along the left edge of the hole 300, and a third middle section extending eastward along the bottom edge of the hole 300), assuming that they cannot be as Figure 4B 100. Each successive data line may be routed further away from the edge of the aperture 300, which infers the closest point at which a display pixel may be formed along the vertical segment of each data line. Thus, the minimum aperture boundary envelope 1100 may depict the location at which the closest display pixel may be formed along the data line relative to the edge of the aperture 300 (i.e., display pixels cannot be formed inside the envelope 1100 and should only be formed outside the envelope 1100). Assuming that the data lines are also routed around the right edge of the aperture 300, a similar envelope may also exist for the right half of the aperture 300.

[0063] Fig. 9B The minimum boundary envelope 1100 of the left half of the hole 300 and the minimum boundary envelope 1100' of the right half of the hole 300 are shown. Envelopes 1100 and 1100' can both be associated with a routing pattern of data lines that are routed substantially in the Y direction. Figure 2 , 3 As shown in FIGS. 5-8 , control lines such as gate lines, scan lines, emission lines or other row control lines are also routed substantially in the X direction, and the control lines in the rows overlapping the hole 300 may need to be routed around the hole 300. Fig. 9A As shown, these row control lines that are required to surround the aperture 300 may also have an associated minimum aperture boundary envelope 1102 that depicts the position at which the nearest display pixel can be formed along the row control lines relative to the edge of the aperture 300 (i.e., display pixels also cannot be formed within the envelope 1102 and should only be formed outside the envelope 1102).

[0064] exist Fig. 9BIn the example of , the envelope associated with the column-extended data lines (i.e., envelopes 1100 and 1100') may have an overall footprint that is larger than the envelope associated with the row-extended gate lines (i.e., envelope 1102). Therefore, the edge of the active area (AA) as depicted by dashed line 1104 may be constrained by the dimensions of envelopes 1100 and 1100'. This may not always be the case. In other arrangements, the envelope associated with the row-extended gate lines may have an overall footprint that is larger than the envelope associated with the column-extended data lines (e.g., the footprint of envelope 1102 is larger than envelopes 1100, 1100'). In such cases, the active area may be constrained by the dimensions of envelopes 1100 and 1100'. The above in combination Figure 3 and 5 -8 The technique of reducing routing congestion at the border of hole 300 can be used to help minimize the size of envelope 1102 so that the active area size is no longer limited by the row line routing pattern, thereby increasing the size of the active area.

[0065] Fig. 10A is a diagram showing how reshaping of a hole can reduce the size of the minimum hole boundary envelope, according to an embodiment. Fig. 10A As shown, a hole such as hole 300' (e.g., a through hole, an optical window, or other ineffective display area) may have an edge that tapers inwardly at an angle α relative to the X-axis. The angle α at which the hole edge narrows may be equal to the angle α at which the cladding 1100 extends outwardly from the rectangular hole 300 (see, e.g., Fig. 9B ). In this manner, tapering the aperture 300' can counteract the increased routing line congestion introduced by the continuous data line being routed around the aperture 300' (e.g., the narrowing aperture shape effectively leaves room for the data line to be routed in the area that would otherwise be occupied by the rectangular aperture). So configured, the resulting minimum aperture boundary envelope 1101 will have a substantially smaller Fig. 9B The overall footprint of the envelope 1100 / 1100' in FIG. 1 is an overall footprint of the envelope 1100 / 1100', which can further increase the size of the display active area.

[0066] wherein the hole 300' has a symmetrical conical shape Fig. 10A The examples are merely illustrative and are not intended to limit the scope of the present embodiment. Fig. 10B Another suitable arrangement is shown, in which a hole such as hole 300 (eg, a through hole, an optical window, or other inactive display area) has an asymmetric tapered shape. Fig. 10B As shown, the hole 300" may have a left portion that tapers at an angle α relative to the X-axis and a right portion that tapers at an angle θ relative to the X-axis. Such a detuned hole shape may be used, for example, to accommodate two or more electronic components from below the display (e.g., a first larger sensor 18-1 may be formed in a wider opening portion of the hole 300", while a second smaller sensor 18-2 may be formed in a narrower opening portion of the hole 300". Thus, Fig. 10B The asymmetric aperture can simultaneously allow signals to pass through to multiple sub-display components while minimizing the minimum aperture border envelope associated with vertical wiring lines extending in the Y direction, which results in an overall reduction in border width around aperture 300" and a larger overall active area of ​​the display. In general, the aperture or inactive area within the active area of ​​the display can have any suitable size or shape to accommodate any suitable number of sensor components (for example, the shape of the aperture or inactive area can also be optimized to reduce the aperture border width to maximize display active area coverage).

[0067] If necessary, combine Figure 2-1 The techniques described in 0 for reducing routing congestion of display control lines routed around holes or inactive areas can also be extended to touch sensor circuits (see, e.g. Fig.11 ). Fig.11 1 is a top plan (layout) diagram showing how multiple rows of touch sensing circuits 1300 formed on the left edge of an electronic device and multiple rows of touch sensing circuits 1300' formed on the right edge of an electronic device can be coupled to corresponding sensing lines that are shorted together before routing around holes 300 in an active area (e.g., vias, optical windows, or other non-display inactive areas). Fig.11 As shown, multiple touch control lines 1302 may be merged at node 1304 before routing around the boundary of hole 300. The merged routing line segment (which is a single intermediate routing line connecting node 1304 to node 1306) may be split into multiple parallel lines at fan-out node 1306 for the active area to the right of hole 300. If desired, the methods and circuits described herein may be extended to any type of signal or power line that must be routed around or across a hole with the goal of minimizing routing congestion near the hole.

[0068] Fig. 12A is a top plan (layout) diagram showing the routing of row and column lines in the hole boundary region outside the active area. Fig. 12A As shown, row lines (e.g., gate lines G, scan lines, emission lines, initialization lines, reset lines, reference lines, and / or other row extension control lines) and column lines (e.g., data lines D, positive power lines, ground power lines, and / or other column extension control lines) near the hole 300 can all be routed in the hole boundary region surrounding the hole 300. The hole boundary region can be defined on one side by the edge of the hole 300 and on the other side by the edge of the active area (as defined by the dashed line 1202). Defined in this manner, the hole boundary region and the active area are non-overlapping regions. Therefore, the hole boundary region surrounding the hole 300 can exhibit a hole boundary width 1204. As described above in conjunction with Fig. 9B As described, the techniques for reducing routing congestion at the border of the hole 300 may be used to help minimize the hole border area (ie, reduce the hole border width), thereby increasing the size of the active area.

[0069] To further maximize the size of the active area, Fig. 12B Another suitable arrangement is shown, in which only the row lines are routed in the hole boundary region, while the column lines are routed outside the hole boundary region and inside the active area (see, for example, data line D is routed inside the active area edge 1212 and does not extend into the hole boundary region). Routing only the row control lines in the hole boundary region can further reduce the hole boundary width 1214. If desired, the row lines routed around the perimeter of the hole 300 can also be merged to help further reduce the hole boundary width. In order to be able to form the column lines in the active area, the column lines can be formed in the upper metal wiring layer above the pixel transistor or in the buried metal layer below the pixel transistor (see below in conjunction with Figure 13-16 As described above). Formed in this way inside the active area, the column lines can be routed directly above or below one or more pixels 22 in the active area. On the other hand, the portion of the column lines extending into the hole boundary region will not overlap with any pixel because no pixel is formed in the retainer boundary region.

[0070] Fig. 12C Yet another suitable arrangement is shown, in which only the column lines are routed inside the hole boundary region, while the row control lines are routed outside the hole boundary region and inside the active area (see, for example, that the gate line G is routed inside the active area edge 1222 and does not extend into the hole boundary region). Routing only the column lines inside the hole boundary region can further reduce the hole boundary width 1224 and thus maximize the size of the active area. In order to be able to form the row control lines in the active area, the row lines can be formed in the upper metal wiring layer above the pixel transistor or in the buried metal layer below the pixel transistor (see below in conjunction with Figure 13-16 Formed in this manner within the active area, the row lines may be routed directly above or below one or more pixels 22 in the active area.

[0071] Fig.13 is a cross-sectional side view of an exemplary display stack structure according to an embodiment. Fig.13 As shown, the display stack may include a backing film 1300 and a substrate layer, such as a substrate 1302 formed on the backing film 1300. The substrate 1302 may be formed of glass, metal, plastic, ceramic, sapphire, or other suitable substrate materials. In some arrangements, the substrate 1302 may be an organic substrate formed of polyimide (PI), polyethylene terephthalate (PET), or polyethylene naphthalate (PEN) (as examples). The surface of the substrate 1302 may optionally be covered with one or more buffer layers (e.g., an inorganic buffer layer, such as a silicon oxide layer, a silicon nitride layer, etc.).

[0072] A thin film transistor (TFT) layer 1304 may be formed over substrate 1302. TFT layer 1304 may include thin film transistor circuits, such as thin film transistors, thin film capacitors, associated routing circuits, and other thin film structures formed within a plurality of alternating metal wiring layers and dielectric layers. An organic light emitting diode (OLED) layer 1306 may be formed over TFT layer 1304. OLED layer 1306 may include a cathode layer, an anode layer, and an emissive material interposed between the cathode layer and the anode layer.

[0073] The circuits formed in the TFT layer 1304 and the OLED layer 1306 can be protected by the encapsulation layer 1308. For example, the encapsulation layer 1308 can include a first inorganic encapsulation layer, an organic encapsulation layer formed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer formed on the organic encapsulation layer. Encapsulation layer 1308 formed in this manner can help prevent moisture and other potential contaminants from damaging the conductive circuits covered by layer 1308.

[0074] One or more polarizing films 1312 may be formed over the encapsulation layer 1308 using an adhesive layer 1310. The adhesive 1310 may be implemented using an optically clear adhesive (OCA) material that provides high light transmittance. One or more touch layers 1316 that implement the touch sensor function of the touch screen display 14 may be formed over the polarizing film 1312 using an adhesive 1314 (e.g., an OCA material). For example, the touch layer 1316 may include horizontal touch sensor electrodes and vertical touch sensor electrodes that together form a capacitive touch sensor electrode array. Finally, the display stack may be covered by a cover glass (CG) layer 1320 formed over the touch layer 1316 using an additional adhesive 1318 (e.g., an OCA material). The cover glass 1320 may serve as an outer protective layer for the display 14.

[0075] Fig.14 FIG. 1 is a cross-sectional side view of an exemplary TFT layer 1304 of a display pixel 22 according to an embodiment. Fig.14 As shown, the TFT layer 1304 may include a buried conductive layer, such as a buried metal layer 1400, formed on a substrate 1302. The buried metal layer 1400 and the substrate 302 may optionally be covered with one or more buffer layers 1401 (e.g., an inorganic buffer layer, such as a silicon oxide layer, a silicon nitride layer, etc.).

[0076] A polysilicon layer (e.g., a low temperature polysilicon or "LTPS" layer) may be formed onto the inorganic buffer layer 1401 and then patterned and etched to form an LTPS region 1452. Opposite ends of the LTPS region 1452 may optionally be doped (e.g., n-doped or p-doped) to form source-drain regions of a silicon transistor (e.g., an LTPS transistor) within a display pixel. In general, a display pixel may include any suitable number of silicon transistors, if any.

[0077] A gate insulating layer 1404 may be formed on the buffer layer 1401 and over the silicon region 1452. A first metal layer (e.g., a first gate metal layer "GE1") may be formed over the gate insulating layer 1404. The GE1 metal layer may be patterned and etched to form a gate conductor for a silicon transistor. If desired, the first metal layer may also be patterned and etched to form terminals of one or more capacitors within a display pixel.

[0078] A first interlayer dielectric (ILD1) layer 1406 may be formed over the first gate metal layer GE1 and the silicon transistor. The dielectric layer 1406 may be formed, for example, of silicon nitride, silicon oxide, and other suitable insulating materials. A second metal layer (e.g., a second gate metal layer "GE2") may be formed on the ILD1 layer 1406. The second metal layer may optionally be patterned and etched to form another terminal of one or more capacitors within the display pixel.

[0079] A second interlayer dielectric (ILD2) layer 1408 may be formed over the second gate metal layer GE2. The dielectric layer 1408 may be formed of silicon nitride, silicon oxide, and other suitable insulating materials. One or more buffer layers such as a buffer layer 1410 (e.g., an inorganic buffer layer such as a silicon oxide layer, a silicon nitride layer, etc.) may be formed over the dielectric layer 1408.

[0080] A semiconductor oxide layer (e.g., an indium gallium zinc oxide or "IGZO" layer) may be formed over buffer layer 1410, which is sometimes referred to as an oxide buffer layer. The semiconductor oxide layer may be patterned and etched to form semiconductor oxide regions 1462. Opposite ends of semiconductor oxide regions 1462 may optionally be doped (e.g., n-doped or p-doped) to form source-drain regions of semiconductor oxide transistors within display pixels. In general, display pixel 22 may include any suitable number of semiconductor oxide transistors, if any.

[0081] Insulating layers such as gate insulating layer 1411 may be formed on IGZO region 1462. An oxide (third) gate metal layer "OGE" may be formed on gate insulating layer 1411 to serve as a gate conductor for a semiconductor oxide transistor. Another interlayer dielectric (OILD) layer 1412 may be formed on buffer layer 1410 and above the semiconductor oxide transistor. Pixel 22 need not include any semiconductor oxide transistors. In an arrangement where pixel 22 does not include any semiconductor oxide transistors, one or more of the layers, such as oxide buffer layer 1410, semiconductor oxide region 1462, gate liner 1411, OGE layer and / or oxide ILD layer 2512, may not be formed when manufacturing pixel 22. Layer GE2 and dielectric layer 1408 are also optional if a capacitor structure is not required to be formed.

[0082] A first interconnect layer above the silicon transistors and above the semiconductor oxide transistors may be formed on dielectric layer 1412. The conductive wiring structures formed in the first interconnect layer may couple down to the source-drain regions of each underlying transistor in pixel 22, and thus may sometimes be referred to as a first source-drain metal layer "SD1".

[0083] A first planarization (PLN1) layer such as layer 1414 may be formed over the SD1 metal wiring layer. A second interconnect layer may also be formed over the first planarization layer 1414. The conductive wiring structures formed in the second interconnect layer may couple downwardly to the SD1 conductors, and thus may sometimes be referred to as a second source-drain metal layer "SD2".

[0084] A second planarization (PLN2) layer such as layer 1416 may be formed on planarization layer 1414 and over the SD2 routing metal line. Planarization layers 1414 and 1416 may be formed of an organic dielectric material such as a polymer. In contrast, layers below the organic planarization layer such as layers 1404, 1406, 1408, 1410, and 1412 are typically formed of an inorganic dielectric material such as silicon nitride, silicon oxide, and the like.

[0085] An anode 1418 (e.g., an anode terminal for an organic light emitting diode within pixel 22) may be formed over second planarization layer 1416. Additional structures may be formed over anode 1418. For example, pixel definition layers, light emitting diode emissive materials, cathodes, and other pixel structures may also be included in the stacked structure of display pixel 22. However, for the sake of brevity, these additional structures are omitted.

[0086] As above combined Fig. 12B and 12C As described above, row and column lines may optionally be routed within the active area using an "upper" conductive layer (i.e., a metal layer formed above the silicon transistors and semiconductor oxide transistors). Fig. 12BThe data lines D shown as being routed in the active area may be formed using the anode layer 1418. As another example, the row / column lines routed in the active area may be formed using the SD1 or SD2 metal layer. As another example, the touch sensor layer 1316 (see Fig.13 ) form one or more of the row / column lines wired in the active area. These upper metal layers can be formed using aluminum, copper, silver, gold or other suitable materials with high conductivity.

[0087] As above combined Fig. 12B and 12C As described above, the row and column lines may optionally be routed within the active area using a "buried" conductive layer (i.e., one or more metal layers formed below the pixel silicon transistors). Fig. 12C The gate lines G in the active area can be arranged as shown. Fig.14 As shown, the buried metal layer 1400 is formed directly on the substrate 1302. As another example, the row / column lines routed in the active area can be formed using a buried metal layer sandwiched between two inorganic buffer layers (see, for example, Fig.15 , wherein the buried metal layer 1400 is formed between the buffer layers 1401-1 and 1401-2). As another example, the row / column lines routed in the active area may be formed using a buried metal layer embedded or buried in the substrate (see, e.g. Fig.16 , wherein a buried metal layer 1400 is formed on the inorganic buffer layer 1401 and buried between the first substrate layer 1302 - 1 and the second substrate layer 1302 - 2 ).

[0088] According to one embodiment, a display circuit is provided, which includes a first row of display pixels formed in an active area, a second row of display pixels formed in the active area, an invalid area within the active area, and a display driver circuit, wherein the display driver circuit is configured to output a control signal to a first row control line coupled to the first row of display pixels, and to output the control signal to a second row control line coupled to the second row of display pixels, the first row control line and the second row control line being merged into a segment that is wired through the invalid area.

[0089] According to another embodiment, the inactive area comprises a hole.

[0090] According to another embodiment, the inactive region comprises a through hole.

[0091] According to another embodiment, the inactive area comprises an optical window.

[0092] According to another embodiment, the merging segments are routed around the boundaries of the hole.

[0093] According to another embodiment, the merged segments are routed directly across the vias.

[0094] According to another embodiment, the display driver circuit is further configured to output the control signal to the first row control line and the second row control line simultaneously.

[0095] According to another embodiment, a display circuit includes a dummy circuit coupled to the merging segment and configured to increase a parasitic load of the first row control line and the second row control line.

[0096] According to another embodiment, the merging section is coupled between a first node and a second node, the first node is connected to the first and second row control lines, and the merging section is split into at least first and second additional row control lines at the second node.

[0097] According to another embodiment, the display circuit includes an additional display driver circuit configured to output an additional control signal to a third row control line coupled to the first row of display pixels and to output an additional control signal to a fourth control line coupled to the second row of display pixels, the third row control line and the fourth row control line being merged into an additional segment that is wired through the invalid region.

[0098] According to another embodiment, the inactive region is physically interposed between the display driver circuit and the additional display driver circuit.

[0099] According to another embodiment, the display circuit includes a third row of display pixels formed in the active area, the display driver circuit is further configured to output the control signal to a third row control line coupled to the third row of display pixels, and the binning segment is also connected to the third row control line.

[0100] According to another embodiment, the inactive region has a tapered shape optimized to increase the size of the active area around the inactive region.

[0101] According to another embodiment, the inactive region is asymmetric.

[0102] According to one embodiment, a display is provided, which includes display pixels formed in an active area; an invalid area at least partially surrounded by the active area; a first wiring segment coupled to a first group of display pixels formed in a first portion of the active area located on a first side of the invalid area; a second wiring segment coupled to a second group of display pixels formed in the first portion of the active area located on the first side of the invalid area, the first wiring segment and the second wiring segment being connected at a node via a short circuit segment; and a merging segment connected to the node and wired via the invalid area.

[0103] According to another embodiment, the display includes a third wiring segment, which is coupled to a third group of display pixels formed in a second portion of the active area located on the side of the inactive area; and a fourth wiring segment, which is coupled to a fourth group of display pixels formed in the second portion of the active area located on the second side of the inactive area, and the third wiring segment and the fourth wiring segment are connected to the merging segment at a fan-out node.

[0104] According to another embodiment, the first wiring segment and the third wiring segment are coupled to the same row of display pixels.

[0105] According to another embodiment, the first wiring segment is parallel to the second wiring segment.

[0106] According to another embodiment, the first group of display pixels and the second group of display pixels correspond to adjacent rows of display pixels in the active area.

[0107] According to another embodiment, the first group of display pixels and the second group of display pixels correspond to non-adjacent rows of display pixels in the active area.

[0108] According to another embodiment, the inactive region has a tapered shape optimized to increase the active area.

[0109] According to one embodiment, a display is provided, comprising a pixel array formed within an active area; an inactive area at least partially surrounded by the active area, the inactive area having a border area that does not overlap with the active area; a first wiring line extending across the display in a first direction and into the border area of ​​the inactive area; and a second wiring line extending across the display in a second direction and not extending into the border area of ​​the inactive area.

[0110] According to another embodiment, the second direction is perpendicular to the first direction.

[0111] According to another embodiment, the first wiring line includes a gate line, and the second wiring line includes a data line.

[0112] According to another embodiment, the first wiring line includes a data line, and the second wiring line includes a gate line.

[0113] According to another embodiment, the second wiring line is formed using the anode layer.

[0114] According to another embodiment, the second wiring line is formed using a source-drain metal wiring layer.

[0115] According to another embodiment, the second wiring line is formed using the touch sensor layer.

[0116] According to another embodiment, the second wiring line is formed using a buried metal layer formed over the substrate layer and under the low temperature polysilicon layer.

[0117] The foregoing is merely exemplary and various modifications may be made to the embodiments described. The foregoing embodiments may be implemented independently or in any combination.

Claims

1. A display circuit, comprising: forming a first row of display pixels, a second row of display pixels, and a third row of display pixels within the active area; an inactive area within the active area; a first wiring segment coupled to the first row of display pixels; a second wiring segment coupled to the second row of display pixels; a wiring circuit coupled to the third row of display pixels; as well as A display driver circuit is coupled to the first wiring segment and the second wiring segment and to the wiring line, wherein the first wiring segment and the second wiring segment are merged into a merged segment, the merged segment is wired from a first side of the inactive area, and wherein the wiring line extends along a second side of the inactive area opposite to the first side. 2 . The display circuit of claim 1 , wherein the routing line comprises unmerged routing segments routed from the second side of the inactive region. 3 . The display circuit of claim 1 , wherein the first and second wiring segments, the merged segments, and the wiring line form a gate line. 4 . The display circuit of claim 1 , wherein the first and second wiring segments, the merged segments, and the wiring line form a data line. 5 . The display circuit of claim 1 , wherein the first wiring segment and the second wiring segment and the merged segment form a power supply line. The display circuit of claim 1 , wherein the inactive region comprises a hole. The display circuit of claim 6 , wherein the hole comprises a through-hole.

8. The display circuit of claim 6, wherein the aperture comprises an optical window.

9. The display circuit of claim 6, wherein the merging segments are routed around the hole, wherein the hole has a border region adjacent to the active area, and wherein the merging segments overlap the border region.

10. The display circuit of claim 6, wherein the merging segment is routed directly across the hole to overlap the hole.

11. A display comprising: A pixel array is formed in the active area; an inactive region at least partially surrounded by the active region, wherein the inactive region has an aperture and a boundary region between the aperture and the active region; a first routing line extending across the display in a first direction; as well as A second wiring line extends across the display in a second direction and has a portion that is routed around the hole to overlap the boundary region between the hole and the active area.

12. The display of claim 11, wherein the second wiring line comprises a gate line, and wherein the first wiring line comprises a data line. 13 . The display according to claim 12 , wherein the first wiring line has a portion which is routed around the hole to overlap the boundary area between the hole and the active area.

14. The display according to claim 12, wherein the first wiring line has a portion that is routed around the hole, and wherein the portion of the first wiring line does not extend into the boundary area. 15 . The display of claim 14 , wherein the portion of the first wiring line comprises a buried conductive layer between a substrate on which the pixel array is formed and a buffer layer on the substrate.

16. A display comprising: A pixel array is formed in the active area; an inactive region at least partially surrounded by the active region; as well as A touch sensor circuit is configured to detect a touch input over the active area, the touch sensor circuit comprising: Touch sensing circuit; a first wiring line and a second wiring line in parallel coupled to the touch sensing circuit, wherein the first wiring line is shorted to the second wiring line in parallel at a node; and Routing line segments are merged, the merged routing line segments connected to the node and routed around the invalid region.

17. The display of claim 16, wherein the merged routing line segment is divided into at least a third routing line and a fourth routing line in parallel at a fan-out node, and wherein the node and the fan-out node are on opposite sides of the inactive region.

18. A display according to claim 17, wherein the touch sensing circuit is arranged along an edge of the display, and wherein the parallel first wiring line and the second wiring line, the merged wiring line segment, and the parallel third wiring line and the fourth wiring line extend from the edge of the display toward an opposite edge.

19. The display of claim 16, wherein the parallel first and second wiring lines are sense lines.

20. The display of claim 17, wherein the parallel first and second wiring lines are control lines.

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