Chip packaging structure and preparation method thereof
By forming blind holes on the substrate and installing conductive materials, the preparation of chip packaging structure is achieved by using hot melt connection method, which solves the problems of inability to reduce the spacing between bubbles and pads and bias in the packaging process of BGA technology, and improves stability, heat dissipation and sealing, and broadens the application range.
Patent Information
- Application Number
- CN202311324043.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-12
- Publication Date
- 2025-04-15
Smart Images
Figure CN119833401A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of packaging technology, and in particular to a chip packaging structure and a preparation method thereof. Background Art
[0002] Electronics manufacturers are increasingly using BGA (Ball Grid Array) technology to connect integrated circuits (ICs; also known as microcircuits, microchips, chips) or other components to printed circuit boards (PCBs). The connection between BGA and PCB is usually through vias, which is prone to bubbles during surface mounting (SMT), and the spacing between pads cannot be reduced, which takes up space. BGA can also be mounted directly on the PCB, but the overall height is relatively high, which is not conducive to the miniaturization of the package structure, and generally requires the addition of underfill for reinforcement. When the pad spacing on the PCB is small, the BGA is prone to misalignment. Summary of the invention
[0003] In view of this, the present application proposes a chip packaging structure and a manufacturing method thereof to solve at least one of the above problems.
[0004] An embodiment of the present application provides a method for preparing a chip packaging structure, comprising the following steps:
[0005] A first blind hole and a second blind hole are formed in communication on a substrate, wherein the substrate comprises a base material layer and a circuit layer formed on the base material layer, and the circuit layer comprises a pad; along a thickness direction of the substrate, the first blind hole and the second blind hole penetrate the base material layer together, and a bottom wall of the second blind hole is the pad;
[0006] Disposing a conductive material in the first blind hole and the second blind hole to form a first conductive portion;
[0007] Mounting a chip on the substrate, wherein the chip comprises a second conductive portion, the second conductive portion is arranged corresponding to the first conductive portion, and the melting point of the second conductive portion is higher than the melting point of the first conductive portion;
[0008] The first conductive part is heated to melt, and then cooled to solidify, so that the first conductive part is connected to the second conductive part to obtain the chip packaging structure.
[0009] In one embodiment, the preparation method further includes: forming a third blind hole on the substrate, wherein the third blind hole penetrates the circuit layer and partially penetrates the base material layer along the thickness direction of the substrate, and the third blind hole is staggered with the second blind hole; and the cooling medium is arranged in the third blind hole.
[0010] In one embodiment, the preparation method further comprises: providing a dielectric layer between the substrate and the chip, wherein the dielectric layer comprises a cooling medium or an adhesive.
[0011] In one embodiment, the shape of the first blind hole is hemispherical, and before the step of "mounting the chip on the substrate", the preparation method further includes: setting the shape of the second conductive portion to be hemispherical.
[0012] An embodiment of the present application provides a chip packaging structure, which includes a substrate and a chip. The substrate includes a base material layer and a circuit layer formed on the base material layer, and the circuit layer includes a pad. The substrate is provided with a first blind hole and a second blind hole that are connected, and along the thickness direction of the substrate, the first blind hole and the second blind hole penetrate the base material layer together, and the bottom wall of the second blind hole is the pad. Conductive material is provided in the first blind hole and the second blind hole to form a first conductive part. The chip includes a second conductive part, the second conductive part is connected to the first conductive part, and the melting point of the second conductive part is higher than the melting point of the first conductive part.
[0013] In one embodiment, a third blind hole is further provided on the substrate. Along the thickness direction of the substrate, the third blind hole penetrates the circuit layer and partially penetrates the base material layer. The third blind hole is staggered with the second blind hole, and a cooling medium is provided in the third blind hole, and the thermal conductivity of the cooling medium is 0.068W / (m·K) to 0.069W / (m·K).
[0014] In one embodiment, the chip packaging structure further includes a dielectric layer. The dielectric layer is disposed between the chip and the substrate, and the dielectric layer includes a cooling medium or an adhesive.
[0015] In one embodiment, the first blind hole is hemispherical in shape, and the second heat conducting portion is hemispherical in shape.
[0016] In one embodiment, the melting point of the first conductive part is 180°C to 200°C, and the melting point of the second conductive part is greater than 250°C.
[0017] In one embodiment, the conductive material of the first conductive part includes tin, tin-bismuth alloy, or tin-indium alloy, and the second conductive part includes tin-silver-copper alloy, tin-bismuth alloy, or tin-indium alloy.
[0018] The present application utilizes the first conductive part with a low melting point to be hot-melted and connected with the second conductive part with a high melting point, thereby improving the bonding force between the first conductive part and the second conductive part, thereby improving the stability of the connection between the substrate and the chip. In addition, the method of the present application can be applied to the packaging of chips that are not resistant to high temperatures, protecting the chip from being broken down by heat, and broadening the scope of application. In addition, a cooling medium is also provided between the substrate and the chip of the present application, and the cooling medium can not only improve the heat dissipation effect, but also form a sealing structure, thereby improving the sealing of the chip packaging structure. The present application does not need to make a separate circuit, does not need to set a bottom filling glue (underfill), simplifies the process, and can also make a chip packaging structure with any fine pitch (Fine pitch). Since the second conductive part (ball grid array) on the chip has a high melting point, when the first conductive part is hot-melted, the solder balls of the ball grid array will not be hot-melted, so the coplanarity of the solder balls in the ball grid array is better. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 A cross-sectional view of a substrate provided in accordance with one embodiment of the present application.
[0020] Figure 2 For Figure 1 A cross-sectional view of a substrate after a blind hole is formed is shown.
[0021] Figure 3 For Figure 2 The cross-sectional view is shown after a conductive material is arranged in the blind hole to form a first conductive portion.
[0022] Figure 4 A cross-sectional view of a chip provided in accordance with one embodiment of the present application.
[0023] Figure 5 For the general Figure 4 The chip shown is Figure 3 Cross-sectional view of the substrate connection shown.
[0024] Figure 6 for Figure 5 Schematic diagram of the connection between the first conductive part and the second conductive part in the structure shown.
[0025] Figure 7 For Figure 5 A cross-sectional view of a chip packaging structure obtained after a cooling medium is disposed in the structure shown in one embodiment.
[0026] Main component symbols
[0027] Chip packaging structure 100
[0028] Substrate 10
[0029] Chip 20
[0030] Dielectric layer 30
[0031] Cooling medium 40
[0032] Base material layer 11
[0033] Circuit layer 12
[0034] Pad 13
[0035] Conductive material 14
[0036] The first conductive portion 15
[0037] The first blind hole 111
[0038] The second blind hole 112
[0039] The third blind hole 113
[0040] Main body 21
[0041] The second conductive portion 22
[0042] Solder ball 23
[0043] The following specific implementation manner will further illustrate the embodiments of the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION
[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the technical field of the present application. The terms used herein are only for the purpose of describing specific implementation methods and are not intended to limit the present application embodiments.
[0045] Here, the embodiments of the present application are described with reference to the cross-sectional views, which are schematic diagrams of the idealized embodiments (and intermediate configurations) of the present application. Thus, it is foreseeable that the shapes of the diagrams are different due to manufacturing processes and / or tolerances. Therefore, the embodiments of the present application should not be interpreted as being limited to the specific shapes of the regions illustrated here, but should include deviations in shapes such as those produced due to manufacturing. The regions shown in the figures are themselves only schematic, and their shapes are not intended to illustrate the actual shapes of the devices, and are not intended to limit the scope of the present application.
[0046] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0047] See also Figures 1 to 6 In a first aspect, the present application provides a method for preparing a chip package structure 100, which includes steps S10 to S40. It is understandable that the numbering of the steps is intended to clearly describe the specific preparation method, and is not intended to limit the order of the steps.
[0048] Step S10, see Figure 1 and Figure 2 The first blind hole 111 and the second blind hole 112 may be formed on the substrate 10 by, but not limited to, laser drilling, mechanical drilling, or the like.
[0049] like Figure 1 As shown, the substrate 10 includes a base material layer 11 and a circuit layer 12 formed on the base material layer 11, and the circuit layer 12 includes a pad 13 (the pad is a metal contact point on the substrate 10 for soldering components, which can also be called a soldering pad). The substrate 10 is a circuit board formed with a conductive circuit layer. The substrate 10 can be a single-layer board or a multi-layer board, which is not limited in this application. The substrate 10 can be, but is not limited to, a hard board, a flexible board (FPC), a hard-soft board, etc., which is not limited in this application.
[0050] The material of the substrate layer 11 may be, but not limited to, polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polydimethylsiloxane, liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), etc. In this embodiment, the material of the substrate layer 11 is PI. The material of the circuit layer 12 may be, but not limited to, copper, gold, silver, etc. In this embodiment, the material of the circuit layer 12 is copper.
[0051] like Figure 2 As shown, the first blind hole 111 can be formed by the surface of the substrate layer 11 facing away from the circuit layer 12 and being recessed in the direction toward the circuit layer 12, and the bottom wall and the side wall of the first blind hole 111 are both the substrate layer 11. A plurality of first blind holes 111 can be provided. The second blind hole 112 can be formed by the part of the bottom wall of the first blind hole 111 continuing to be recessed in the direction toward the circuit layer 12 until the surface of the circuit layer 12 close to the substrate layer 11 is exposed. The first blind hole 111 and the second blind hole 112 are provided corresponding to the pad 13. The side wall of the second blind hole 112 is the substrate layer 11, and the bottom wall is the pad 13. A plurality of second blind holes 112 can also be provided, and the number of the second blind holes 112 corresponds to the number of the first blind holes 111. Along the thickness direction of the substrate 10 (i.e. Figure 2 The first blind hole 111 and the second blind hole 112 penetrate the substrate layer 11 together.
[0052] In some embodiments, Figure 2 As shown, the first blind hole 111 is hemispherical (semicircular in cross section), and the second blind hole 112 is a circular hole (rectangular in cross section). The diameter of the second blind hole 112 may be smaller than that of the first blind hole 111 .
[0053] In some embodiments, Figure 2As shown, a third blind hole 113 may also be formed on the substrate 10, and the third blind hole 113 may be formed by the surface of the circuit layer 12 facing away from the substrate layer 11 and being recessed toward the substrate layer 11. Along the thickness direction of the substrate 10, the third blind hole 113 penetrates the circuit layer 12 and partially penetrates the substrate layer 11, that is, the bottom wall of the third blind hole 113 is the substrate layer 11, and the side walls are the circuit layer 12 and the substrate layer 11. There may be a plurality of third blind holes 113, and the third blind holes 113 may be staggered with the second blind holes 112.
[0054] Step S20, see Figure 3 , a conductive material 14 is injected into the first blind hole 111 and the second blind hole 112 to form a first conductive part 15. The conductive material may be, but is not limited to, a tin (Sn) bismuth (Bi) alloy, a tin indium (Im) alloy, and the like, and the melting point of the alloy can be changed by adjusting the content of each component in the alloy. In the present embodiment, the conductive material of the first conductive part 15 is a tin-bismuth alloy. The melting point of the first conductive part 15 is approximately 180°C to 200°C, which is lower than the temperature of the subsequent reflow (reflow, heating to melt the first conductive part 15 and thereby connect it to the second conductive part 22) process. Therefore, the first conductive part 15 can be melted, and the liquid metal and the second conductive part 22 (see Figure 5 )Atomic diffusion occurs and eventually interconnection is achieved.
[0055] Step S30, see Figure 4 and Figure 5 , the chip 20 is mounted on the substrate 10 .
[0056] like Figure 4 As shown, the chip 20 includes a main body 21 and a second conductive portion 22 formed on the main body 21. In this embodiment, the second conductive portion 22 is a ball grid array (BGA), and the BGA is composed of a plurality of solder balls 23. In some embodiments, the solder balls 23 can be ground into a hemispherical shape. In this way, the hemispherical second conductive portion 22 can better fit (contact) with the conductive material 14 (the upper part of the first conductive portion 15) in the hemispherical first blind hole 111, which is beneficial to the subsequent connection between the first conductive portion 15 and the second conductive portion 22.
[0057] like Figure 5 As shown, the chip 20 is stacked with the substrate 10 so that the second conductive part 22 is arranged corresponding to the first conductive part 15. The second conductive part 22 contacts the first conductive part 15, and the diameter of the second conductive part 22 can be the same as the diameter of the first conductive part 15 located in the first blind hole 111.
[0058] The melting point of the second conductive part 22 is higher than the melting point of the first conductive part 15. During reflow soldering, the first conductive part 15 melts, while the second conductive part 22 does not melt. The material of the second conductive part 22 may be, but is not limited to, a tin-silver-copper (SnAgCu) alloy, a tin-bismuth alloy, or a tin-indium alloy. The melting point of the alloy can be changed by adjusting the content of each component in the alloy. In this embodiment, the material of the second conductive part 22 is a tin-silver-copper alloy. The melting point of the second conductive part 22 is greater than 250°C, which is higher than the temperature of the subsequent reflow soldering process (the reflow soldering temperature is usually less than 250°C). Therefore, the first conductive part 15 melts while the second conductive part 22 does not melt.
[0059] In step S40, after stacking, heating is provided to melt the first conductive part 15, and atomic diffusion occurs between the melted first conductive part 15 and the second conductive part 22. After cooling and solidification, the first conductive part 15 is connected (mechanically and electrically) to the second conductive part 22 to achieve interconnection, thereby obtaining the chip packaging structure 100.
[0060] like Figure 6 As shown, when the first conductive part 15 and the second conductive part 22 are connected and combined by heating, there is a clear boundary between the first conductive part 15 and the second conductive part 22. The first conductive part 15 and the second conductive part 22 are both relatively regular hemispherical (semicircular in cross section). Because only the first conductive part 15 on the lower side will be hot-melted and solidified, the second conductive part 22 on the upper side will be relatively smooth, and the first conductive part 15 on the lower side will be relatively rough. According to elemental analysis, the atoms of the first conductive part 15 and the second conductive part 22 will diffuse with each other to form a tin-bismuth-silver (SnBiAg) alloy, indicating that a close connection is formed between the first conductive part 15 and the second conductive part 22, and the bonding force is strong.
[0061] See also Figure 7 In some embodiments, the preparation method may further include step S50: disposing a dielectric layer 30 between the substrate 10 and the chip 20 .
[0062] In some embodiments, a cooling medium may be provided between the main body 21 and the substrate layer 11, and the cooling medium fills the gaps between the solder balls 23 in the second conductive portion 22. The cooling medium may be, but is not limited to, fluorinated liquid, hydrocarbons, silicone oil, synthetic oil, natural mineral oil, etc., and its thermal conductivity may be 0.068W / (m·K) to 0.069W / (m·K), and its surface tension may be 13.6mN / m. The cooling medium can dissipate heat from the chip 20 and the substrate 10, and can also improve the sealing of the chip packaging structure 100. In some embodiments, the cooling medium between the chip 20 and the substrate 10 may also be replaced by an adhesive (e.g., underfill) for bonding, so as to make the connection between the chip 20 and the substrate 10 more stable.
[0063] In some embodiments, Figure 7As shown, a cooling medium 40 may be provided in the third blind hole 113 to further improve the heat dissipation efficiency of the substrate 10. The cooling medium 40 may be, but is not limited to, fluorinated liquid, hydrocarbon, silicone oil, synthetic oil, natural mineral oil, etc., and its thermal conductivity may be 0.068W / (m·K) to 0.069W / (m·K), and its surface tension may be 13.6mN / m. The cooling medium 40 in the third blind hole 113 may be the same as or different from the cooling medium between the chip 20 and the substrate 10, and the present application does not limit this.
[0064] See also Figure 7 In a second aspect, the present application provides a chip packaging structure 100 prepared by the above-mentioned preparation method, which includes a substrate 10 and a chip 20.
[0065] The substrate 10 is a circuit board formed with a conductive circuit layer. The substrate 10 includes a base material layer 11 and a circuit layer 12 formed on the base material layer 11, and the circuit layer 12 includes a pad 13. The substrate 10 can be a single-layer board or a multi-layer board, which is not limited in this application. The substrate 10 can be, but is not limited to, a hard board, a flexible board (FPC), a hard-soft board, etc., which is not limited in this application.
[0066] The substrate 10 is provided with a first blind hole 111 and a second blind hole 112 that are connected. Conductive material 14 is provided in the first blind hole 111 and the second blind hole 112 to form a first conductive portion 15. The first blind hole 111 can be formed by the surface of the substrate layer 11 facing away from the circuit layer 12 being recessed in the direction toward the circuit layer 12, and the bottom wall and side wall of the first blind hole 111 are both the substrate layer 11. A plurality of first blind holes 111 can be provided. The second blind hole 112 can be formed by the part of the bottom wall of the first blind hole 111 that continues to be recessed in the direction toward the circuit layer 12 until the surface of the circuit layer 12 close to the substrate layer 11 is exposed. The first blind hole 111 and the second blind hole 112 are provided corresponding to the pad 13. The side wall of the second blind hole 112 is the substrate layer 11, and the bottom wall is the pad 13. A plurality of second blind holes 112 can also be provided, and the number of the second blind holes 112 corresponds to the number of the first blind holes 111. Along the thickness direction of the substrate 10 (i.e. Figure 7 The first blind hole 111 and the second blind hole 112 penetrate the substrate layer 11 together.
[0067] The chip 20 includes a main body 21 and a second conductive part 22 formed on the main body 21. The second conductive part 22 may be a ball grid array (BGA), which may be composed of a plurality of solder balls 23. The second conductive part 22 corresponds to the first conductive part 15 one by one and is connected to each other (mechanically and electrically), and the melting point of the second conductive part 22 is higher than the melting point of the first conductive part 15. In addition, the melting point of the first conductive part 15 is lower than the temperature of reflow soldering (a process of heating the first conductive part 15 to melt and connect with the second conductive part 22), and the melting point of the second conductive part 22 is higher than the temperature of reflow soldering.
[0068] In some embodiments, Figure 7 As shown, the chip packaging structure 100 also includes a dielectric layer 30, which is disposed between the chip 20 and the substrate 10. Specifically, a cooling medium can be disposed between the main body 21 of the chip 20 and the base material layer 11 of the substrate 10, and the cooling medium fills the gaps between the solder balls 23 in the second conductive portion 22. The cooling medium may be, but is not limited to, fluorinated liquid, hydrocarbons, silicone oil, synthetic oil, natural mineral oil, etc., and its thermal conductivity is 0.068W / (m·K) to 0.069W / (m·K), and its surface tension is 13.6mN / m. In some embodiments, the cooling medium between the chip 20 and the substrate 10 can also be replaced by an adhesive for bonding, thereby improving the stability of the connection between the chip 20 and the substrate 10.
[0069] In some embodiments, Figure 7 As shown, the substrate 10 is further provided with a third blind hole 113, which can be formed by the surface of the circuit layer 12 facing away from the substrate layer 11 and being recessed toward the substrate layer 11. Along the thickness direction of the substrate 10, the third blind hole 113 penetrates the circuit layer 12 and partially penetrates the substrate layer 11, that is, the bottom wall of the third blind hole 113 is the substrate layer 11, and the side walls are the circuit layer 12 and the substrate layer 11. The number of the third blind holes 113 can be multiple, and the third blind holes 113 can be staggered with the second blind holes 112. A cooling medium 40 is provided in the third blind hole 113 to further improve the heat dissipation efficiency of the substrate 10.
[0070] In some embodiments, the thermal conductivity of the cooling medium 40 is 0.068W / (m·K) to 0.069W / (m·K), and the surface tension is 13.6mN / m. The cooling medium 40 may be, but is not limited to, fluorinated liquid, hydrocarbon, silicone oil, synthetic oil, natural mineral oil, etc.
[0071] In some embodiments, Figure 7 As shown, the first blind hole 111 is hemispherical (semicircular in cross section), the second blind hole 112 is a circular hole (rectangular in cross section), and the third blind hole 113 is a circular hole (rectangular in cross section). The diameter of the second blind hole 112 may be smaller than the diameter of the first blind hole 111. The second conductive portion 22 is hemispherical (semicircular in cross section).
[0072] In some embodiments, the melting point of the first conductive part 15 is 180° C. to 200° C., and the melting point of the second conductive part 22 is greater than 250° C.
[0073] In some embodiments, the conductive material of the first conductive part 15 may be, but not limited to, tin-bismuth alloy, tin-indium alloy, etc. The material of the second conductive part 22 may be, but not limited to, tin-silver-copper alloy, tin-bismuth alloy, tin-indium alloy, etc.
[0074] The present application utilizes the first conductive part 15 with a low melting point to be connected with the second conductive part 22 with a high melting point by hot melting, thereby improving the bonding force between the first conductive part 15 and the second conductive part 22, thereby improving the stability of the connection between the substrate 10 and the chip 20. In addition, the method of the present application can be applied to the packaging of the chip 20 that is not resistant to high temperatures, protecting the chip 20 from being broken down by heat, and broadening the scope of application. In addition, a cooling medium is also provided between the substrate 10 and the chip 20 of the present application, and the cooling medium can not only improve the heat dissipation effect, but also form a sealing structure, thereby improving the sealing of the chip packaging structure 100. The present application does not need to make a separate circuit, does not need to set a bottom filling glue (underfill), simplifies the process, and can also make a chip packaging structure 100 with any fine pitch (Fine pitch). Since the second conductive part 22 (ball grid array) on the chip 20 has a high melting point, when the first conductive part 15 is hot melted, the solder balls 23 of the ball grid array will not be hot melted, so the coplanarity of the solder balls 23 in the ball grid array is better.
[0075] The above descriptions are some specific implementations of the present application, but they are not limited to these implementations in actual application. For ordinary technicians in this field, other variations and changes made according to the technical concept of the present application should all fall within the protection scope of the present application.
Claims
1. A method for preparing a chip packaging structure, characterized in that: The steps include: A first blind hole and a second blind hole are formed in communication on a substrate, wherein the substrate comprises a base material layer and a circuit layer formed on the base material layer, and the circuit layer comprises a pad; along a thickness direction of the substrate, the first blind hole and the second blind hole penetrate the base material layer together, and a bottom wall of the second blind hole is the pad; Disposing a conductive material in the first blind hole and the second blind hole to form a first conductive portion; Mounting a chip on the substrate, wherein the chip comprises a second conductive portion, the second conductive portion is arranged corresponding to the first conductive portion, and the melting point of the second conductive portion is higher than the melting point of the first conductive portion; The first conductive part is heated to melt, and then cooled to solidify, so that the first conductive part is connected to the second conductive part to obtain the chip packaging structure.
2. The preparation method according to claim 1, characterized in that The preparation method also includes: forming a third blind hole on the substrate, wherein the third blind hole penetrates the circuit layer and partially penetrates the base material layer along the thickness direction of the substrate, and the third blind hole is staggered with the second blind hole; and a cooling medium is arranged in the third blind hole.
3. The preparation method according to claim 2, characterized in that: The preparation method further comprises: providing a dielectric layer between the substrate and the chip, wherein the dielectric layer comprises a cooling medium or an adhesive.
4. The preparation method according to claim 1, characterized in that: The shape of the first blind hole is hemispherical. Before the step of "mounting the chip on the substrate", the preparation method further includes: setting the shape of the second conductive part to be hemispherical.
5. A chip packaging structure, characterized in that: include: A substrate, the substrate comprising a base material layer and a circuit layer formed on the base material layer, the circuit layer comprising a pad; a first blind hole and a second blind hole are connected on the substrate, the first blind hole and the second blind hole penetrate the base material layer together along the thickness direction of the substrate, and the bottom wall of the second blind hole is the pad; a conductive material is provided in the first blind hole and the second blind hole to form a first conductive portion; and The chip comprises a second conductive part, the second conductive part is connected to the first conductive part, and the melting point of the second conductive part is higher than the melting point of the first conductive part.
6. The chip packaging structure according to claim 5, characterized in that: A third blind hole is also provided on the substrate. Along the thickness direction of the substrate, the third blind hole penetrates the circuit layer and partially penetrates the base material layer. The third blind hole and the second blind hole are staggered. A cooling medium is provided in the third blind hole. The thermal conductivity of the cooling medium is 0.068W / (m·K) to 0.069W / (m·K).
7. The chip packaging structure according to claim 5, characterized in that: The chip packaging structure further includes a dielectric layer, which is disposed between the chip and the substrate, and includes a cooling medium or an adhesive.
8. The chip packaging structure according to claim 5, characterized in that: The first blind hole is hemispherical in shape, and the second heat conducting portion is hemispherical in shape.
9. The chip packaging structure according to claim 5, characterized in that: The melting point of the first conductive part is 180°C to 200°C, and the melting point of the second conductive part is greater than 250°C.
10. The chip packaging structure according to claim 5, characterized in that: The conductive material of the first conductive part includes tin, tin-bismuth alloy, and tin-indium alloy, and the second conductive part includes tin-silver-copper alloy, tin-bismuth alloy, and tin-indium alloy.