Semiconductor package assembly and method of forming same

Abstract

The invention provides a semiconductor packaging assembly and a forming method thereof. The method includes: providing a package substrate including a first region on which at least one first type of electronic component is mounted and a second region on which at least one second type of electronic component is mounted; attaching a protective layer to the second region; forming a base cover on the first region and the second region to encapsulate the at least one first type electronic component and the protective layer; a part of the base mold cover formed on the second area is removed, a cavity is formed in the base mold cover, and the protective layer is exposed out of the cavity; the protection layer is removed from the packaging substrate; mounting a second type of electronic component on the second region; and filling the cavity with a filling material.

Description

Technical Field

[0001] The present application relates generally to semiconductor packaging technology, and more particularly, to semiconductor package assemblies and methods of forming the same. Background Art

[0002] The semiconductor industry has been facing complex integration challenges as consumers want their electronic products to be smaller, faster, and higher performing, and to pack more and more functions into a single device. In some semiconductor packages, a Package-in-Package (PiP) process is applied, which combines two or more integrated circuit (IC) packages together. PiP devices can use space more efficiently and reduce the length of signal paths between packages. In a typical PiP device, one or more pre-molded electronic packages are mounted on a package substrate together with other electronic components, and then an additional mold cap is formed on the package substrate using a molding process, which encapsulates the pre-molded electronic package and the electronic components to form the entire electronic package. However, since the entire electronic package has a relatively large thickness, there may be a potential risk of warping of the mold cap during subsequent heating processes (e.g., during reflow of solder bumps), which may have an adverse effect on device performance and subsequent device manufacturing processes.

[0003] Therefore, a method for forming a semiconductor package assembly having a smaller mold cover thickness is needed. Summary of the invention

[0004] An object of the present application is to provide a semiconductor package assembly having a smaller mold cover thickness.

[0005] According to one aspect of the present application, a method for making a semiconductor package assembly is provided. The method comprises: providing a package substrate, the package substrate comprising a first area and a second area, wherein at least one first type electronic component is mounted on the first area; attaching a protective layer to the second area; forming a base mold cover on the first area and the second area to seal the at least one first type electronic component and the protective layer; removing a portion of the base mold cover formed on the second area, forming a cavity in the base mold cover, the cavity exposing the protective layer; removing the protective layer from the package substrate; mounting a second type electronic component on the second area; and filling a filling material in the cavity.

[0006] According to another aspect of the present application, a semiconductor package assembly is provided. The semiconductor package assembly includes: a package substrate, the package substrate includes a first area and a second area; at least one first type electronic component, the at least one first type electronic component is mounted on the first area; a base mold cover, the base mold cover is formed on the package substrate to seal the at least one first type electronic component, wherein the base mold cover includes a cavity, the cavity exposes the second area of ​​the package substrate; a second type electronic component, the second type electronic component is mounted on the second area; and a filling material, the filling material is filled in the cavity.

[0007] It should be understood that both the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. In addition, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings referred to herein form part of this specification. The features shown in the drawings only illustrate some embodiments of the present application, rather than all embodiments of the present application, unless the specific implementation mode clearly indicates otherwise, and the reader of this specification should not make an inference to the contrary.

[0009] Figures 1A to 1I Various steps of a method for forming a semiconductor package assembly in a first embodiment of the present application are shown.

[0010] Figures 2A to 2E Part of the steps of a method for forming a semiconductor package assembly in a second embodiment of the present application is shown.

[0011] Figures 3A to 3F Part of the steps of a method for forming a semiconductor package assembly in a third embodiment of the present application is shown.

[0012] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0013] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which the present application can be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable a person skilled in the art to practice the present application. Other embodiments of the present application may be further utilized by a person skilled in the art, and logical, mechanical and other changes may be made without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0014] In this application, unless otherwise expressly stated, the use of the singular includes the plural. In this application, unless otherwise stated, the use of "or" means "and / or". In addition, the use of the term "including" and other forms is not limiting. In addition, unless otherwise specifically stated, terms such as "element" or "component" cover elements and components that include one unit and elements and components that include more than one subunit. In addition, the section headings used herein are for organizational purposes only and should not be interpreted as limiting the subject matter described.

[0015] As used herein, for ease of description, spatially relative terms such as "under," "below," "above," "above," "up," "upper," "lower," "left," "right," "vertical," "horizontal," "side," etc. may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features), as shown in the drawings. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" another element or "coupled to" another element, the element may be directly connected to or coupled to another element, or there may be intermediate elements.

[0016] As mentioned above, in a typical PiP device, one or more pre-molded electronic packages are mounted on a packaging substrate together with other electronic components. A molding process can be used to form an additional mold cap on the packaging substrate, which encapsulates the pre-molded electronic package and the electronic component to form the entire electronic package. During this process, since the entire electronic package needs to have a uniform thickness and the pre-molded electronic package is covered with a redundant mold cap, the total thickness of the entire electronic package is increased. In addition, due to the height difference that may exist between the pre-molded electronic package and the electronic component, the thickness of the mold cap material above the pre-molded electronic package and the electronic component may also be different. The thickness difference of the mold cap material may cause warping of the mold cap during subsequent heating (for example, during the reflow of the solder bump), which is caused by different thermal stresses at different positions of the entire package. The warping of the mold cap may have an adverse effect on device performance and subsequent device manufacturing processes.

[0017] To address this problem, a novel method for forming a semiconductor assembly is provided in which pre-molded electronic packages, particularly those having a greater height, are installed after other electronic components are encapsulated by a mold cover. To achieve delayed installation of the pre-molded electronic package, a removable protective layer may be used to form one or more cavities in the mold cover. The method may be used to form a semiconductor package assembly that requires a smaller package thickness and that produces less warpage when the semiconductor package assembly is exposed to a heating process such as reflow.

[0018] Figures 1A to 1I The various steps of the method for forming a semiconductor package assembly in the first embodiment of the present application are shown. Figures 1A to 1I , describing the method in more detail.

[0019] like Figure 1A As shown, the packaging substrate strip 100 has interconnect lines embedded therein. The packaging substrate strip 100 includes a front surface, which can be used to serve as a platform for mounting electronic components and electronic packages. The packaging substrate strip 100 may have a plurality of units, and at least one of the units includes a first area A1 and a second area A2. In some embodiments, the electronic modules mounted to the first area A1 and the second area A2 may be different. It can be understood that the number of first areas A1 and the number of second areas A2 included in the packaging substrate strip 100 can vary according to actual conditions. Figure 1A In the illustrated embodiment, each first region A1 may be adjacent to two second regions A2 and located between the two second regions A2. In other embodiments, the first region A1 and the second region A2 may have various arrangements according to various layouts of the semiconductor package assembly.

[0020] In addition, at least one first type electronic component 101 is mounted on the front surface of the first area A1. The first type electronic component 101 may include various types of electronic devices, such as semiconductor chips, resistors, capacitors, or similar devices. In some embodiments, the first type electronic component 101 may be electrically connected to interconnects embedded in the package substrate strip 100 via a plurality of solder bumps.

[0021] Still reference Figure 1A In addition to the first type electronic components 101 on the first area A1, the package substrate strip 100 may also include a set of conductive patterns 102 located on the second area A2. The conductive patterns 102 may be used to attach other electronic modules. In some embodiments, the conductive patterns 102 may be exposed portions of interconnects formed within the package substrate strip 100, i.e., contact pads.

[0022] like Figure 1BAs shown, a protective layer 105 is attached to the second area A2 to cover the conductive pattern 102. In this way, the conductive pattern 102 can be isolated from potential contamination during the subsequent manufacturing process, thereby ensuring that the electrical connection between the conductive pattern 102 and other structures has good reliability. In some embodiments, the protective layer 105 can extend a certain length from the edge of the conductive pattern 102 to form a sufficient margin, which can ensure the protection provided by the protective layer 105. In addition, it is also necessary to form a sufficient gap between the corresponding first-type electronic component 101 and the protective layer 105 to avoid potential damage to the first-type electronic component 101 when the protective layer 105 is subsequently removed, which will be described in detail later.

[0023] In some preferred embodiments, the protection layer 105 should provide sufficient protection for the conductive pattern 102 and at the same time be easily removed together with the excess residue. Figure 1B In the illustrated embodiment, the protective layer 105 is an ultraviolet (UV) sensitive tape, which can be hardened after being irradiated with UV light having a certain wavelength range. The hardened UV sensitive tape can provide effective protection for the conductive pattern 102 below it. In some embodiments, the protective layer 105 may include multiple layers of different UV sensitive tapes or other similar tapes. In addition, the UV sensitive tape layer directly in contact with the conductive pattern 102 below it may have a high adhesive property to better fit on the surface of the conductive pattern 102, thereby avoiding bubbles or gaps between the protective layer 105 and the conductive pattern 102. The UV sensitive tape layer located in the upper layer may have a greater hardness after being irradiated with UV light, and thus can be easily removed. In some other embodiments, the protective layer 105 may include, for example, a polymer, plastic, ceramic or similar material. In addition, in some embodiments, the height of the conductive pattern 102 is much smaller than the height of the first type electronic component 101. Therefore, after the protective layer 105 is attached to the conductive pattern 102, the height of the protective layer 105 relative to the package substrate strip 100 can still be less than or equal to the height of the first type electronic component 101.

[0024] Next, a base mold cover 110 is formed on the first area A1 and the second area A2 to seal the first type electronic component 101 and the protective layer 105. Figure 1CAs shown, the base mold cover 110 covers the corresponding front surfaces of the first type electronic component 101 and the protective layer 105 and the front surface of the package substrate strip 100 on which the electronic component and the protective layer 105 are not mounted. The base mold cover 110 can be formed using a molding process such as an injection molding process. As mentioned earlier, since the height of the protective layer 105 is still less than or equal to the height of the first type electronic component 101, the height of the mold cover can be determined according to the height of the first type electronic component 101. In other embodiments, the relative heights of the first type electronic component 101 and the conductive pattern 102 can be varied according to the actual needs of the semiconductor package assembly. The material of the base mold cover 110 may include, for example, epoxy resin, liquid silicone resin, or similar materials.

[0025] Next, a plurality of solder bumps 115 are formed on the back surface of the package substrate strip 100, which is opposite to the front surface on which the electronic components are mounted. The solder bumps 115 can be used to attach the package substrate strip 100 to an external device, and the solder bumps 115 are electrically coupled to the interconnection lines in the package substrate 100, and thus the solder bumps 115 are also electrically coupled to the first type electronic component 101.

[0026] Then, if Figure 1D As shown, after packaging the first type electronic component 101 and the protective layer 105, as one of the several units of the packaging substrate strip 100, the packaging substrate 116 with the structure thereon is separated from the packaging substrate strip 100. The separation process can be performed along the boundary of the first area A1 or the second area A2. After separation, the packaging substrate 116 includes at least one first area A1 and one second area A2 with corresponding structures. It can be understood that the number of first areas A1 and the number of second areas A2 can vary according to the actual packaging design. It should be noted that the subsequent process will be described exemplarily with reference to the separated packaging substrate 116, however, it can be understood that the same or similar process can be applied to other units separated from the packaging substrate strip 100.

[0027] Then, if Figure 1E As shown, a shielding layer 120 is formed at least on the base mold cover 110 of the package substrate 116, which can help protect the semiconductor package assembly from electromagnetic interference. In some embodiments, the shielding layer 120 can extend to structures adjacent to the base mold cover 110, and / or other surfaces (e.g., sides) of the base mold cover 110, thereby providing more effective protection against electromagnetic interference. In some embodiments, the shielding layer 120 can be formed using a sputtering process or other applicable metal deposition process.

[0028] like Figure 1FAs shown, a portion of the base mold cover 110 formed on the second area A2 is removed to form a cavity 121 in the base mold cover 110, thereby exposing the protective layer 105 and a portion or all of the front surface of the second area A2. The cavity 121 is used to accommodate the electronic module to be installed on the second area A2. In some embodiments, the length of the cavity 121 in the horizontal direction can be sufficiently greater than the length of the protective layer 105, as long as the cavity 121 does not exceed the boundary with the adjacent first area A1. This can help to remove the protective layer 105 more thoroughly later, and can reduce potential contamination of the first type electronic component 101 on the adjacent first area A1. In some embodiments, the cavity 121 in the base mold cover 110 is formed by removing a portion of the base mold cover 110 using laser ablation, and the laser ablation has the advantages of high accuracy and high efficiency. In other embodiments, the cavity 121 in the base mold cover 110 can also be formed by a combination of one or more of milling, drilling, pinching, and etching processes. In addition, in Figure 1F In the embodiment shown in FIG. 1 , the materials of the protective layer 105 and the substrate mold cap 110 are completely different, thus resulting in completely different removal rates in the same removal process. In view of this, when the mold cap material is removed, the protective layer 105 can act as a stop layer, thereby protecting the conductive pattern 102 underneath from damage. In other words, when the protective layer 105 is exposed during the ablation process, the ablation process can be stopped.

[0029] like Figure 1G As shown, the protective layer 105 is removed from the package substrate 116, thereby exposing the corresponding surface of the conductive pattern 102 for attaching an additional electronic module. In this embodiment, the step of removing the protective layer 105 may include: the protective layer is a UV-sensitive tape in this embodiment, and after irradiating the protective layer 102 with ultraviolet light, the protective layer 102 can be hardened and peeled off from the package substrate 116. In some other embodiments, acetone, ethanol, ethyl acetate or similar organic solvents may be applied to facilitate the complete removal of the UV-sensitive tape. In some other embodiments, the removal process of the protective layer 105 may include, for example, pinching, etching or other similar removal techniques.

[0030] Next, the second type electronic component 130 may be mounted on the second area A2 and placed in the cavity 121. Figure 1HAs shown, the second type electronic component 130 may be a pre-molded electronic package covered with a shielding layer 134. More specifically, the second type electronic component 130 may include a second package substrate 131 having embedded interconnects, at least one third type electronic component 132 mounted on the second package substrate 131, and a second mold cap 133 formed on the second package substrate 131, the second mold cap 133 covering the corresponding top surface of the third type electronic component 132 and the front surface of the second package substrate 131. In addition, the shielding layer 134 formed on the flat top surface and side surfaces of the second mold cap 133 may extend continuously to the side surfaces of the second package substrate 131, which may help protect other parts of the pre-molded electronic package from electromagnetic interference.

[0031] Still reference Figure 1H , a group of solder bumps 122 are formed on the conductive pattern 102, and then the second type electronic component 130 can be mounted on the package substrate 116 via the solder bumps 122, thereby forming an electrical connection between the second type electronic component 130 and the package substrate 116. Therefore, the second type electronic component 130 can be connected to the first type electronic component 101 via the solder bumps and the interconnection lines in the package substrate, thereby forming an integrated semiconductor package assembly. After the second type electronic component 130 is attached to the conductive pattern 102, the solder bumps 122 can be reflowed. In some embodiments, the length of the cavity 121 in the horizontal direction is greater than the length of the second type electronic component 130, thereby providing sufficient space for the installation of the second type electronic component 130, so that the second type electronic component 130 can be more conveniently aligned and installed on the second area A2.

[0032] In addition, the thickness of the second type electronic component 130 is greater than the thickness of the first type electronic component 101. In this embodiment, since the second type electronic component 130 already includes the second mold cover 133, no additional molding process is required on the second type electronic component 130. Therefore, the base mold cover 110 can only seal the first type electronic component 101, thereby saving the redundant mold cover material on the second type electronic component 130. In this way, the overall thickness of the semiconductor package assembly can be significantly reduced, so that in the subsequent heating process, the thermal stress and deformation generated can be reduced. In addition, since the first type electronic component 101 and the second type electronic component 130 are respectively and individually sealed by the corresponding mold cover, the height of the corresponding mold cover can substantially correspond to the corresponding height of the first type electronic component 101 and the second type electronic component 130, respectively. Therefore, the difference between the mold cover materials on the first type electronic component 101 and the second type electronic component 130 can also be reduced, thereby reducing the uneven deformation of the semiconductor package assembly during the subsequent heating process. In this way, the top surfaces of the base mold cover 110 and the second type electronic component 130 can be parallel to each other, thereby further improving the structural uniformity of other modules subsequently attached thereto. However, it is also understood that the height of the second type electronic component 130 relative to the height of the first type electronic component 101 can be varied according to the actual needs of the package design.

[0033] Then, if Fig. 1I As shown, a filling material 140 is filled into the cavity 121 to cover the solder bump, the conductive pattern 102, the second type electronic component 130 and the surface of the second area A2 to protect the electrical connection structure from potential contamination, thereby forming a semiconductor package assembly 150. The filling material 140 can fill the gap between the second type electronic component 130 and the base mold cover 110, which provides mechanical support for the second type electronic component 130, thereby allowing the second type electronic component 130 to be better accommodated in the cavity 121 and making the second type electronic component 130 more strongly attached to the second area A2.

[0034] In some embodiments, the semiconductor package assembly 150 may be applied to any semiconductor device requiring a smaller package thickness, such as a highly integrated circuit device or the like.

[0035] exist Figures 1A to 1I In the illustrated embodiment, the second type electronic component 130 may have a preformed shielding layer, while in some other embodiments, the shielding layer of the second type electronic component may be formed together with the shielding layer on the first type electronic component. For example, the shielding layer may be formed after the filling material is filled into the cavity, so that the shielding layer may at least cover the base mold cover, the second type electronic component and the filling material.

[0036] Figures 2A to 2E FIG. 2 shows a part of the steps of the method for forming a semiconductor package assembly according to the second embodiment of the present application. Figures 2A to 2E Before the steps shown in Figures 1A to 1D For simplicity, similar steps are not described in detail here. More specifically, in Figure 2A Before the steps shown in , the method further includes the following steps: providing a packaging substrate strip having a plurality of units, and at least one of the units includes a first region and a second region, wherein at least one first type electronic component is mounted on the first region, and the second region has a group of conductive patterns; attaching a protective layer to the second region to cover the group of conductive patterns; forming a base mold cover on the first region and the second region to seal the first type electronic component and the protective layer; and then separating one of the several units of the packaging substrate strip, that is, the packaging substrate together with the structure thereon, from the packaging substrate strip. Next, reference is made to Figures 2A to 2E The following steps in the method of forming a semiconductor package assembly according to the second embodiment of the present application are described in more detail. It should be noted that the subsequent process will be described exemplarily with reference to the separated package substrate, but it should be understood that the same or similar process can be applied to other units separated from the package substrate strip.

[0037] like Figure 2A As shown, a portion of the substrate mold cover 210 on the second area B2 is removed to form a cavity 221 in the substrate mold cover 210 to expose the protective layer 205 and a portion or all of the front surface of the second area B2. The details of the formation process of the cavity 221 can be referred to Figure 1F The details of the formation process of the cavity 121 are shown in FIG.

[0038] Then, if Figure 2B As shown, the protective layer 205 is removed from the package substrate 216, thereby exposing the corresponding surface of the conductive pattern 202 for attaching other electronic modules. The details of the removal process of the protective layer 205 can be referred to Figure 1G Those details shown in the removal process of the protective layer 105 shown in FIG.

[0039] Then, if Figure 2CAs shown, the second type electronic component 230 can be mounted on the second area B2 and located in the cavity 221. In some embodiments, the second type electronic component 230 can be a pre-molded electronic package. The pre-molded electronic package may include a second packaging substrate 231 with embedded interconnects, at least one third type electronic component 232 mounted on the second packaging substrate 231, and a second mold cap 233 formed on the second packaging substrate 231. In some embodiments, the thickness of the second type electronic component 230 can be greater than the thickness of the first type electronic component 201. The details of the installation process of the second type electronic component 230 can be referred to Figure 1H Those details shown in the installation process of the second type electronic component 130 shown in FIG.

[0040] Then, if Figure 2D As shown, a filling material 240 is filled into the cavity 221 to cover the solder bump, the conductive pattern 202, the second type electronic component 230 and the surface of the second area B2. Figure 2E As shown, a shielding layer 220 is formed on the package substrate 216 to cover at least the base mold cover 210, the second type electronic component 230 and the filling material 240, thereby forming a semiconductor package assembly 250. The shielding layer 220 can extend from the base mold cover 210 to the second type electronic component 230 via the filling material 240. In some embodiments, the shielding layer 220 can extend to the structure adjacent to the base mold cover 210, and / or other surfaces (e.g., side surfaces) of the base mold cover 210. In this way, the shielding layer 220 can be a continuous layer covering the front surface and side surfaces of all structures on the package substrate 216, which can provide better protection against electromagnetic interference for the semiconductor package assembly 250.

[0041] Figures 3A to 3F FIG. 2 shows a part of the method for forming a semiconductor package assembly according to the third embodiment of the present application. In this embodiment, after removing a part of the base mold cover on the second area of ​​the package substrate, the package substrate is separated from the package substrate strip. It should be noted that Figures 3A to 3F Before the steps shown in Figures 1A to 1C For simplicity, similar steps are not described in detail here. More specifically, in Figure 3A Prior to the steps shown in , the method further includes the following steps: providing a packaging substrate strip having a plurality of units, and at least one of the units may include a first region and a second region, wherein at least one first type electronic component is mounted on the first region, and the second region has a group of conductive patterns; attaching a protective layer to the second region to cover the group of conductive patterns; and forming a base mold cover on the first region and the second region to seal the first type electronic component and the protective layer. Next, reference will be made to Figures 3A to 3FThe following steps in the method of forming a semiconductor package assembly according to the third embodiment of the present application are described in more detail.

[0042] like Figure 3A As shown, a portion of the substrate mold cover 310 on the second region C2 is removed to form a cavity 321 in the substrate mold cover 310 to expose the protective layer 305 and a portion or all of the front surface of the second region C2. The details of the formation process of the cavity 321 can be referred to Figure 1F The details of the formation process of the cavity 121 are shown in FIG.

[0043] Then, if Figure 3B As shown, the protective layer 305 is removed from the package substrate 316, thereby exposing the corresponding surface of the conductive pattern 302 for attaching other electronic modules. The details of the removal process of the protective layer 305 can be referred to Figure 1G Those details shown in the removal process of the protective layer 105 shown in FIG.

[0044] Then, if Figure 3C As shown, the second type electronic component 330 is mounted on the second region C2 and is located in the cavity 321. In some embodiments, the second type electronic component 330 may be a pre-molded electronic package. The pre-molded electronic package may include a second packaging substrate 331 with embedded interconnects, at least one third type electronic component 332 mounted on the second packaging substrate 331, and a second mold cap 333 formed on the second packaging substrate 331. In some embodiments, the thickness of the second type electronic component 330 may be greater than the thickness of the first type electronic component 301. The details of the installation process of the second type electronic component 330 may refer to Figure 1H Those details shown in the installation process of the second type electronic component 130 shown in FIG.

[0045] Then, if Figure 3D As shown, a filling material 340 is filled into the cavity 321 to cover the solder bump, the conductive pattern 302, the second type electronic component 330 and the surface of the second area C2. Since the processes of forming the cavity 321, removing the protection layer 305, installing the second type electronic component 330 and filling the cavity 321 are all performed on different areas of the same package substrate strip 300, the accuracy and efficiency of the process can be further improved.

[0046] Then, if Figure 3E As shown, one of the several units of the package substrate strip 300, that is, the package substrate 316 and the structure thereon are separated from the package substrate strip 300. Then, as shown in FIG. Figure 3FAs shown, a shielding layer 320 is formed on the package substrate 316 to cover at least the base mold cover 310, the second type electronic component 330 and the filling material 340, thereby forming a semiconductor package assembly 350. The shielding layer 320 can extend from the base mold cover 310 to the second type electronic component 330 via the filling material 340. In some embodiments, the shielding layer 320 can further extend to the structure adjacent to the base mold cover 310 and / or other surfaces (e.g., side surfaces) of the base mold cover 310. In this way, the shielding layer 320 can provide better anti-electromagnetic interference protection for the semiconductor package assembly 350.

[0047] In some embodiments, the semiconductor package assembly can be applied to any semiconductor device requiring a smaller package thickness and less electromagnetic interference, such as a highly integrated circuit device or the like.

[0048] Although the exemplary method for forming a semiconductor package assembly of the present application is described in conjunction with the corresponding drawings, those skilled in the art will appreciate that modifications and adaptations may be made to the method without departing from the scope of the present invention.

[0049] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. In addition, other embodiments will be apparent to those skilled in the art by considering the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that the present application and the embodiments herein be considered exemplary only, with the true scope and spirit of the invention being indicated by the list of the appended exemplary claims.

Claims

1. A method for manufacturing a semiconductor package assembly, characterized in that: The method comprises: Providing a packaging substrate, the packaging substrate comprising a first area and a second area, wherein at least one first type electronic component is mounted on the first area; attaching a protective layer to the second region; forming a substrate mold cover on the first region and the second region to seal the at least one first type electronic component and the protective layer; removing a portion of the base mold cover formed on the second region to form a cavity in the base mold cover, wherein the cavity exposes the protective layer; removing the protective layer from the packaging substrate; mounting a second type of electronic component on the second region; and Filling material into the cavity.

2. The method according to claim 1, characterized in that The second type of electronic component is a pre-molded electronic package.

3. The method according to claim 1, characterized in that The thickness of the second type electronic component is greater than the thickness of the first type electronic component.

4. The method according to claim 1, characterized in that: The step of removing a portion of the substrate mold cover formed on the second area comprises: A portion of the base mold cover is removed using a laser ablation process.

5. The method according to claim 1, characterized in that The protective layer is an ultraviolet sensitive tape, and the step of removing the protective layer from the packaging substrate comprises: irradiating the UV-sensitive tape with UV light; and The UV-sensitive tape is peeled off from the packaging substrate.

6. The method according to claim 1, characterized in that The package substrate includes a set of conductive patterns located on the second area, and the process of attaching the protection layer to the second area includes: The protection layer is attached to the second region to cover the set of conductive patterns.

7. The method according to claim 6, characterized in that The step of mounting a second type of electronic component on the second area comprises: forming a set of solder bumps on the set of conductive patterns; placing the second type of electronic component on the set of solder bumps; and The set of solder bumps are reflowed.

8. The method according to claim 1, characterized in that The package substrate is one unit of a package substrate strip having a plurality of units, wherein before removing a portion of the base mold cover formed on the second area, the method further comprises: separating the package substrate from the package substrate strip; and A shielding layer is formed at least on the base mold cover of the packaging substrate.

9. The method according to claim 8, characterized in that The second type of electronic component is a pre-molded electronic package covered with a shielding layer.

10. The method according to claim 1, characterized in that After filling the cavity with a filling material, the method further comprises: A shielding layer is formed on the packaging substrate to at least cover the base mold cover, the second type electronic component and the filling material.

11. The method according to claim 10, characterized in that The package substrate is one unit of a package substrate strip having a plurality of units, wherein after removing a portion of the base mold cover formed on the second area, the method further comprises: The package substrate is separated from the package substrate strip.

12. The method according to claim 10, characterized in that The package substrate is one unit of a package substrate strip having a plurality of units, wherein before removing a portion of the base mold cover formed on the second area, the method further comprises: The package substrate is separated from the package substrate strip.

13. A semiconductor package assembly, characterized in that: include: A packaging substrate, the packaging substrate comprising a first area and a second area; at least one first type electronic component, the at least one first type electronic component being mounted on the first region; a base mold cover formed on the packaging substrate to seal the at least one first type electronic component, wherein the base mold cover comprises a cavity, and the cavity exposes the second area of ​​the packaging substrate; a second type of electronic components mounted on the second region; and A filling material is filled in the cavity.

14. The semiconductor package assembly according to claim 13, wherein: The second type of electronic component is a pre-molded electronic package.

15. The semiconductor package assembly according to claim 14, wherein: The pre-molded electronic package is covered with a shielding layer.

16. The semiconductor package assembly according to claim 13, wherein: The thickness of the second type electronic component is greater than the thickness of the first type electronic component.

17. The semiconductor package assembly according to claim 13, wherein: Further including: A shielding layer is formed at least on the base mold cover.

18. The semiconductor package assembly according to claim 17, wherein: The shielding layer extends from the base mold cover through the filling material to the second type electronic component.

19. The semiconductor package assembly according to claim 13, wherein: The cavity is formed by the following process: attaching a protective layer to the second region; forming a portion of the substrate mold cover on the second region; removing the portion of the base mold cover formed on the second region to expose the protective layer; as well as The protection layer is removed from the packaging substrate.

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