Packaging structure and forming method thereof
By introducing a carbon particle molded layer with high thermal conductivity into the semiconductor die packaging structure, the challenges of heat dissipation and hot spot management of the packaging structure in the prior art are solved, and more efficient heat diffusion and temperature management are achieved.
Patent Information
- Application Number
- CN202411906019.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-28
- Filing Date
- 2024-12-23
- Publication Date
- 2025-04-15
AI Technical Summary
Existing semiconductor die packaging technologies face manufacturing challenges, especially the issue of effectively dissipating heat and managing hot spots while increasing density and functionality.
Using a package structure including a redistribution structure, packaging assembly, underfill and a molded layer, carbon particles with high thermal conductivity are embedded in the molded layer to improve thermal conductivity and promote heat diffusion.
By improving thermal conductivity and improving heat diffusion, the operating temperature of packaging components and semiconductor dies can be effectively reduced, and the heat dissipation performance of the packaging structure is improved.
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Figure CN119833485A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present application relate to a packaging structure and a method for forming the same. Background Art
[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous advances in semiconductor manufacturing processes have produced semiconductor devices with more sophisticated components and / or higher integration. Functional density (i.e., the number of interconnected devices per chip area) has generally increased, while component size (i.e., the smallest component that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.
[0003] The chip package not only provides protection for the semiconductor device from environmental contamination, but also provides a connection interface for the semiconductor device packaged therein. Smaller package structures occupying less space or being lower in height have been developed to package semiconductor devices.
[0004] New packaging technologies have been developed to further improve the density and functionality of semiconductor dies.These relatively new packaging technologies for semiconductor dies face manufacturing challenges. Summary of the invention
[0005] Some embodiments of the present application provide a packaging structure including: a redistribution structure; a first packaging component and a second packaging component attached to a first side of the redistribution structure; a bottom filler located above the redistribution structure around a lower portion of the first packaging component and the second packaging component; and a molding layer formed above the bottom filler and around an upper portion of the first packaging component and the second packaging component, wherein the molding layer includes: a base material; and a filler embedded in the base material, wherein a thermal conductivity of the filler is greater than approximately 400 W / mK.
[0006] Other embodiments of the present application provide a packaging structure including: a first redistribution structure; a first packaging component and a second packaging component attached to a first side of the first redistribution structure and spaced apart from each other; a bottom filler located around the first packaging component and the second packaging component; a first molding layer located above the bottom filler and above the first side of the first redistribution structure, wherein the first molding layer includes first carbon particles, wherein the thermal conductivity of the first molding layer is greater than the thermal conductivity of the bottom filler; and a first semiconductor die attached to a second side of the first redistribution structure, wherein, in a top view, the first semiconductor die partially overlaps with the first packaging component and the second packaging component.
[0007] Some other embodiments of the present application provide a method for forming a packaging structure, comprising: forming a redistribution structure; disposing a first packaging component and a second packaging component above the redistribution structure, wherein the first packaging component is separated from the second packaging component by a first spacer; forming a bottom filler around the first packaging component and the second packaging component and in a lower area of the first spacer; forming a first molding layer above the first packaging component, the second packaging component and the bottom filler, wherein the first molding layer includes first carbon particles; and partially removing the first molding layer to expose the top surfaces of the first packaging component and the second packaging component, wherein the upper area of the first spacer is filled with the first molding layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.
[0009] Figure 1A and Figure 1B A schematic top view of a package structure according to some embodiments is shown.
[0010] Figures 2A to 2M A cross-sectional view illustrating an intermediate stage in the fabrication of a package structure according to some embodiments is shown.
[0011] Figure 2G-1 According to some embodiments Figure 2G An enlarged cross-sectional view of the packaging structure of region R_2G shown in FIG.
[0012] Figure 2I-1 According to some embodiments Fig.2I An enlarged cross-sectional view of the packaging structure of region R_2I shown in FIG.
[0013] Figure 3A and Figure 3B A cross-sectional view is shown of an intermediate stage in the fabrication of a package structure 100 ′ in accordance with some embodiments.
[0014] Figure 4 A schematic top view of a package structure according to some embodiments is shown.
[0015] Figure 5A A schematic top view of a package structure according to some embodiments is shown.
[0016] Figure 5B According to some embodiments, Figure 5A Line X 5A -X5A 'A cross-sectional view of the packaging structure shown.
[0017] Figure 5C A cross-sectional view of a package structure according to some embodiments is shown.
[0018] Figure 6 A schematic top view of a package structure according to some embodiments is shown.
[0019] Fig. 7A and Figure 7B A schematic top view of a package structure according to some embodiments is shown.
[0020] Fig. 8A and Figure 8B A cross-sectional view illustrating an intermediate stage in the fabrication of a package structure according to some embodiments is shown.
[0021] Fig. 9 A cross-sectional view of a package structure according to some embodiments is shown.
[0022] Fig.10 A layout of a package structure according to some embodiments is shown.
[0023] Fig.11A A schematic top view of a package structure according to some embodiments is shown.
[0024] Fig. 11B According to some embodiments, Fig.11A Line X 11B -X 11B 'A cross-sectional view of the packaging structure shown.
[0025] Fig. 11C A cross-sectional view of a package structure according to some embodiments is shown.
[0026] Fig.12 A layout of a package structure according to some embodiments is shown.
[0027] Fig.13 A schematic top view of a package structure according to some embodiments is shown.
[0028] Fig.14 A layout of a package structure according to some embodiments is shown.
[0029] Fig.15 A schematic top view of a package structure according to some embodiments is shown.
[0030] Fig.16 A layout of a package structure according to some embodiments is shown. DETAILED DESCRIPTION
[0031] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.
[0032] Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. It should be understood that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or eliminated for other embodiments of the method.
[0033] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.
[0034] Embodiments of the present disclosure may be directed to packaging structures, such as three-dimensional (3D) packaging, 3D-IC devices, and 2.5D packaging. Embodiments of the present disclosure form a packaging structure including a substrate that carries one or more dies or packages and a protective element (such as a protective cover) next to the die or package. The protective element may also be used as a warpage control element and / or a heat dissipation element.
[0035] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on 3D packages or 3DIC devices and / or 2.5D packages. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.
[0036] The package structure may include individual package components, and these package components may generate heat during operation and may be considered as hot spots in the device. Therefore, a molded layer with a filler having high thermal conductivity may be used to seal the package component so that the heat generated from the package component may be diffused (e.g., dissipated) through the molded layer. In addition, the package structure may also include a semiconductor die electrically connected to the package component. These semiconductor die may also generate heat during operation. Therefore, a molded layer with a filler having high thermal conductivity may also be used to seal the semiconductor die. Therefore, the temperature of the semiconductor device during operation may be reduced.
[0037] Figure 1A and Figure 1B A schematic top view of a package structure 100 according to some embodiments is shown. To better understand the structure, XYZ coordinate references are provided in the following figures. In addition, to better understand the inventive concepts of the disclosed embodiments, the following figures may have been simplified for clarity. Additional components may be included, and some of the components described below may be replaced, modified, or eliminated.
[0038] More specifically, Figure 1A 1 shows a layout of package components 10 and 20 in a package structure 100 according to some embodiments. In addition, according to some embodiments, package components 10 and 20 are sealed (e.g., surrounded) by a molding layer 25. In some embodiments, the space between package components 10 and 20 in the X direction and the Y direction is filled with a molding layer 25.
[0039] In some embodiments, package components 10 and 20 are semiconductor dies with different functions. In some embodiments, package component 10 includes: a memory device including multiple memory dies, such as a hybrid memory multidimensional cube (HMC) module, a high bandwidth memory (HBM) module, etc. In some embodiments, package component 20 includes a system-on-chip (SoC) die, a chip-scale package (CSP), or a combination thereof. In some embodiments, package component 10 is an HBM die, and package component 20 is an SoC die. The heat generated by package component 10 can be regarded as a hot spot in package structure 100.
[0040] In some embodiments, one of the package components 20 is sandwiched between two of the package components 10 in the X direction, such as Figure 1A In some embodiments, one of the package components 20 and two of the package components 10 are aligned with each other in the X direction. In some embodiments, the package components 10 are aligned with each other in the Y direction, and the package components 20 are aligned with each other in the Y direction. The package components 10 and 20 may be formed on a redistribution structure ( Figure 1A The process is not shown in the figure), and the details of the process will be described later.
[0041] In some embodiments, the molding layer 25 includes a base material 26 and a filler 28 embedded in the base material 26. The filler 28 may have a high thermal conductivity so that the heat generated by the package components 10 and 20 can be diffused laterally through the molding layer 25. In some embodiments, the thermal conductivity of the filler 28 is greater than about 400W / mK. In some embodiments, the concentration of the filler 28 is in the range of from about 20wt% to about 80wt%. The concentration of the filler 28 should be high enough to provide sufficient thermal conductivity. On the other hand, the concentration of the filler 28 may not be too high, or the filler 28 may not be uniformly mixed in the base material 26. In some embodiments, the particle size of the filler 28 is in the range of from about 10um to about 70um. In some embodiments, the filler 28 is a carbon particle, such as graphite, graphene, or diamond-like carbon particles. In some embodiments, the molding layer 25 includes more than one type of filler 28. In some embodiments, the molding layer 25 includes a single type of filler 28.
[0042] Figure 1B The layout of semiconductor dies 30 and 40 in package structure 100 according to some embodiments is further shown. More specifically, according to some embodiments, semiconductor dies 30 and 40 are embedded active dies and are electrically coupled to package components 10 and 20 through redistribution structures. In some embodiments, semiconductor dies 30 and 40 are embedded local interconnect dies.
[0043] In some embodiments, each of semiconductor die 30 is configured to provide electrical connections between one or more of package components 10 and one or more of package components 20 in the X direction ( Figure 1B 1 and 2. In some embodiments, in the top view, each of the semiconductor dies 30 partially overlaps with two of the package components 10 and one of the package components 20, as shown in FIG. Figure 1B . In some embodiments, in the top view, each of the semiconductor dies 30 partially overlaps two adjacent sidewall surfaces of two package components 10 and one sidewall surface of one package component 20. In some embodiments, each of the semiconductor dies 40 is configured to provide an electrical connection between two of the package components 30 in the Y direction. In some embodiments, in the top view, each of the semiconductor dies 40 vertically overlaps two of the package components 20.
[0044] Figures 2A to 2M 1 shows a cross-sectional view of an intermediate stage of manufacturing a package structure 100 according to some embodiments. More specifically, according to some embodiments, Figure 1B Line X 1B -X1B ' shows a cross-sectional view.
[0045] like Figure 2A As shown in FIG. 1 , in accordance with some embodiments, a through-insulated via (TIV) 104 is formed over a carrier substrate 102. The carrier substrate 102 may be configured to provide structural support during a manufacturing process of the package structure 100. In some embodiments, the carrier substrate 102 is made of a material such as silicon, a polymer, a polymer composite, a metal foil, a ceramic, a glass, a glass epoxy, beryllium oxide, a tape, or other suitable materials for structural support. In some embodiments, the carrier substrate 102 is a sapphire glass substrate.
[0046] In some embodiments, the insulating via 104 is made of a conductive material, such as copper, titanium, tungsten, aluminum, etc. In some embodiments, a seed layer (not shown) is formed before forming the insulating via 104. The insulating via 104 can be formed by the following process. A photoresist layer can be formed above the carrier substrate 102 by spin coating, etc. The photoresist layer can then be exposed to light for patterning, and an opening can be formed in the photoresist layer. After the opening is formed, the insulating via 104 can be formed in the opening by filling the opening with a conductive material by plating (such as electroplating or chemical plating, etc.). The photoresist can then be removed by ashing or stripping processes, such as using oxygen plasma, etc.
[0047] According to some embodiments, after forming insulating via 104, semiconductor dies 30 and 40 ( Figure 2B Not shown, see Figure 1B ) is disposed above the carrier substrate 102, such as Figure 2B Although the semiconductor die 40 is not Figure 2B , but the structure of semiconductor die 40 may be similar to Figures 2B to 2M Those of the semiconductor die 30 shown in and described below or with Figures 2B to 2M 1 and 12 are the same as those of the semiconductor die 30 shown in and described later. In some embodiments, the insulating via 104 is interposed between the semiconductor dies 30 and 40 and is spaced apart from the semiconductor dies 30 and 40. In some embodiments, some of the semiconductor dies 30 and 40 are formed adjacent to each other without the insulating via 104 formed therebetween. In some embodiments, the closest distance between two adjacent semiconductor dies 30 and 40 is in a range from about 50 μm to about 150 μm.
[0048] In some embodiments, each of semiconductor dies 30 and 40 includes a substrate 202, a conductive via 204 formed through substrate 202, and an interconnect structure 206 formed over substrate 202. In some embodiments, interconnect structure 206 includes a plurality of metallization layers, and the metallization layers include a dielectric layer 208 and a conductive structure 210 formed in dielectric layer 208. Conductive structure 210 may include metal lines and metal vias formed in dielectric layer 208. Furthermore, conductive via 204 is electrically connected to conductive structure 210 in interconnect structure 206 according to some embodiments. In some embodiments, conductive connectors 212 are formed over interconnect structure 206 to be electrically connected to conductive structure 210 in interconnect structure 206. The layout of conductive structure 210 in interconnect structure 208 in each of semiconductor dies 30 and 40 may be the same or different.
[0049] Substrate 202 may be a semiconductor substrate, such as silicon, which may be doped or undoped, and which may be an active layer of a silicon wafer or a semiconductor on insulator (SOI) substrate, etc. Substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, conductive vias 204 are formed to pass through substrate 202 to electrically connect both sides of substrate 202. In some embodiments, conductive vias 204 are made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or a combination thereof.
[0050] The interconnect structure 206 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. In some embodiments, the dielectric layer 208 includes multiple layers made of a low-k dielectric material having a k value lower than 7. In some embodiments, the dielectric layer 208 is made of SiO 2 , SiN, SiCN, SiOC, SiOCN, etc. The dielectric layer 208 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other applicable processes. In some embodiments, the conductive structure 210 is made of W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, other applicable conductive materials, or combinations thereof. The conductive structure 210 can be formed using processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition process.
[0051] The conductive connector 212 may include a bonding pad, a micro bump, a copper pillar, a copper layer, a nickel layer, a lead-free layer, an electroless nickel electroless palladium immersion gold (ENEPIG) layer, a Sn / Ag layer, a Sn / Pb layer, etc. In some embodiments, the conductive connector 212 is electrically connected to the conductive structure 210 in the interconnect structure 206 .
[0052] According to some embodiments, after semiconductor dies 30 and 40 are disposed over carrier substrate 102 , encapsulant 106 is formed over carrier substrate 102 , such as Figure 2C . More specifically, encapsulant 106 is formed to laterally encapsulate insulating vias 104 and semiconductor dies 30 and 40. In some embodiments, in this step, insulating vias 104 and top surfaces of semiconductor dies 30 and 40 are covered by encapsulant 106. In some embodiments, encapsulant 106 includes a molding compound such as resin, polyimide, PPS, PEEK, PES, epoxy molding compound (EMC), or a combination thereof.
[0053] According to some embodiments, after the sealant 106 is formed, a planarization process is performed on the sealant 106 until the insulating via 104 and the conductive connection 212 are exposed, such as Figure 2D . A planarization process may be performed to remove excess portions of the encapsulant 106 by using a mechanical grinding process, a chemical mechanical polishing (CMP) process, or the like. In some embodiments, during the planarization process, the insulating vias 104 and / or the conductive connections 212 are also slightly polished. According to some embodiments, after the planarization process, the top surfaces of the insulating vias 104 and the conductive connections 212 are substantially flush with the top surface of the encapsulant 106.
[0054] Next, according to some embodiments, a redistribution structure 108 is formed over semiconductor dies 30 and 40, insulating vias 104, and encapsulant 106, and a conductive pad 114 is formed over redistribution structure 108, such as Figure 2E In some embodiments, the redistribution structure 108 includes a plurality of insulating layers 110 and a redistribution layer (RDL) 112, and the redistribution layer 112 is electrically connected to the insulating vias 104 and the conductive connections 212 of the semiconductor dies 30 and 40. The redistribution layer 112 can be considered a fan-out structure. Figure 2E The number of insulating layers 110 and the number of redistribution layers 112 shown in FIG. 1 are merely examples and are not intended to be limiting. For example, the number of insulating layers 110 and the number of redistribution layers 112 may range from about 1 to about 15.
[0055] In some embodiments, the insulating layer 110 is made of one or more suitable dielectric materials, such as oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), polymer materials, polyimide materials, low-k dielectric materials, molding materials (e.g., EMC, etc.), another dielectric material, or a combination thereof. The insulating layer 110 can be formed by processes such as spin coating, lamination, CVD, etc., or a combination thereof. In some embodiments, the redistribution layer 112 is made of a conductive material, such as copper, titanium, tungsten, aluminum, or a combination thereof. The conductive material can be formed by a deposition process such as electroplating, chemical plating, etc.
[0056] According to some embodiments, after forming the redistribution structure 108, the conductive pad 114 is formed over the redistribution structure 108, such as Figure 2E . In some embodiments, the conductive pad 114 is physically connected to the redistribution layer 112 in the redistribution structure 108. In addition, according to some embodiments, the conductive pad 114 is electrically connected to the insulating via 104 and the conductive connector 212 of the semiconductor die 30 and 40 through the redistribution layer 112 in the redistribution structure 108. In some embodiments, the conductive pad 114 is made of a conductive material, such as W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, Al, other suitable conductive materials, or combinations thereof. In some embodiments, the conductive pad 114 and the redistribution layer 112 are made of different conductive materials.
[0057] Thereafter, according to some embodiments, package components 10 and 20 are attached (eg, bonded) to redistribution structure 108 , such as Figure 2F and Figure 1B More specifically, according to some embodiments, package components 10 and 20 are bonded to conductive pads 114 above redistribution structure 108 via conductive connectors 116. As previously described, package components 10 and 20 may be Figure 1A and Figure 1B The layout shown in FIG. 1 is disposed above the redistribution structure 108. In addition, according to some embodiments, the package assembly 10 is an HBM die, and the package assembly 20 is an SoC die. In addition, according to some embodiments, the package assemblies 10 and 20 include conductive pads 118 electrically connected to the devices in the package assemblies 10 and 20. In some embodiments, the conductive pads 114 are made of a conductive material, such as W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, Al, other applicable conductive materials, or combinations thereof.
[0058] In some embodiments, the conductive connector 116 is bonded to the conductive pad 118 of the package assembly 10 and 20. In some embodiments, the conductive connector 116 is a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel plating-electroless palladium plating-immersion gold technology (ENEPIG), etc. In some embodiments, the conductive connector 116 is a microbump vertically sandwiched between the conductive pads 114 and 118. In some embodiments, the conductive connector 116 is made of a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 116 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc., and a reflow process can be implemented to shape the material into a desired bump shape. In some embodiments, the conductive connector 116 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some other embodiments, the package components 10 and 20 are bonded to the redistribution structure 108 by dielectric-to-dielectric bonding and metal-to-metal bonding.
[0059] According to some embodiments, after the package components 10 and 20 are bonded to the redistribution structure 108, an underfill 120 is formed around the package components 10 and 20, such as Figure 2G as shown in . Figure 2G-1 According to some embodiments Figure 2G 2G is an enlarged cross-sectional view of the package structure 100 shown in FIG. 2 . More specifically, according to some embodiments, the bottom surface and lower portions of the side walls of the package components 10 and 20 are surrounded and covered by the bottom filler 120. In addition, according to some embodiments, the conductive pads 114 and 118 and the conductive connector 116 are embedded in the bottom filler 120. In some embodiments, the top surface and upper portions of the side walls of the package components 10 and 20 are not covered by the bottom filler 120.
[0060] More specifically, according to some embodiments, package component 10 has sidewall surface 10_S facing sidewall surface 20_S of package component 20, and lower portions of sidewall surfaces 10_S and 20_S are covered by bottom filler 120, as shown in FIG. Figure 2G-1 In some embodiments, the package components 10 and the package components 20 are separated by a space SP in the X direction, and the lower area of the space SP is filled with a bottom filler 120. In some embodiments, the height H of the bottom filler 120 in the space SP is 1 In some embodiments, the underfill 120 has a concave top surface in the space SP between the package components 10 and 20. Figure 2G, but according to some embodiments, the bottom filler 120 is formed on Figure 1A That is, the interval between two adjacent package components 10 in the Y direction may also have a spacing similar to Figure 2G-1 The bottom filler 120 is shown in FIG.
[0061] In some embodiments, the bottom filler 120 is made of a polymer, an epoxy resin, etc. After the package components 10 and 20 are attached to the redistribution structure 108, the bottom filler 120 can be formed by a capillary flow process. After the bottom filler 120 is formed, a curing process can be implemented. The curing process may include heating the bottom filler 120 to a predetermined temperature for a predetermined period of time using an annealing process or other heating process. The curing process may also include an ultraviolet (UV) light exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination thereof with a heating process.
[0062] Next, according to some embodiments, a molding layer 25 is formed over the bottom filler 120, such as Figure 2H . More specifically, according to some embodiments, the package components 10 and 20 and the bottom filler 120 are covered and surrounded by a mold layer 25. As previously described, the mold layer 25 includes a base material 26 and a filler 28 embedded in the base material 26. The filler 28 may have a high thermal conductivity so that the heat generated by the package components 10 and 20 can be diffused laterally through the mold layer 25. In some embodiments, the mold layer 25 is formed by mixing the filler 28 into the base material 26. In some embodiments, the base material 26 is an epoxy resin. In some embodiments, the filler 28 is carbon particles, such as graphite, graphene, diamond-like carbon particles. In some embodiments, the mold layer 25 and the bottom filler 120 are made of different materials. In some embodiments, the thermal conductivity of the mold layer 25 is greater than the thermal conductivity of the bottom filler 120.
[0063] In some embodiments, filler 28 is graphite particles. In some embodiments, the particle size of the graphite particles is in the range of from about 30um to about 70um. If the particle size is too small, the formation of the particles may be challenging. On the other hand, if the particle size is too large, it may be difficult to uniformly mix the particles into the base material 26. In some embodiments, the concentration of the graphite particles is in the range of from about 20wt% to about 80wt%. If the concentration is too small, the resulting molded layer may not be able to provide sufficient thermal conductivity. On the other hand, if the concentration is too large, it may be difficult to uniformly mix the particles into the base material 26. In some embodiments, the graphite particles have a thermal conductivity in the range of from about 1000W / mK to about 4000W / mK. In some embodiments, the graphite particles have a melting point of about 3527°C. In some embodiments, the graphite particles have a density in the range of from about 1.9g / cm^3 to about 2.2g / cm^3.
[0064] In some embodiments, filler 28 is diamond-like carbon particles. In some embodiments, the particle size of diamond-like carbon particles is in the range of from about 10um to about 70um. If the particle size is too small, the formation of particles may be challenging. On the other hand, if the particle size is too large, it may be difficult to uniformly mix the particles into the base material 26. In some embodiments, the concentration of diamond-like carbon particles is in the range of from about 20wt% to about 80wt%. If the concentration is too small, the resulting molded layer may not be able to provide sufficient thermal conductivity. On the other hand, if the concentration is too large, it may be difficult to uniformly mix the particles into the base material 26. In some embodiments, diamond-like carbon particles have a thermal conductivity in the range of from about 400W / mK to about 1000W / mK. In some embodiments, graphite particles have a density in the range of from about 3.2g / cm^3 to about 3.4g / cm^3.
[0065] The molding layer 25 can be applied using a wafer level molding process. The molding layer 25 can be molded using, for example, compression molding, transfer molding, molded underfill (MUF) or other methods. A curing process can be applied to the molding layer 25. The curing process can include heating the molding layer 25 to a predetermined temperature for a predetermined period of time using an annealing process or other heating process. The curing process can also include an ultraviolet (UV) light exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination thereof with a heating process.
[0066] According to some embodiments, after forming the molding layer 25, a planarization process is performed until the top surfaces of the package components 10 and 20 are exposed, such as Fig.2I as shown in . Figure 2I-1 According to some embodiments Fig.2I2 is an enlarged cross-sectional view of the package structure 100 of the region R_2I shown in FIG. A planarization process may be performed to remove an excess portion of the molding layer 25 by using a mechanical grinding process, a chemical mechanical polishing (CMP) process, or the like. In some embodiments, the package components 10 and 20 are also slightly polished in the planarization process. According to some embodiments, after the planarization process, the top surfaces of the package components 10 and 20 are substantially flush with the top surface of the molding layer 25.
[0067] In some embodiments, the sidewall surface 10_S of the package component 10 and the upper portion of the sidewall surface 20_S of the package component 20 are covered by the molding layer 25, such as Figure 2I-1 In some embodiments, an upper region of the space SP between the package components 10 and 20 is filled with the molding layer 25 , and a lower region of the space SP is filled with the underfill 120 .
[0068] In some embodiments, the contact height between the sidewall surface 10_S of the package component 10 and the molding layer 25 is greater than the contact height between the sidewall surface 10_S of the package component 10 and the bottom filler 120. Similarly, the contact height between the sidewall surface 20_S of the package component 20 and the molding layer 25 is greater than the contact height between the sidewall surface 20_S of the package component 20 and the bottom filler 120. Because the molding layer 25 has a greater thermal conductivity than the bottom filler 120, and the contact height between the molding layer 25 and the package components 10 and 20 is relatively large, the heat generated by the package components 10 and 20 can be laterally diffused faster.
[0069] In some embodiments, in the Z direction, the height H of the molding layer 25 in the interval SP is 2 is greater than the height H of the bottom fill 120 in the space SP 1 In some embodiments, the height H of the molding layer 25 in the interval SP is 2 In the range from about 600 μm to about 650 μm. In some embodiments, the molding layer 25 and the bottom filler 120 have a curved interface. That is, according to some embodiments, the molding layer 25 has a convex bottom surface that contacts the top surface of the bottom filler 120 in the gap SP between the package components 10 and 20. In some embodiments, the package component 10 vertically overlaps the molding layer 25 and the bottom filler 120 in the gap SP.
[0070] Next, according to some embodiments, the carrier substrate 124 is attached to the molding layer 25 and the package components 10 and 20, such as Figure 2J. Carrier substrate 124 may be configured to provide structural support during the manufacturing process of package structure 100. In some embodiments, carrier substrate 124 is made of a material such as silicon, a polymer, a polymer composite, a metal foil, a ceramic, a glass, a glass epoxy, beryllium oxide, a tape, or other suitable materials for structural support. In some embodiments, carrier substrate 124 is a sapphire glass substrate. In some embodiments, carrier substrates 102 and 124 are made of the same material, but have different thicknesses.
[0071] According to some embodiments, after the carrier substrate 124 is attached to the molding layer 25, the package structure is turned upside down and the carrier substrate 102 is removed, such as Figure 2K . In some embodiments, carrier substrate 102 is removed by a carrier stripping process. The carrier stripping process may use any suitable process to remove carrier substrate 102, such as etching, grinding, and mechanical stripping. In some embodiments, after removing carrier substrate 102, residues such as adhesive may remain on the exposed surfaces of semiconductor dies 30 and 40. Next, according to some embodiments, a cleaning process 126 is performed to clean the exposed surfaces of semiconductor dies 30 and 40, such as Figure 2L as shown in .
[0072] Thereafter, according to some embodiments, a redistribution structure 140 is formed over the sealant 106 , such as Figure 2M In some embodiments, redistribution structure 140 includes a plurality of insulating layers 142 and a redistribution layer (RDL) 144, and redistribution layer 144 is electrically connected to insulating vias 104 and conductive connections 212 of semiconductor dies 30 and 40. Redistribution layer 144 may be considered a fan-out structure. Figure 2M The number of insulating layers 142 and the number of redistribution layers 144 shown in FIG. 1 are merely examples and are not intended to be limiting. For example, the number of insulating layers 142 and the number of redistribution layers 144 may range from about 1 to about 15.
[0073] In some embodiments, the insulating layer 142 is made of one or more suitable dielectric materials, such as oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), polymer materials, polyimide materials, low-k dielectric materials, molding materials (e.g., EMC, etc.), another dielectric material, or a combination thereof. The insulating layer 142 can be formed by processes such as spin coating, lamination, CVD, etc., or a combination thereof. In some embodiments, the redistribution layer 144 is made of a conductive material, such as copper, titanium, tungsten, aluminum, another metal, or a combination thereof. The conductive material can be formed by a deposition process such as electroplating, chemical plating, etc.
[0074] According to some embodiments, after forming the redistribution structure 140, a conductive connector 146 is formed over the redistribution structure 140, and the package structure 100 is formed, such as Figure 2M . Conductive connector 146 may include a bonding pad, a microbump, a copper pillar, a copper layer, a nickel layer, a lead-free layer, an electroless nickel-electroless palladium-immersion gold (ENEPIG) layer, a Sn / Ag layer, a Sn / Pb layer, etc. In some embodiments, conductive connector 146 includes conductive pillar 148 and a solder ball 150 formed over conductive pillar 148. In some embodiments, conductive connector 146 is electrically connected to redistribution layer 144 in redistribution structure 140.
[0075] As previously described, according to some embodiments, the package structure 100 includes a redistribution structure 108 and package components 10 and 20 attached to the redistribution structure 108 in the Z direction and spaced apart from each other in the X direction and the Y direction. Figure 1A and Figure 2M In addition, according to some embodiments, underfill 120 is formed around lower portions of package components 10 and 20 above redistribution structure 108 , and molding layer 25 is formed over underfill 120 and around upper portions of package components 10 and 20 .
[0076] As previously described, package components 10 and 20 may generate heat during operation. For example, package component 10 may be an HBM die, and the area around the HBM die may be considered a hot spot of package structure 100. Therefore, according to some embodiments, a mold layer 25 having a relatively high thermal conductivity is applied to package structure 100 to facilitate heat dissipation during operation. Figure 2I-1 As shown in , according to some embodiments, the mold layer 25 has a first portion sandwiched between the upper portions of the package components 10 and 20 in the X direction, the bottom filler 120 has a second portion sandwiched between the lower portions of the package components 10 and 20 in the X direction, and the thickness of the first portion of the mold layer 25 is greater than the thickness of the second portion of the bottom filler 120 in the Z direction. The thickness of the mold layer 25 is greater than the thickness of the bottom filler 120, so that the heat dissipation of the device can be greatly improved. In some embodiments, the mold layer 25 is vertically sandwiched (e.g., in the Z direction) between the redistribution structures 108 and 140.
[0077] Figure 3A and Figure 3BA cross-sectional view of an intermediate stage of manufacturing a package structure 100' according to some embodiments is shown. According to some embodiments, the package structure 100' can be similar to the previously described package structure 100, except that the encapsulant 106 is replaced by the molding layer 25'. The processes and materials used to form the package structure 100' can be similar to those previously described for forming the package structure 100 or the same as those previously described for forming the package structure 100, and are not repeated here.
[0078] More specifically, according to some embodiments, implementing Figure 2A and Figure 2B The process shown in FIG. 1 is repeated, and a mold layer 25′ is formed around the semiconductor dies 30 and 40 and the insulating vias 104, as shown in FIG. Figure 3A That is, according to some embodiments, the semiconductor dies 30 and 40 and the insulating vias 104 are sealed in the mold layer 25'. Similar to the mold layer 25, according to some embodiments, the mold layer 25' also includes a base material 26 and a filler 28 embedded in the base material 26. Because the filler 28 has a relatively high thermal conductivity, the heat can be diffused laterally faster.
[0079] In some embodiments, the filler 28 in the molded layer 25' is the same as the filler 28 in the molded layer 25. In some embodiments, the filler 28 in the molded layer 25' is the same as the filler 28 in the molded layer 25, but has a different concentration. In some embodiments, the filler 28 in the molded layer 25' is the same as the filler 28 in the molded layer 25, but has a different particle size. In some embodiments, the filler 28 in the molded layer 25' is different from the filler 28 in the molded layer 25, but the base material 26 is the same.
[0080] Then, according to some embodiments, implementing Figures 2D to 2M The process shown in FIG. 1 is used to form a package structure 100 ′, as shown in FIG. Figure 3B The package structure 100' may also have Figure 1A and Figure 1B Similar to package structure 100 , package structure 100 ′ includes a redistribution structure 108 , package components 10 and 20 attached to a first side of the redistribution structure 108 and spaced apart from each other in the X and Y directions, and semiconductor dies 30 and 40 attached to a second side of the redistribution structure 108 in accordance with some embodiments.
[0081] Furthermore, according to some embodiments, the mold layer 25 is formed over a first side of the redistribution structure 108, and the mold layer 25′ is formed over a second side of the redistribution structure 108. In some embodiments, the mold layer 25′ is vertically sandwiched (e.g., in the Z direction) between the redistribution structure 104 and the carrier substrate 124. In some embodiments, the mold layers 25 and 25′ include the same base material, but include different kinds of carbon particles.
[0082] Figure 4 A schematic top view of a package structure 200 in accordance with some embodiments is shown. In accordance with some embodiments, package structure 200 can be similar to previously described package structures 100 and 100', except that the size of the semiconductor die is different from those in package structures 100 and 100'. Processes and materials used to form package structure 200 can be similar to or the same as those previously described for forming package structures 100 and 100', and are not repeated here.
[0083] like Figure 4 As shown in , according to some embodiments, package structure 200 includes package components 10 and 20 and semiconductor die 40, but semiconductor die 30 is replaced by semiconductor die 30a and 30b. More specifically, according to some embodiments, each of semiconductor die 30a and 30b is configured to connect electrical signals between one of package components 10 and one of package components 20. The functions and formations of semiconductor die 30a and 30b may be the same as those of semiconductor die 30, and therefore are not repeated here.
[0084] Similar to package structure 100, in package structure 200, package components 10 and 20 are sealed (eg, surrounded) by mold layer 25 according to some embodiments. In some embodiments, semiconductor dies 30a, 30b, and 40 are sealed (eg, surrounded) by mold layer 25', similar to Figure 3B Thus, the heat generated by the package components 10 and 20 and the semiconductor dies 30a, 30b, and 40 during operation can be dissipated through the molding layers 25 and 25', and the temperature of the device can be reduced. The cross-sectional view of the package structure 200 can be similar to Figure 2M and Figure 3B The package structures 100 and 100 ′ shown in FIG. 1 are identical to those of FIG. 1 , and thus the details of the structures will not be repeated here.
[0085] Figure 5A A schematic top view of a package structure 300 is shown in accordance with some embodiments. Figure 5B According to some embodiments, Figure 5A Line X 5A -X5A ' is a cross-sectional view of package structure 300 shown in FIG. According to some embodiments, package structure 300 may be similar to previously described package structure 100, except that semiconductor die 50 is provided together with semiconductor dies 30 and 40. Processes and materials used to form package structure 300 may be similar to or the same as those previously described for forming package structure 100, and are not repeated here.
[0086] like Figure 5A As shown in , according to some embodiments, package structure 300 includes package components 10 and 20 and semiconductor dies 30 and 40, and an additional semiconductor die 50 is also disposed (e.g., bonded) to redistribution structure 108. Semiconductor die 50 may be configured to control power of package component 10. More specifically, according to some embodiments, semiconductor dies 30, 40, and 50 are disposed over carrier substrate 102, and implemented Figures 2C to 2M The process shown in FIG. 3 is used to form a package structure 300, as shown in FIG. Figure 5B In some embodiments, each of the semiconductor dies 50 overlaps a portion of the package components 10. Similar to the package structure 100, according to some embodiments, the package components 10 and 20 are sealed (e.g., surrounded) by the molding layer 25 so that the heat generated by the package components 10 and 20 can be dissipated faster.
[0087] Figure 5C A cross-sectional view of a package structure 300' according to some embodiments is shown. According to some embodiments, package structure 300' may be similar to previously described package structure 300, except that encapsulant 106 is replaced by molding layer 25'. Processes and materials used to form package structure 300' may be similar to or the same as those previously described for forming package structure 300, and are not repeated here.
[0088] Similar to package structure 300, according to some embodiments, package components 10 and 20 are sealed (eg, surrounded) by mold layer 25. In some embodiments, semiconductor dies 30, 40, and 50 are sealed (eg, surrounded) by mold layer 25', similar to Figure 3B Thus, the heat generated by the package components 10 and 20 during operation can be dissipated through the mold layer 25, and the heat generated by the semiconductor dies 30, 40, and 50 during operation can be dissipated through the mold layer 25', and the temperature of the device can be reduced. The layout of the package structure 300' can be similar to Figure 5A The package structure 300 is identical to those shown in FIG. 3 , and therefore the details of the layout are not repeated here.
[0089] Figure 6 A schematic top view of a package structure 400 according to some embodiments is shown. According to some embodiments, package structure 400 can be similar to previously described package structure 200, except that semiconductor die 50 is also provided. Processes and materials used to form package structure 400 can be similar to or the same as those previously described for forming package structures 100, 200, and 300, and are not repeated here.
[0090] like Figure 6 As shown in , according to some embodiments, package structure 400 includes package components 10 and 20 and semiconductor die 30a, 30b, 40 and 50. Similar to package structure 100, according to some embodiments, in package structure 400, package components 10 and 20 are sealed (e.g., surrounded) by mold layer 25. In some embodiments, semiconductor die 30a, 30b, 40 and 50 are sealed (e.g., surrounded) by mold layer 25'. Therefore, heat generated by package components 10 and 20 and semiconductor die 30a, 30b, 40 and 50 during operation can be dissipated by mold layers 25 and 25', and the temperature of the device can be reduced. A cross-sectional view of package structure 400 can be similar to Figure 5B and Figure 5C The package structures 300 and 300 ′ shown in FIG. 1 are identical to those of FIG. 5 , and thus the details of the structures will not be repeated here.
[0091] Fig. 7A and Figure 7B A schematic top view of a package structure 100A in accordance with some embodiments is shown. In accordance with some embodiments, package structure 100A can be similar to previously described package structure 100, except that dummy die 15 is also attached to redistribution structure 108. Processes and materials used to form package structure 100A can be similar to or the same as those previously described for forming package structure 100, and are not repeated here.
[0092] More specifically, Fig. 7A The layout of the package components 10 and 20 and the dummy die 15 in the package structure 100A according to some embodiments is shown. As previously described, the package component 10 can be an HBM die and can be a hot spot of the device during operation. Therefore, the dummy die 15 can be applied to the package structure 100A to further assist in heat dissipation. In addition, according to some embodiments, the package components 10 and 20 and the dummy die 15 are also sealed (e.g., surrounded) by the molding layer 25. The dummy die 15 and the molding layer 25 can assist in heat dissipation.
[0093] In some embodiments, the space between the package components 10 and 20 and the dummy die 15 in the X direction and the Y direction is filled with a molding layer 25. In addition, according to some embodiments, because the dummy die 15 is used for heat dissipation, the dummy die 15 has no active and / or passive devices. In some embodiments, the dummy die 15 is spaced apart from the package component 10 in the Y direction. In some embodiments, the dummy die 15 is sandwiched between the two package components 10 in the Y direction, so that the heat dissipation between the package components 10 can be further improved. In some embodiments, the sidewall surfaces of the package component 10 and the dummy die 15 are substantially aligned with each other.
[0094] In some embodiments, the dummy die 15 is spaced apart from the package component 20 in the X direction. In some embodiments, the molding layer 25 is laterally interposed between the dummy die 15 and the package component 20 in the X direction. In some embodiments, the molding layer 25 is laterally interposed between the dummy die 15 and the package component 10 in the Y direction.
[0095] Figure 7B The layout of semiconductor dies 30 and 40 in the package structure 100A according to some embodiments is further shown. In some embodiments, each of the semiconductor dies 30 overlaps vertically with two package components 10, one package component 20, and one dummy die 15. That is, in the top view, according to some embodiments, the projection area of each of the semiconductor dies 30 overlaps with two package components 10, one package component 20, and one dummy die 15. In some embodiments, the package component 10 and the dummy die 15 are substantially aligned in the Y direction. In some embodiments, the sidewalls of the package component 10 and the dummy die 15 are substantially aligned in the Y direction. In some embodiments, the width of the package component 10 is substantially equal to the width of the dummy die 15 in the X direction. In some embodiments, the width of the package component 10 is greater than the width of the dummy die 15 in the Y direction. In some embodiments, the width of the package component 20 is greater than the width of the dummy die 15 in both the X direction and the Y direction.
[0096] Fig. 8A and Figure 8B FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a package structure 100A according to some embodiments. More specifically, according to some embodiments, Figure 7B Line X 7A -X 7A More specifically, according to some embodiments, the implementation FIG. 2A to FIG. 2E The process shown in FIG. 1 and the package components 10 and 20 and the dummy die 15 are bonded to the redistribution structure 108, as shown in FIG. Fig. 8A. Similar to package assemblies 10 and 20, according to some embodiments, dummy die 15 is bonded to redistribution structure 108 by bonding conductive pads 114 and 118 through conductive connectors 116. In some embodiments, dummy die 15 is bonded to redistribution structure 108 after bonding package assemblies 10 and 20. In some other embodiments, dummy die 15 is bonded to redistribution structure 108 through an adhesive layer. In some other embodiments, dummy die 15 is bonded to redistribution structure 108 through dielectric-to-dielectric and metal-to-metal bonding. In some embodiments, dummy die 15 and semiconductor dies 30 and 40 are located at opposite sides of redistribution structure 108.
[0097] As described above, rather than being used as an electrical device, dummy die 15 can help dissipate heat generated from package assembly 10. Therefore, according to some embodiments, dummy die 25 has no active and / or passive devices. In addition, according to some embodiments, dummy die 25 is electrically isolated from package assemblies 10 and 20, redistribution layer 112 in redistribution structure 108, insulating vias 104, and semiconductor dies 30 and 40. In some embodiments, dummy die 15 includes one or more materials having relatively high thermal conductivity. In some embodiments, dummy die 15 is made of materials such as silicon (e.g., bulk silicon), silicon oxide, silicon carbide, aluminum nitride, ceramic materials, etc., or combinations thereof.
[0098] According to some embodiments, after the package components 10 and 20 and the dummy die 15 are bonded to the redistribution structure 108 , performing Figure 2G to Figure 2M The process shown in FIG. 1 is used to form a package structure 100A. Figure 8B Similar to package assembly 10 , underfill 120 is formed around a lower portion of dummy die 15 over redistribution structure 108 , and molding layer 25 is formed over underfill 120 and around an upper portion of dummy die 15 , in accordance with some embodiments.
[0099] In some embodiments, the bottom filler 120 is in direct contact with the bottom surface and lower portions of the sidewall surfaces of the dummy die 15, and the mold layer 25 is in direct contact with upper portions of the sidewall surfaces of the dummy die 15. Because the dummy die 15 can also contribute to heat dissipation, the heat generated by the package assembly 10 during operation can be dissipated by the mold layer 25 and the dummy die 15, and the temperature of the resulting device can be reduced. Figure 2M The cross-sectional views shown in FIG. 1 are the same and will not be repeated here.
[0100] Fig. 9A cross-sectional view of a package structure 100A' according to some embodiments is shown. According to some embodiments, package structure 100A' can be similar to previously described package structure 100A, except that encapsulant 106 is replaced by molding layer 25'. Processes and materials used to form package structure 100A' can be similar to or the same as those previously described for forming package structures 100 and 100A, and are not repeated here.
[0101] Similar to package structure 100A, according to some embodiments, package components 10 and 20 and dummy die 15 are sealed (e.g., surrounded) by mold layer 25. In some embodiments, semiconductor die 30 and 40 are sealed (e.g., surrounded) by mold layer 25'. Therefore, heat generated by semiconductor die 30 and 40 during operation can be dissipated by mold layer 25', and the temperature of the device can be reduced. The layout of package structure 100A' can be similar to Fig. 7A and Figure 7B The package structure 100A shown in FIG. 1 is the same as that shown in FIG. 1 , and therefore the details of the structure are not repeated here. Figure 3B The cross-sectional views shown in FIG. 1 are the same and will not be repeated here.
[0102] Fig.10 1 shows a layout of a package structure 100B according to some embodiments. According to some embodiments, the package structure 100B can be similar to the package structure 100A described previously, except that the dummy dies 15 ′ and 15 ″ have the same Fig. 7A and Figure 7B The dummy die 15 shown in FIG. 1 is of different sizes. The processes and materials used to form package structure 100B may be similar to or the same as those previously described for forming package structures 100 and 100A, and are not repeated here.
[0103] More specifically, according to some embodiments, the package components 10 and 20 and the dummy dies 15' and 15" are sealed (e.g., surrounded) by a molding layer 25. In some embodiments, the spaces between the package components 10 and 20 and the dummy dies 15' and 15" in the X and Y directions are filled with a molding layer 25. In some embodiments, the width of the dummy die 15' is smaller than the width of the package component 10 in both the X and Y directions. In some embodiments, the width of the dummy die 15' is smaller than the width of the package component 20 in both the X and Y directions. In some embodiments, the width of the dummy die 15" is greater than the width of the package component 10 in the X direction. In some embodiments, the width of the dummy die 15' is different from the width of the dummy die 15". The materials and functions of the dummy dies 15' and 15" may be similar to or the same as those of the previously described dummy die 15, and are not repeated here. In addition, a cross-sectional view of the package structure 100B may be similar to that of the package component 10. Figure 2M , Figure 3B , Figure 8B and Fig. 9 The same as those shown in , and therefore are not repeated here.
[0104] Fig.11A A schematic top view of a package structure 200A is shown in accordance with some embodiments. Fig. 11B According to some embodiments, Fig.11A Line X 11A -X 11A ' is a cross-sectional view of package structure 200A shown in FIG. According to some embodiments, package structure 200A may be similar to package structure 200 described previously, except that dummy die 15 is provided together with package components 10 and 20. Processes and materials used to form package structure 200A may be similar to or the same as those previously described for forming package structure 200, and are not repeated here.
[0105] Similar to the previously described package structure 100A, according to some embodiments, the package components 10 and 20 and the dummy die 15 are sealed (eg, surrounded) by a molding layer 25, such as Fig.11A and Fig. 11B In some embodiments, in the top view, semiconductor dies 30a and 30b overlap package components 10 and 20, but do not overlap dummy die 15. The cross-sectional view at package component 10 is similar to Figure 2M The cross-sectional views shown in FIG. 1 are the same and will not be repeated here.
[0106] Fig. 11C2 shows a cross-sectional view of a package structure 200A′ according to some embodiments. According to some embodiments, package structure 200A′ can be similar to package structure 200A described previously, except that encapsulant 106 is replaced by molding layer 25′. Processes and materials used to form package structure 200A′ can be similar to or the same as those previously described for forming package structure 200A, and are not repeated here. The layout of package structure 200A′ can be similar to that of package structure 200A. Fig.11A The package structure 200A shown in FIG. 1 is the same as that of FIG. 1 , and therefore the details of the layout are not repeated here. Figure 3B The cross-sectional views shown in FIG. 1 are the same and will not be repeated here.
[0107] Fig.12 2 shows a layout of a package structure 200B according to some embodiments. According to some embodiments, the package structure 200B can be similar to the package structure 200A described previously, except that the dummy die 15 ′ and 15 ″ have the same Fig.11A The dummy die 15 shown in FIG. 2 is a different size. The processes and materials used to form the package structure 200B may be similar to or the same as those previously described for forming the package structures 200 and 200A, and are not repeated here. The cross-sectional view of the package structure 200B may be similar to that of FIG. Figure 2M , Figure 3B , Fig. 11B and Fig. 11C The same as those shown in , and therefore are not repeated here.
[0108] Fig.13 1 shows a schematic top view of a package structure 300A according to some embodiments. According to some embodiments, package structure 300A can be similar to package structure 300 described previously, except that dummy die 15 is provided with package components 10 and 20. Processes and materials used to form package structure 300A can be similar to or the same as those previously described for forming package structure 300, and are not repeated here. In addition, a cross-sectional view of package structure 300A can be similar to that of package structure 300 described previously. Figure 2M , Figure 3B , Figure 8B and Fig. 9 The same as those shown in , and therefore are not repeated here.
[0109] Fig.141 shows a layout of a package structure 300B according to some embodiments. According to some embodiments, the package structure 300B can be similar to the package structure 300A described previously, except that the dummy die 15 ′ and 15 ″ have the same Fig.13 The dummy die 15 shown in FIG. 3 is of a different size. The processes and materials used to form package structure 300B may be similar to or the same as those previously described for forming package structures 300 and 300A, and are not repeated here. The cross-sectional view of package structure 300B may be similar to that of FIG. Figure 2M , Figure 3B , Figure 8B and Fig. 9 The same as those shown in , and therefore are not repeated here.
[0110] Fig.15 4 shows a schematic top view of a package structure 400A according to some embodiments. According to some embodiments, package structure 400A can be similar to package structure 400 described previously, except that dummy die 15 is provided with package components 10 and 20. Processes and materials used to form package structure 400A can be similar to or the same as those previously described for forming package structure 400, and are not repeated here. In addition, a cross-sectional view of package structure 400A can be similar to that of package structure 400 described previously. Figure 2M , Figure 3B , Fig. 11B and Fig. 11C The same as those shown in , and therefore are not repeated here.
[0111] Fig.16 4 shows a layout of a package structure 400B according to some embodiments. According to some embodiments, the package structure 400B can be similar to the package structure 400A described previously, except that the dummy die 15 ′ and 15 ″ have the same Fig.15 The dummy die 15 shown in FIG. 4 is of a different size. The processes and materials used to form package structure 400B may be similar to or the same as those previously described for forming package structures 400 and 400A, and are not repeated here. The cross-sectional view of package structure 400B may be similar to that of FIG. Figure 2M , Figure 3B , Fig. 11B and Fig. 11C The same as those shown in , and therefore are not repeated here.
[0112] As previously described, the package components 10 and 20 may generate heat during operation. For example, the package component 10 may be an HBM die, and the area of the HBM die may be considered a hot spot of the package structure. Therefore, in some embodiments, a mold layer 25 having a relatively high thermal conductivity is formed around the package components 10 and 20, thereby improving heat dissipation and reducing the temperature around the package component 10 (e.g., about 12°C) during operation. In addition, according to some embodiments, the dummy die 15, 15', 15" is bonded to the redistribution structure 108 between the package components 10, thereby further reducing the temperature around the package component 10. In addition, the mold layer 25' is also formed around the semiconductor die 30, 30a, 30b, 40 and 50, so that the heat generated by the semiconductor die can also be diffused faster. Therefore, the temperature of the package structure, especially the temperature at the hot spots around the package component 10, can be reduced, and thus the performance of the package structure can be improved.
[0113] It should be understood that the components shown in the package structures 100, 100', 200, 300, 300', 400, 100A, 100A', 100B, 200A, 200A', 200B, 300A, 300B, 400A and 400B may be combined and / or exchanged. In addition, it should be noted that Figures 1A to 16 The same elements in the present invention may be represented by the same reference numerals, may include the same or similar materials, and may be formed by the same or similar processes; therefore, such redundant details are omitted for the sake of brevity. Figures 1A to 16 It is described in terms of methods, but it should be understood that Figures 1A to 16 The structure disclosed in is not limited to the method, but can exist independently as a structure independent of the method. Similarly, Figures 1A to 16 The methods shown in are not limited to the disclosed structures but can exist independently of the structures.
[0114] In addition, although disclosed method is shown and described as a series of steps or events above, it should be understood that in some other embodiments, the shown order of such steps or events can be changed. For example, some steps can occur in different orders and / or with other steps or events except those shown and / or described above. In addition, not all steps shown are necessary for implementing one or more aspects or embodiments described above. In addition, one or more of the steps described above can be performed as one or more independent steps and / or stages.
[0115] Embodiments of a package structure may be provided. The package structure may include a package component and a semiconductor die disposed at opposite sides of a redistribution structure. In addition, a mold layer having a relatively high thermal conductivity is formed around the package component. The mold layer may include a filler having a high thermal conductivity. The mold layer may help dissipate the heat generated by the package component, and thus may reduce the temperature of the package structure during operation.
[0116] A packaging structure is provided. The packaging structure includes: a redistribution structure; and a first packaging component and a second packaging component attached to the redistribution structure in a first direction and spaced apart from each other in a second direction. The packaging structure also includes: a bottom filler formed around lower portions of the first packaging component and the second packaging component above the redistribution structure; and a molding layer formed above the bottom filler and around upper portions of the first packaging component and the second packaging component. In addition, the molding layer includes a base material and a filler embedded in the base material. In addition, the thermal conductivity of the filler is greater than about 400 W / mK.
[0117] A packaging structure is provided. The packaging structure includes: a first redistribution structure; and a first packaging component and a second packaging component, which are attached to a first side of the first redistribution structure and are spaced apart from each other in a first direction. The packaging structure also includes: an underfill formed around the first packaging component and the second packaging component; and a first mold layer formed above the underfill and above the first side of the first redistribution structure. In addition, the first mold layer includes first carbon particles, and the thermal conductivity of the first mold layer is greater than the thermal conductivity of the underfill. The packaging structure also includes: a first semiconductor die, which is attached to a second side of the first redistribution structure, and in a top view, the first semiconductor die has a first projection area that partially overlaps with the first packaging component and the second packaging component.
[0118] A method for forming a package structure is provided. The method includes: forming a redistribution structure; and arranging a first package component and a second package component above the redistribution structure. In addition, the first package component is spaced apart from the second package component by a first spacer. The method also includes: forming a bottom filler around the first package component and the second package component and in a lower area of the first spacer; and forming a first mold layer covering the first package component, the second package component and the bottom filler. In addition, the first mold layer includes first carbon particles. The method also includes: partially removing the first mold layer until the top surfaces of the first package component and the second package component are exposed and the upper area of the first spacer is filled with the first mold layer.
[0119] Some embodiments of the present application provide a packaging structure including: a redistribution structure; a first packaging component and a second packaging component attached to a first side of the redistribution structure; a bottom filler located above the redistribution structure around a lower portion of the first packaging component and the second packaging component; and a molding layer formed above the bottom filler and around an upper portion of the first packaging component and the second packaging component, wherein the molding layer includes: a base material; and a filler embedded in the base material, wherein a thermal conductivity of the filler is greater than approximately 400 W / mK.
[0120] In some embodiments, the molding layer has a first portion located between the upper portions of the first and second packaging components, the bottom filler has a second portion located between the lower portions of the first and second packaging components, and the thickness of the first portion of the molding layer is greater than the thickness of the second portion of the bottom filler. In some embodiments, the packaging structure further includes: a dummy die attached to the first side of the redistribution structure and spaced apart from the first packaging component, wherein the molding layer extends between the dummy die and the first packaging component. In some embodiments, the molding layer extends between the dummy die and the second packaging component. In some embodiments, the packaging structure further includes: a third packaging component attached to the first side of the redistribution structure, wherein sidewall surfaces of the first packaging component, the dummy die, and the third packaging component are substantially aligned with each other. In some embodiments, the filler includes graphite, graphene, or diamond-like carbon. In some embodiments, the concentration of the filler in the molding layer is in a range between 20wt% and 80wt%.
[0121] Other embodiments of the present application provide a packaging structure including: a first redistribution structure; a first packaging component and a second packaging component attached to a first side of the first redistribution structure and spaced apart from each other; a bottom filler located around the first packaging component and the second packaging component; a first molding layer located above the bottom filler and above the first side of the first redistribution structure, wherein the first molding layer includes first carbon particles, wherein the thermal conductivity of the first molding layer is greater than the thermal conductivity of the bottom filler; and a first semiconductor die attached to a second side of the first redistribution structure, wherein, in a top view, the first semiconductor die partially overlaps with the first packaging component and the second packaging component.
[0122] In some embodiments, the first carbon particles are graphite or diamond-like carbon. In some embodiments, the package structure further comprises a second redistribution structure attached to the first semiconductor die; and a second molding layer located around the first semiconductor die, wherein the second molding layer comprises second carbon particles. In some embodiments, the first carbon particles are different from the second carbon particles. In some embodiments, the package structure further comprises: a dummy die attached to the first side of the first redistribution structure; and a third package component attached to the first side of the first redistribution structure, wherein the first molding layer contacts the dummy die and the third package component. In some embodiments, in the top view, the first semiconductor die partially overlaps the dummy die. In some embodiments, in the top view, the first semiconductor die partially overlaps the third package component. In some embodiments, the first package component has a first sidewall surface facing the second package component in the first direction, wherein a contact height between the first sidewall surface and the first molding layer is greater than a contact height between the first sidewall surface and the bottom filler.
[0123] Some other embodiments of the present application provide a method for forming a packaging structure, comprising: forming a redistribution structure; disposing a first packaging component and a second packaging component above the redistribution structure, wherein the first packaging component is separated from the second packaging component by a first spacer; forming a bottom filler around the first packaging component and the second packaging component and in a lower area of the first spacer; forming a first molding layer above the first packaging component, the second packaging component and the bottom filler, wherein the first molding layer includes first carbon particles; and partially removing the first molding layer to expose the top surfaces of the first packaging component and the second packaging component, wherein the upper area of the first spacer is filled with the first molding layer.
[0124] In some embodiments, the first mold layer includes the first carbon particles in a base material, wherein the concentration of the filler in the mold layer is in a range between 20wt% and 80wt%. In some embodiments, the method further includes: disposing a first semiconductor die above a carrier substrate; and forming a second mold layer around the first semiconductor die, wherein the second mold layer includes second carbon particles, wherein forming the redistribution structure includes forming the redistribution structure above the first semiconductor die and the second mold layer. In some embodiments, the first mold layer and the second mold layer include the same base material, and the first carbon particles are different from the second carbon particles. In some embodiments, the first mold layer and the second mold layer are located on opposite sides of the redistribution structure, and the first semiconductor die vertically overlaps the first package component and the second package component.
[0125] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.
Claims
1. A packaging structure, comprising: Redistribution structure; a first package component and a second package component attached to a first side of the redistribution structure; a bottom filler over the redistribution structure around lower portions of the first package component and the second package component; as well as A molding layer formed over the underfill and around upper portions of the first package component and the second package component, wherein the molding layer comprises: Base material; and A filler is embedded in the base material, wherein the thermal conductivity of the filler is greater than 400 W / mK.
2. The packaging structure according to claim 1, wherein: The molding layer has a first portion located between the upper portions of the first packaging component and the second packaging component, the bottom filler has a second portion located between the lower portions of the first packaging component and the second packaging component, and a thickness of the first portion of the molding layer is greater than a thickness of the second portion of the bottom filler.
3. The packaging structure according to claim 1, further comprising: A dummy die is attached to the first side of the redistribution structure and is spaced apart from the first package component, wherein the molding layer extends between the dummy die and the first package component.
4. The packaging structure according to claim 3, wherein: The molding layer extends between the dummy die and the second package component.
5. The packaging structure according to claim 3, further comprising: A third package component is attached to the first side of the redistribution structure, wherein sidewall surfaces of the first package component, the dummy die, and the third package component are substantially aligned with each other.
6. The packaging structure according to claim 1, wherein: The filler includes graphite, graphene or diamond-like carbon.
7. The packaging structure according to claim 1, wherein: The concentration of the filler in the molding layer ranges between 20 wt % and 80 wt %.
8. A packaging structure, comprising: First redistribution structure; a first package component and a second package component attached to a first side of the first redistribution structure and spaced apart from each other; A bottom filler is disposed around the first packaging component and the second packaging component; a first molding layer over the underfill and over the first side of the first redistribution structure, wherein the first molding layer comprises first carbon particles, wherein a thermal conductivity of the first molding layer is greater than a thermal conductivity of the underfill; and A first semiconductor die is attached to a second side of the first redistribution structure, wherein the first semiconductor die partially overlaps the first package assembly and the second package assembly in a top view.
9. The packaging structure according to claim 8, wherein: The first carbon particles are graphite or diamond-like carbon.
10. A method for forming a package structure, comprising: forming a redistribution structure; Disposing a first package component and a second package component over the redistribution structure, wherein the first package component is spaced apart from the second package component by a first spacer; forming an underfill around the first package component and the second package component and in a lower region of the first spacer; forming a first molding layer over the first packaging component, the second packaging component, and the underfill, wherein the first molding layer includes first carbon particles; and The first mold layer is partially removed to expose top surfaces of the first package component and the second package component, wherein an upper region of the first space is filled with the first mold layer.
Citation Information
Cited By
Semiconductor package structure, fabricating method thereof, and memory system
US20240304509A1