Semiconductor test structure and test method thereof

Abstract

The invention provides a semiconductor test structure and a test method thereof. The semiconductor test structure comprises a plurality of basic test units, and each basic test unit comprises a substrate which is provided with a first active region and a second active region which are defined through an isolation structure and are arranged at intervals along a first direction; the two polycrystalline silicon structures are formed on the surface of the substrate, extend in the first direction and are arranged at intervals in the second direction, the orthographic projection of each polycrystalline silicon structure on the substrate is partially overlapped with the first active region and the second active region, a first interval is formed between the two polycrystalline silicon structures in the second direction, an included angle is formed between the first direction and the second direction, and the two polycrystalline silicon structures are parallel to the surface of the substrate; the dielectric layer covers the first active region and the second active region and is filled between the two polycrystalline silicon structures; the first contact structure and the second contact structure penetrate through the dielectric layer, are in contact with the first active region and the second active region and are positioned between the two polycrystalline silicon structures; whether holes are formed in the dielectric layer filled between the two polycrystalline silicon structures or not is judged by measuring leakage current of the first contact structure and the second contact structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor test structure and a test method thereof. Background Art

[0002] In the field of semiconductor technology, as the process node decreases, for example, the polysilicon pitch of the 90nm to 65nm node process decreases from 140nm to 120nm, based on the polysilicon minimum spacing design rule (Poly Space Minimum DR), the reduction in spacing may cause voids to be generated in the chemical vapor deposition (CVD) insulating layer deposition (ILD)11, such as Figure 1 As shown. The main reason why holes are produced in the deposition of the insulating layer is that the deposition has certain requirements for the step coverage. Step coverage is an important parameter to measure the deposition quality. If there are faults or uneven areas on the surface of the wafer, it is impossible to form a film with uniform thickness. Step coverage is an indicator of the thickness loss at the step when the film layer crosses the step, that is, the ratio of the thickness of the film layer at the step to the thickness of the film layer at the flat part. The closer the step coverage is to 1, the less the difference between the film layer thickness at the step (bottom or sidewall) and the film layer at the flat part. The farther away from 1 (that is, the smaller it is than 1), the thinner the film layer thickness at the step is compared with the film layer thickness at the flat part. The bottom thickness of the insulating layer deposition is a, the plane thickness is b, and the sidewall thickness is c. The sidewall step coverage of the insulating layer deposition is c / b, and the bottom step coverage is a / b.

[0003] like Figure 2-Figure 3 As shown, the existence of Void will lead to two situations: (1) Figure 2 As shown in FIG. 1 , the presence of the hole may cause a contact structure bridge 22 (CT Bridge) to be formed between two contact structures 21 at different positions, thereby causing a short circuit in the entire product; (2) as Figure 3 As shown, the silicide (SAB) wet over-etching causes a hole 31 to be generated in the shallow trench isolation (STI) 32 , increasing the risk of the shallow trench isolation 32 being broken down.

[0004] Therefore, how to avoid the generation of holes in the insulating layer or shallow trench isolation and improve the stability of the semiconductor structure is a problem that needs to be solved at present. Summary of the invention

[0005] The technical problem to be solved by the present invention is how to avoid the generation of holes in the insulating layer or shallow trench isolation, and to provide a semiconductor test structure and a test method thereof.

[0006] In order to solve the above problems, the present invention provides a semiconductor test structure, including a plurality of basic test units, wherein the basic test unit includes: a substrate, wherein a first active area and a second active area are defined by an isolation structure in the substrate, wherein the first active area and the second active area are arranged at intervals along a first direction, and the first direction is parallel to the surface of the substrate; two polysilicon structures, formed on the surface of the substrate, wherein the two polysilicon structures extend along the first direction and are arranged at intervals along a second direction, wherein the orthographic projection of each polysilicon structure on the substrate partially overlaps with the first active area and the second active area, and in the second direction, there is a gap between the two polysilicon structures. a first spacing, wherein the second direction is parallel to the substrate surface, and the second direction forms an angle with the first direction; a dielectric layer, covering the first active area and the second active area, and filling between the two polysilicon structures; a first contact structure, penetrating the dielectric layer and contacting the first active area, and located between the two polysilicon structures; a second contact structure, penetrating the dielectric layer and contacting the second active area, and located between the two polysilicon structures; the semiconductor test structure determines whether a hole is generated in the dielectric layer filled between the two polysilicon structures by measuring the leakage current of the first contact structure and the second contact structure.

[0007] In order to solve the above problem, the present invention provides a semiconductor testing method, comprising the following steps: providing a plurality of basic test units, wherein the basic test units adopt the basic test units as described in claim 2; measuring the leakage current of the first contact structure and the second contact structure in the plurality of the basic test units; and counting the first spacing corresponding to the basic test units whose leakage current meets the process requirements to obtain the process window parameters of the first spacing.

[0008] The above technical solution tests the leakage current of the first contact structure and the second contact structure at different spacings by setting polysilicon structures with different first spacings, so as to monitor the generation of insulating layer holes and contact structure bridges in the insulating layer holes at different spacings, and then obtain the process window of the first spacing to improve the insulating layer deposition process and improve the stability of the semiconductor structure. The problem of contact structure bridges caused by holes is detected by electrical testing, and there is no need to monitor the trench filling (Gap Fill) process problem through destructive testing such as slicing.

[0009] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following is a brief introduction to the drawings required for the description of the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic diagram of the structure of holes generated by insulating layer deposition in the prior art.

[0012] Figure 2 It is a schematic diagram of the structure of the contact structure bridge caused by the hole in the prior art.

[0013] Figure 3 A schematic diagram of the structure of holes generated by shallow trench isolation in the prior art.

[0014] Figure 4A It is a structural schematic diagram of an embodiment of a basic test unit of the semiconductor test structure of the present invention.

[0015] Figure 4B for Figure 4A Cross-sectional view along AA' direction.

[0016] Figure 4C for Figure 4A Cross-sectional view along BB' direction.

[0017] Figure 5 It is a structural schematic diagram of another embodiment of the basic test unit of the semiconductor test structure of the present invention.

[0018] Figure 6 It is a structural schematic diagram of an embodiment of a combined test unit of the semiconductor test structure of the present invention.

[0019] Figure 7 FIG. 4 is an equivalent circuit diagram of an embodiment of a combined test unit of the semiconductor test structure of the present invention.

[0020] Figure 8 This is a flowchart of the steps of the first embodiment of the semiconductor testing method of the present invention.

[0021] Fig. 9 This is a flow chart of the steps of the second embodiment of the semiconductor testing method of the present invention.

[0022] Fig.10 This is a flowchart of the steps of the third embodiment of the semiconductor testing method of the present invention. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0024] In order to improve the insulating layer deposition process and enhance the stability of the semiconductor structure, the present invention designs a test structure for the polysilicon spacing, thereby affecting the chemical vapor deposition step coverage to produce insulating layer holes or shallow trench isolation holes, and tests the generation of contact structure bridges or shallow trench isolation breakdown at different spacings to monitor the impact of holes and design process windows.

[0025] See also Figure 4A to Figure 4C ,in, Figure 4A is a structural schematic diagram of an embodiment of a basic test unit of the semiconductor test structure of the present invention, Figure 4B for Figure 4A The cross-sectional view along the AA' direction is shown in Fig. Figure 4C for Figure 4A The cross-sectional view along the BB' direction is shown in FIG. 1 , where, in order to more clearly illustrate the film structure, Figure 4A The dielectric layer is not shown in the figure. The semiconductor test structure includes a plurality of basic test units, such as Figure 4A to Figure 4CAs shown, the basic test unit includes: a substrate 40, a polysilicon structure 41, a first contact structure 421, a second contact structure 422, and a dielectric layer 43. The first active area 401 and the second active area 402 are defined by an isolation structure 403 in the substrate 40. The first active area 401 and the second active area 402 are arranged at intervals along a first direction D1, and the first direction D1 is parallel to the surface of the substrate 40. A straight line and a plane have no common point (do not intersect), which is called a straight line and a plane are parallel. The first direction D1 is an arbitrary direction parallel to the surface of the substrate 40. The polysilicon structure 41 is formed on the surface of the substrate 40. The two polysilicon structures 41 extend along the first direction D1 and are arranged along the second direction D2. The orthographic projection of each polysilicon structure 41 on the substrate 40 partially overlaps with the first active area 401 and the second active area 402. In the second direction D2, there is a first spacing X1 between the two polysilicon structures 41, wherein the second direction D2 is parallel to the surface of the substrate 40, and the second direction D2 forms an angle with the first direction D1. The second direction D2 is any direction parallel to the surface of the substrate 40 and not parallel to the first direction D1. The dielectric layer 43 covers the first active area 401 and the second active area 402, and fills between the two polysilicon structures 41. The first contact structure 421 penetrates the dielectric layer 43 and contacts the first active area 401, and is located between the two polysilicon structures 41. The second contact structure 422 penetrates the dielectric layer 43 and contacts the second active region 402, and is located between the two polysilicon structures 41. The semiconductor test structure determines whether a hole is generated in the dielectric layer 43 filled between the two polysilicon structures 41 by measuring the leakage current of the first contact structure 421 and the second contact structure 422.

[0026] In some embodiments, the first spacing X1 of the plurality of the basic test units changes gradually, and the process window parameters of the first spacing X1 can be obtained by measuring the leakage current of the first contact structure 421 and the second contact structure 422 in the plurality of the basic test units. The plurality of the first spacing X1 includes a first reference value S1 and a plurality of offset values ​​of the first reference value S1, and the offset range of the offset values ​​of the plurality of the first reference values ​​S1 is -10% to 10%. In this embodiment, the offset values ​​of the plurality of the first reference values ​​S1 are 0.9*S1, 0.95*S1, 1.05*S1, and 1.1*S1, respectively.

[0027] The above technical solution tests the leakage current of the first contact structure and the second contact structure at different spacings by setting polysilicon structures with different first spacings, so as to monitor the generation of insulating layer holes and contact structure bridges in the insulating layer holes at different spacings, and then obtain the process window of the first spacing to improve the insulating layer deposition process and improve the stability of the semiconductor structure. By electrical testing the breakdown of the contact structure bridge caused by the holes, there is no need to monitor the trench filling (Gap Fill) process problem through destructive testing such as slicing.

[0028] See also Figure 5 , which is a structural schematic diagram of another embodiment of the basic test unit of the semiconductor test structure of the present invention, in order to more clearly illustrate the film layer structure, Figure 5 The dielectric layer is not shown. Figure 5 The embodiment shown in the figure is different from the embodiment shown in Figure 4 in that a parameter is selected in the process window parameters of the first spacing X1 as a reference spacing; in the first direction D1, the first active area 401 and the second active area 402 have a second spacing X2; in the second direction D2, a portion of at least one of the polysilicon structures 41 located above the isolation structure 403 also forms a protrusion 410 protruding toward the other polysilicon structure 41, and the protrusion 410 is located on opposite sides of the two polysilicon structures 41, so that the minimum spacing X3 between the two polysilicon structures 41 in the second direction D2 is smaller than the reference spacing.

[0029] In some embodiments, the second spacing X2 of the plurality of basic test units changes gradually, and the process window parameter of the second spacing X2 can be obtained by measuring the leakage current of the first contact structure 421 and the second contact structure 422 in the plurality of basic test units. In this embodiment, the first spacing X1 of the plurality of basic test units is equal, and the minimum spacing X3 of the plurality of basic test units is equal.

[0030] The plurality of second spacings X2 include a second reference value S2 and a plurality of offset values ​​of the second reference value S2, and the offset range of the offset values ​​of the plurality of second reference values ​​S2 is -10% to 10%. In this embodiment, the offset values ​​of the plurality of second reference values ​​S2 are 0.9*S2, 0.95*S2, 1.05*S2, and 1.1*S2, respectively.

[0031] In some embodiments, the minimum spacing X3 of the plurality of basic test units changes gradually, and the process window parameters of the minimum spacing X3 can be obtained by measuring the leakage current of the first contact structure 421 and the second contact structure 422 in the plurality of basic test units. In this embodiment, the first spacing X1 of the plurality of basic test units is equal, and the second spacing X2 of the plurality of basic test units is equal. Under the condition that the first spacing X1 does not cause holes in the insulating layer, it is tested whether the minimum spacing X3 at the isolation structure 403 will cause holes in the isolation structure 403, resulting in reduced isolation of the isolation structure 403. By obtaining the process window parameters of the minimum spacing X3, the situation in which holes are generated in the isolation structure 403 and the isolation structure 403 is broken down can be monitored.

[0032] The plurality of minimum spacings X3 include a third reference value S3 and a plurality of offset values ​​of the third reference value S3, and the offset range of the offset values ​​of the third reference value S3 is -10% to 10%. In this embodiment, the offset values ​​of the third reference value S3 are 0.9*S3, 0.95*S3, 1.05*S3, and 1.1*S3, respectively.

[0033] See also Figure 6-7 ,in, Figure 6 is a structural schematic diagram of an embodiment of a combined test unit of a semiconductor test structure according to the present invention, Figure 7 The equivalent circuit diagram of one embodiment of the combination test unit of the semiconductor test structure of the present invention. In order to increase the statistics, the semiconductor test structure of the present invention further includes a plurality of combination test units, and the combination test unit includes a plurality of basic test units 61 connected in series, and the second contact structure 422 of the previous basic test unit 61 of two adjacent basic test units 61 is electrically connected to the first contact structure 421 of the next basic test unit 61. Among them, the arrangement direction of the basic test unit 61 in the combination test unit is not limited, and the plurality of basic test units 61 can be connected end to end to form a series structure. In this embodiment, the basic test unit 61 adopts the following Figure 5 The embodiment shown. Wherein, Figure 6-7 The number and arrangement of the basic test units described are for illustration only and can be adjusted according to the required test accuracy.

[0034] In some embodiments, the first contact structure 421 of the first basic test unit 610 of the combined test unit is connected to the first pad 621, and the second contact structure 422 of the basic test unit 619 at the end of the combined test unit is connected to the second pad 622, and the combined unit is electrically tested by applying pressure to the first pad 621 and the second pad 622. Corresponding to the three test methods of the basic test unit, the combined test unit can also test the second spacing X2 and the minimum spacing X3 respectively.

[0035] In some embodiments, the second spacing X2 changes gradually, the first spacing X1 and the minimum spacing X3 remain unchanged, and the combined unit is electrically tested by applying pressure to the first pad 621 and the second pad 622 to obtain the process window parameters of the second spacing X2.

[0036] In some embodiments, the minimum spacing X3 of the combined test unit changes gradually, the first spacing X1 and the second spacing X2 remain unchanged, and the combined unit is electrically tested by applying pressure to the first pad 621 and the second pad 622 to obtain the process window parameters of the minimum spacing X3. On the basis of ensuring that the first spacing X1 does not cause holes in the insulating layer, the influence of the minimum spacing X3 on the holes in the shallow trench isolation is monitored by testing the minimum spacing X3.

[0037] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor testing method.

[0038] See also Figure 8 , which is a flow chart of the steps of the first embodiment of the semiconductor testing method of the present invention. Figure 8 As shown, the semiconductor testing method includes the following steps: step S81, providing multiple basic test units, and the basic test units adopt the basic test units described in the present invention; step S82, measuring the leakage current of the first contact structure and the second contact structure in the multiple basic test units; step S83, counting the first spacing corresponding to the basic test units whose leakage current meets the process requirements, so as to obtain the process window parameters of the first spacing.

[0039] Please refer to FIG4 and step S81, provide a plurality of basic test units, the basic test units adopt the basic test units of the present invention. In this embodiment, the basic test units adopt the embodiment shown in FIG4, and the first interval X1 of the plurality of basic test units changes gradually.

[0040] Please refer to FIG. 4 and step S82 , measuring the leakage current of the first contact structure 421 and the second contact structure 422 in a plurality of the basic test units.

[0041] Please refer to FIG. 4 and step S83 , the first spacing X1 corresponding to the basic test units whose leakage current meets the process requirement is counted to obtain the process window parameter of the first spacing X1 .

[0042] See also Fig. 9 , which is a flow chart of the steps of the second embodiment of the semiconductor testing method of the present invention. Fig. 9 As shown, in some embodiments, the semiconductor testing method also includes the following steps: step S91, providing multiple basic test units, and the basic test units adopt the basic test units described in the present invention; step S92, measuring the leakage current of the first contact structure and the second contact structure in the multiple basic test units; step S93, counting the second spacing corresponding to the basic test units whose leakage current meets the process requirements, so as to obtain the process window parameters of the second spacing.

[0043] See also Figure 5 And step S91, providing a plurality of basic test units, wherein the basic test units adopt the basic test units described in the present invention. In this embodiment, the basic test units adopt Figure 5 In the embodiment shown, the second interval X2 of the plurality of basic test units changes gradually.

[0044] See also Figure 5 And step S92, measuring the leakage current of the first contact structure 421 and the second contact structure 422 in a plurality of the basic test units.

[0045] See also Figure 5 And step S93, counting the second spacing X2 corresponding to the basic test units whose leakage current meets the process requirement, to obtain the process window parameter of the second spacing X2.

[0046] See also Fig.10 , which is a flow chart of the steps of the third embodiment of the semiconductor testing method of the present invention. Fig.10 As shown, in some embodiments, the semiconductor testing method also includes the following steps: step S101, providing multiple basic test units, and the basic test units adopt the basic test units described in the present invention; step S102, measuring the leakage current of the first contact structure and the second contact structure in the multiple basic test units; step S103, counting the minimum spacing corresponding to the basic test units whose leakage current meets the process requirements, so as to obtain the process window parameters of the minimum spacing.

[0047] See also Figure 5 And step S101, providing a plurality of basic test units, wherein the basic test units adopt the basic test units described in the present invention. In this embodiment, the basic test units adopt Figure 5 In the embodiment shown, the minimum spacing X3 of the plurality of basic test units changes gradually.

[0048] See also Figure 5 And step S102, measuring the leakage current of the first contact structure 421 and the second contact structure 422 in a plurality of the basic test units.

[0049] See also Figure 5 And step S103, counting the minimum spacing X3 corresponding to the basic test unit whose leakage current meets the process requirement, so as to obtain the process window parameter of the minimum spacing X3.

[0050] In other embodiments, it is also possible to use Figure 6 The test method of the combined test unit shown in step S91 to step S93 or step S101 to step S103 is described in detail above and will not be repeated here. Testing by the combined test unit can increase statistics, reduce measurement errors, and make test results more accurate.

[0051] The above technical solution tests the leakage current of the first contact structure and the second contact structure at different spacings to monitor the generation of contact structure bridges or shallow trench isolation breakdown at different spacings, thereby obtaining the process window of spacing to improve the insulating layer deposition process and improve the stability of the semiconductor structure. By electrical testing the contact structure bridge or shallow trench isolation breakdown caused by holes, there is no need to monitor the trench filling (Gap Fill) process problem through destructive testing such as slicing.

[0052] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0053] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0054] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0055] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A semiconductor test structure, characterized in that: It includes multiple basic test units, and the basic test unit includes: A substrate, wherein a first active region and a second active region are defined in the substrate by an isolation structure, the first active region and the second active region are arranged at intervals along a first direction, and the first direction is parallel to the surface of the substrate; Two polysilicon structures are formed on the surface of the substrate, the two polysilicon structures extend along a first direction and are arranged at intervals along a second direction, the orthographic projection of each polysilicon structure on the substrate partially overlaps with the first active area and the second active area, and along the second direction, there is a first spacing between the two polysilicon structures, wherein the second direction is parallel to the substrate surface, and the second direction forms an angle with the first direction; A dielectric layer, covering the first active area and the second active area, and filling between the two polysilicon structures; A first contact structure, penetrating the dielectric layer and contacting the first active region, and located between the two polysilicon structures; a second contact structure, penetrating the dielectric layer and contacting the second active region, and located between the two polysilicon structures; The semiconductor test structure determines whether a hole is generated in the dielectric layer filled between the two polysilicon structures by measuring the leakage current of the first contact structure and the second contact structure.

2. The semiconductor test structure according to claim 1, characterized in that: The first spacing of the plurality of basic test units changes gradually, and the process window parameters of the first spacing can be obtained by measuring the leakage current of the first contact structure and the second contact structure in the plurality of basic test units.

3. The semiconductor test structure according to claim 2, characterized in that: Selecting a parameter in the process window parameters of the first spacing as a reference spacing; In the first direction, the first active region and the second active region have a second distance; In the second direction, the portion of at least one of the polysilicon structures located above the isolation structure also forms a protrusion protruding toward the other polysilicon structure, and the protrusion is located on opposite sides of the two polysilicon structures, so that the minimum spacing between the two polysilicon structures in the second direction is less than the reference spacing.

4. The semiconductor test structure according to claim 3, characterized in that: The second spacing of the plurality of basic test units changes gradually, and the process window parameters of the second spacing can be obtained by measuring the leakage current of the first contact structure and the second contact structure in the plurality of basic test units.

5. The semiconductor test structure according to claim 3, characterized in that: The minimum spacing of the plurality of basic test units changes gradually, and the process window parameters of the minimum spacing can be obtained by measuring the leakage current of the first contact structure and the second contact structure in the plurality of basic test units.

6. The semiconductor test structure according to claim 3, characterized in that: The method comprises a combined test unit, wherein the combined test unit comprises a plurality of the basic test units connected in series, and the second contact structure of the first basic test unit of two adjacent basic test units is electrically connected to the first contact structure of the second basic test unit.

7. The semiconductor test structure according to claim 6, characterized in that: The first contact structure of the first basic test unit of the combined test unit is connected to the first pad, and the second contact structure of the last basic test unit of the combined test unit is connected to the second pad. The combined unit is electrically tested by applying pressure to the first pad and the second pad.

8. A semiconductor testing method, characterized in that: The steps include: Providing a plurality of basic test units, wherein the basic test units are the basic test units as claimed in claim 2; measuring leakage currents of the first contact structures and the second contact structures in a plurality of the basic test units; The first spacing corresponding to the basic test unit whose leakage current meets the process requirement is counted to obtain a process window parameter of the first spacing.

9. The method according to claim 8, characterized in that The following steps are also included: Providing a plurality of basic test units, wherein the basic test units are the basic test units as claimed in claim 4; measuring leakage currents of the first contact structures and the second contact structures in a plurality of the basic test units; The second spacing corresponding to the basic test unit whose leakage current meets the process requirement is counted to obtain a process window parameter of the second spacing.

10. The method according to claim 8, characterized in that The following steps are also included: Providing a plurality of basic test units, wherein the basic test units are the basic test units as claimed in claim 5; measuring leakage currents of the first contact structures and the second contact structures in a plurality of the basic test units; The minimum spacing corresponding to the basic test unit whose leakage current meets the process requirement is counted to obtain a process window parameter of the minimum spacing.

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