Undervoltage protection circuit and high-voltage integrated circuit chip

Abstract

The invention discloses an under-voltage protection circuit and a high-voltage integrated circuit chip, the under-voltage protection circuit comprises a voltage division sub-circuit, a switch sub-circuit and an output sub-circuit, the switch sub-circuit comprises a first switch unit and a second switch unit, the first end of the voltage division sub-circuit, the first end of the first switch unit and the first end of the output sub-circuit are connected with a first working power supply, and the second end of the voltage division sub-circuit is connected with a second working power supply. The second end of the voltage division sub-circuit, the second end of the second switch unit and the second end of the output sub-circuit are connected with a second working power supply, the second end of the first switch unit is connected with the first end of the second switch unit to form a first node, and the control end of the first switch unit is connected with the third end of the voltage division sub-circuit to form a second node. The control end of the second switch unit is connected with the fourth end of the voltage division sub-circuit, the control end of the output sub-circuit is connected with the first node, and the third end of the output sub-circuit serves as the output end of the under-voltage protection circuit. The under-voltage protection circuit is small in occupied area, the HVIC cost can be reduced, and the risk caused by the overlarge voltage change rate is reduced.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This invention is a divisional application of the Chinese patent application with application number 202311327080.7 filed on October 12, 2023 and named “Undervoltage Protection Circuit and High-Voltage Integrated Circuit Chip”. Technical Field

[0003] The present invention relates to the technical field of integrated circuits, and in particular to an undervoltage protection circuit and a high-voltage integrated circuit chip. Background Art

[0004] HVIC (High Voltage Integrated Circuit) is a power integrated circuit that can be used to receive control signals from external digital chips such as CPU (Central Processing Unit) or MCU (Micro-Control Unit), and provide gate signals required to control and drive power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices or power IGBT (Insulate-Gate Bipolar Transistor) devices. In addition to providing drive signals, HVIC also needs to implement some protection functions, and undervoltage protection is one of the key functions.

[0005] Figure 1 This is a structural diagram of an HVIC. HVIC is generally divided into a low-voltage area and a high-voltage area. The high-voltage area generally has a high-voltage island and a high-voltage withstand voltage ring. The low-voltage area and each high-voltage island each require an undervoltage protection circuit.

[0006] Figure 2 It is a schematic diagram of an undervoltage protection circuit in the related art, including: resistors R1-R4, switch tubes M1-M16 and voltage regulator tube D. Although the undervoltage protection circuit can achieve undervoltage protection, it uses more devices and occupies a larger area of ​​HVIC, especially the area of ​​the high-voltage island, which not only increases the cost of HVIC, but also increases the parasitic capacitance between the high-voltage island and the substrate, increasing the risk of dv / dt impact. Summary of the invention

[0007] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the purpose of the present invention is to provide an undervoltage protection circuit and a high voltage integrated circuit chip, which has a small footprint, can reduce the cost of the HVIC, and reduce the risk caused by excessive voltage change rate.

[0008] To achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes an undervoltage protection circuit, including: a voltage divider subcircuit, a switch subcircuit and an output subcircuit, the switch subcircuit including a first switch unit and a second switch unit, the first end of the voltage divider subcircuit, the first end of the first switch unit and the first end of the output subcircuit are connected to a first working power supply, the second end of the voltage divider subcircuit, the second end of the second switch unit and the second end of the output subcircuit are connected to a second working power supply, the second end of the first switch unit is connected to the first end of the second switch unit to form a first node, the control end of the first switch unit is connected to the third end of the voltage divider subcircuit, the control end of the second switch unit is connected to the fourth end of the voltage divider subcircuit, the control end of the output subcircuit is connected to the first node, and the third end of the output subcircuit serves as the output end of the undervoltage protection circuit.

[0009] In addition, the undervoltage protection circuit of the above embodiment of the present invention may also have the following additional technical features:

[0010] According to one embodiment of the present invention, when the voltage of the first working power supply is greater than the target under-voltage threshold, the fourth end of the voltage divider sub-circuit outputs a first control signal to control the second switch unit to be turned on, and the first node outputs a second control signal to control the third end of the output sub-circuit to output an under-voltage signal of a first level; when the voltage of the first working power supply is less than or equal to the target under-voltage threshold, the third end of the voltage divider sub-circuit outputs a third control signal to control the first switch unit to be turned on, and the first node outputs a fourth control signal to control the third end of the output sub-circuit to output an under-voltage signal of a second level.

[0011] According to one embodiment of the present invention, the voltage divider subcircuit includes a first resistor, a second resistor R2 and a first voltage regulator; wherein the cathode of the first voltage regulator is connected to the first working power supply, the anode of the first voltage regulator is respectively connected to the first end of the first resistor and the control end of the first switch unit, the second end of the first resistor is respectively connected to the first end of the second resistor and the control end of the second switch unit, and the second end of the second resistor is connected to the second working power supply.

[0012] According to one embodiment of the present invention, the first switch unit includes a first PMOS tube and a second PMOS tube; wherein the source and substrate of the first PMOS tube are connected to the first working power supply, the gate of the first PMOS tube is connected to the anode of the first voltage regulator tube and the gate of the second PMOS tube respectively, the drain of the first PMOS tube is connected to the source of the second PMOS tube, the substrate of the second PMOS tube is connected to the first working power supply, and the drain of the second PMOS tube is connected to the first node.

[0013] According to one embodiment of the present invention, the second switch unit includes a first NMOS tube and a second NMOS tube; wherein the drain of the first NMOS tube is connected to the first node, the substrate of the first NMOS tube is connected to the second working power supply, the gate of the first NMOS tube is respectively connected to the second end of the first resistor and the gate of the second NMOS tube, the source of the first NMOS tube is connected to the drain of the second NMOS tube, and the substrate and source of the second NMOS tube are connected to the second working power supply.

[0014] According to one embodiment of the present invention, the switch subcircuit also includes a third PMOS tube, the source of the third PMOS tube is connected to the drain of the first PMOS tube, the substrate of the third PMOS tube is connected to the first working power supply, the drain of the third PMOS tube is connected to the second working power supply, and the gate of the third PMOS tube is connected to the first node.

[0015] According to an embodiment of the present invention, the circuit further includes a third resistor, a first end of the third resistor is connected to the second end of the first resistor, and a second end of the third resistor is connected to the gate of the first NMOS transistor.

[0016] According to an embodiment of the present invention, the circuit further includes a first capacitor, a first end of the first capacitor is connected to the gate of the first NMOS transistor, and a second end of the first capacitor is connected to the second working power supply.

[0017] According to one embodiment of the present invention, the voltage divider subcircuit includes a first voltage regulator tube, a second voltage regulator tube, a first resistor, a second resistor and a first triode; wherein, the cathode of the first voltage regulator tube is connected to the first working power supply, the anode of the first voltage regulator tube is connected to the control end of the first switch unit and the cathode of the second voltage regulator tube respectively, the anode of the second voltage regulator tube is connected to the first end of the first resistor, the second end of the first resistor is connected to the collector, the base and the control end of the second switch unit of the first triode respectively, the emitter of the first triode is connected to the first end of the second resistor, and the second end of the second resistor is connected to the second working power supply.

[0018] According to one embodiment of the present invention, the voltage divider subcircuit includes a first voltage regulator tube, a second voltage regulator tube, a first resistor, and a second resistor; wherein, the cathode of the first voltage regulator tube is connected to the first working power supply, the anode of the first voltage regulator tube is connected to the control end of the first switch unit and the cathode of the second voltage regulator tube respectively, the anode of the second voltage regulator tube is connected to the first end of the first resistor and the first end of the second resistor respectively, the second end of the first resistor is connected to the control end of the second switch unit, and the second end of the second resistor is connected to the second working power supply.

[0019] According to an embodiment of the present invention, the first resistor and the second resistor are proportional resistors.

[0020] According to one embodiment of the present invention, the first switch unit includes a first PMOS tube, a source and a substrate of the first PMOS tube are connected to the first working power supply, a gate of the first PMOS tube is connected to the anode of the first voltage regulator tube, and a drain of the first PMOS tube is connected to the first node.

[0021] According to one embodiment of the present invention, the second switch unit includes a second transistor, the collector of the second transistor is connected to the first node, the base of the second transistor is connected to the base of the first transistor, and the emitter of the second transistor is connected to the second working power supply.

[0022] According to one embodiment of the present invention, the second switching unit includes a second transistor, the collector of the second transistor is connected to the first node, the base of the second transistor is connected to the second end of the first resistor, and the emitter of the second transistor is connected to the second working power supply.

[0023] According to one embodiment of the present invention, the circuit also includes a second PMOS tube, a source and a substrate of the second PMOS tube are connected to the first working power supply, a gate of the second PMOS tube is connected to the third end of the output sub-circuit, and a drain of the second PMOS tube is connected to the first node.

[0024] According to an embodiment of the present invention, the circuit further includes a first capacitor, a first end of the first capacitor is connected to the gate of the first PMOS tube, and a second end of the first capacitor is connected to the second working power supply.

[0025] According to one embodiment of the present invention, the output subcircuit includes a fourth PMOS tube and a third NMOS tube; wherein, the source and substrate of the fourth PMOS tube are connected to the first working power supply, the source and substrate of the third NMOS tube are connected to the second working power supply, the gate of the third NMOS tube and the gate of the fourth PMOS tube are connected to the first node, the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube, and serves as the output end of the undervoltage protection circuit.

[0026] To achieve the above object, a second embodiment of the present invention provides a high-voltage integrated circuit chip, including the above undervoltage protection circuit.

[0027] The undervoltage protection circuit and high-voltage integrated circuit chip of the embodiment of the present invention occupy a small area, can reduce the cost of HVIC, and reduce the risk caused by excessive voltage change rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of an HVIC in the related art;

[0029] Figure 2 It is a schematic diagram of an undervoltage protection circuit in the related art;

[0030] Figure 3 is a structural block diagram of an undervoltage protection circuit according to an embodiment of the present invention;

[0031] Figure 4 is a circuit topology diagram of an undervoltage protection circuit according to an embodiment of the present invention;

[0032] Figure 5 is a circuit topology diagram of an undervoltage protection circuit according to another embodiment of the present invention;

[0033] Figure 6 is a circuit topology diagram of an undervoltage protection circuit according to another embodiment of the present invention;

[0034] Figure 7 It is a structural block diagram of a high-voltage integrated circuit chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0036] The undervoltage protection circuit and the high-voltage integrated circuit chip according to the embodiments of the present invention are described below with reference to the accompanying drawings.

[0037] Figure 3 It is a structural block diagram of an undervoltage protection circuit according to an embodiment of the present invention.

[0038] like Figure 3 As shown, the undervoltage protection circuit 100 includes: a voltage divider subcircuit 101, a switch subcircuit 102 and an output subcircuit 103, the switch subcircuit 102 includes a first switch unit 1021 and a second switch unit 1022, a first end of the voltage divider subcircuit 101, a first end of the first switch unit 1021 and a first end of the output subcircuit 103 are connected to a first working power supply VCC, a second end of the voltage divider subcircuit 101, a second end of the second switch unit 1022 and a second end of the output subcircuit 103 are connected to a second working power supply VSS, a second end of the first switch unit 1021 is connected to a first end of the second switch unit 1022 to form a first node, a control end of the first switch unit 1021 is connected to a third end of the voltage divider subcircuit 101, and a control end of the second switch unit 1022 is connected to The fourth end of the voltage divider subcircuit 101 is connected, the control end of the output subcircuit 103 is connected to the first node, and the third end of the output subcircuit 103 serves as the output end of the undervoltage protection circuit 100; wherein, when the voltage of the first working power supply VCC is greater than the target undervoltage threshold, the fourth end of the voltage divider subcircuit 101 outputs a first control signal to control the second switch unit 1022 to be turned on, the first node outputs a second control signal to control the third end of the output subcircuit 103 to output an undervoltage signal of a first level; when the voltage of the first working power supply VCC is less than or equal to the target undervoltage threshold, the third end of the voltage divider subcircuit 101 outputs a third control signal to control the first switch unit 1021 to be turned on, the first node outputs a fourth control signal to control the third end of the output subcircuit 103 to output an undervoltage signal of a second level.

[0039] Specifically, in the relevant IC manufacturing process, the block resistance used to provide resistance is only 1-2kΩ / μm; for a working voltage of 15V, assuming that the branch current of the voltage divider subcircuit 101 is designed to be 10μA, it is estimated that a 1.5MΩ resistor is required. In order to meet the matching accuracy of the resistor, the width of the resistor cannot be too small. Assuming that the width of the resistor is 3um, it is estimated that the area required for the resistor of the voltage divider subcircuit 101 alone will occupy 10000μm. 2 In addition, if Figure 2 The undervoltage protection circuit 100 shown in the figure has a resistor R4 in its bias circuit. The resistor R4 is close to the sum of the resistor 101 of the voltage divider circuit. If the branch current of the bias circuit is the same as the branch current of the voltage divider circuit 101, the total area of ​​the bias circuit and the voltage divider circuit 101 is 18000 μm. 2Therefore, in order to reduce the chip area occupied by the undervoltage protection circuit 100, reducing the resistor area is very important. In addition, the chip area occupied by the undervoltage protection circuit 100 can also be reduced by reducing the number of components. Therefore, the resistors and components in the voltage divider subcircuit 101, the switch subcircuit 102 and the output subcircuit 103 can be reduced.

[0040] like Figure 1 As shown in the structure of the HVIC, the HVIC is generally divided into a low voltage area and a high voltage area. The high voltage area generally has a high voltage island and a high voltage withstand ring. The low voltage area and each high voltage island each require an undervoltage protection circuit 100.

[0041] like Figure 2 An undervoltage protection circuit 100 in the related art shown in the figure includes: resistors R1-R4, switch tubes M1-M16 and voltage regulator tube D. Although the undervoltage protection circuit can achieve undervoltage protection, it uses more components and occupies a larger HVIC area, especially the high-voltage island area, which not only increases the HVIC cost, but also increases the parasitic capacitance between the high-voltage island and the substrate, and increases the risk of dv / dt (voltage change rate).

[0042] The undervoltage protection circuit of the embodiment of the present invention reduces the area of ​​the high-voltage island occupied by it, reduces the area of ​​the high-voltage island, thereby reducing the area of ​​the chip and reducing the chip cost. The reduction of the high-voltage island also reduces the parasitic capacitance between it and the substrate. It can be seen from the capacitance coupling formula i=C*dv / dt that the risk brought by dv / dt during circuit operation is reduced, where i is current and C is capacitance. The undervoltage protection circuit is more effective when used in the high-voltage side circuit of HVIC, and the undervoltage protection circuit can also be used in the low-voltage side circuit of HVIC. Because the low-voltage side circuit of HVIC has a large area and many circuits, the reduction in the area of ​​the undervoltage protection circuit has an effect on the low-voltage side, but it is not significant enough. However, the reduction in the area of ​​the undervoltage protection circuit has a relatively large impact on the high-voltage island. The reduction of the high-voltage island can drive the reduction of the high-voltage withstand voltage ring, so that the size of the entire chip can be reduced.

[0043] In some embodiments, Figure 4 As shown, the voltage divider subcircuit 101 includes a first resistor R1, a second resistor R2 and a first voltage regulator D1; wherein, the cathode of the first voltage regulator D1 is connected to the first working power supply VCC, the anode of the first voltage regulator D1 is connected to the first end of the first resistor R1 and the control end of the first switch unit 1021 respectively, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the control end of the second switch unit 1022 respectively, and the second end of the second resistor R2 is connected to the second working power supply VSS.

[0044] Specifically, Figure 4As shown, the voltage divider subcircuit 101 is no longer composed of only resistors. The voltage divider subcircuit 101 is connected in series with the first voltage regulator D1. The voltage regulator voltage of the first voltage regulator D1 can be 5V, 6V, 7V, etc. according to the process. Taking the voltage regulator voltage of 5V as an example, the voltage divider subcircuit 101 can reduce 1 / 3 of the resistance. If the voltage regulator voltage is 5V or 6V, the voltage divider subcircuit 101 can reduce 40% of the resistance. In addition, the voltage divider subcircuit 101 does not have a bias circuit and a comparator circuit, which reduces the number of devices and the resistance.

[0045] In some embodiments, Figure 4 As shown, the first switch unit 1021 includes a first PMOS tube MP1 and a second PMOS tube MP2; wherein, the source and substrate of the first PMOS tube MP1 are connected to the first working power supply VCC, the gate of the first PMOS tube MP1 is connected to the anode of the first voltage regulator tube D1 and the gate of the second PMOS tube MP2 respectively, the drain of the first PMOS tube MP1 is connected to the source of the second PMOS tube MP2, the substrate of the second PMOS tube MP2 is connected to the first working power supply VCC, and the drain of the second PMOS tube MP2 is connected to the first node.

[0046] In some embodiments, Figure 4 As shown, the second switch unit 1022 includes a first NMOS tube MN1 and a second NMOS tube MN2; wherein, the drain of the first NMOS tube MN1 is connected to the first node, the substrate of the first NMOS tube MN1 is connected to the second working power supply VSS, the gate of the first NMOS tube MN1 is connected to the second end of the first resistor R1 and the gate of the second NMOS tube MN2 respectively, the source of the first NMOS tube MN1 is connected to the drain of the second NMOS tube MN2, and the substrate and source of the second NMOS tube MN2 are connected to the second working power supply VSS.

[0047] In some embodiments, Figure 4 As shown, the switch sub-circuit 102 also includes a third PMOS tube MP3, the source of the third PMOS tube MP3 is connected to the drain of the first PMOS tube MP1, the substrate of the third PMOS tube MP3 is connected to the first working power supply VCC, the drain of the third PMOS tube MP3 is connected to the second working power supply VSS, and the gate of the third PMOS tube MP3 is connected to the first node.

[0048] Among them, the third PMOS tube MP3 plays a feedback role, which is used to realize the hysteresis of undervoltage protection, even if the undervoltage trigger threshold and recovery threshold are different.

[0049] Specifically, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the first NMOS transistor MN1, and the second NMOS transistor MN2 form a structure similar to a Schmitt trigger. Among them, the Schmitt trigger is a comparator circuit with hysteresis, which is realized by applying positive feedback to the non-inverting input terminal of the comparator or differential amplifier. The Schmitt trigger uses two inputs with different threshold voltage levels to avoid noise in the input signal. The effect of this dual threshold is called hysteresis, that is, when the input is higher than the preset high-level threshold voltage, the output is low; when the input is lower than the preset low-level threshold voltage, the output is high; when the input is between the two, the output maintains its current value.

[0050] In some embodiments, Figure 4 As shown, the undervoltage protection circuit 100 further includes a third resistor R3, a first end of the third resistor R3 is connected to the second end of the first resistor R1, and a second end of the third resistor R3 is connected to the gate of the first NMOS transistor MN1.

[0051] In some embodiments, Figure 4 As shown, the undervoltage protection circuit 100 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the gate of the first NMOS transistor MN1, and a second end of the first capacitor C1 is connected to the second working power supply VSS.

[0052] In some embodiments, Figure 4 As shown, the output sub-circuit 103 includes a fourth PMOS transistor MP4 and a third NMOS transistor MN3; wherein, the source and substrate of the fourth PMOS transistor MP4 are connected to the first working power supply VCC, the source and substrate of the third NMOS transistor MN3 are connected to the second working power supply, the gate of the third NMOS transistor MN3 and the gate of the fourth PMOS transistor MP4 are connected to the first node, and the drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4, and serves as the output terminal UV of the undervoltage protection circuit 100.

[0053] The fourth PMOS transistor MP4 and the third NMOS transistor MN3 form an inverter, and output an undervoltage signal at the output terminal UV.

[0054] In this embodiment, the first voltage regulator D1 fixes the VGS (gate-to-source voltage) of the first PMOS tube MP1 and the second PMOS tube MP2, that is, their current-flowing capabilities are determined; the width-to-length ratio of the first PMOS tube MP1 and the second PMOS tube MP2 is adjusted to adjust the current of the branch.

[0055] When the voltage of the first working power supply VCC is high and the undervoltage protection is not triggered, the first resistor R1 and the second resistor R2 divide the voltage; the voltage division of the second resistor R2 causes the first NMOS tube MN1 and the second NMOS tube MN2 to turn on, and the ability of the first NMOS tube MN1 and the second NMOS tube MN2 to flow current is significantly higher than the first PMOS tube MP1 and the second PMOS tube MP2. Therefore, the voltage V1 of the drain of the first NMOS MN1 is a low level 0V. At this time, the undervoltage signal is a high level VCC.

[0056] When the voltage of the first working power supply VCC decreases, the voltage division of the second resistor R2 gradually decreases, and finally triggers the undervoltage protection, that is, the voltage division of the resistor R2 causes the first NMOS tube MN1 and the second NMOS tube MN2 to have a lower current flow capacity than the first PMOS tube MP1 and the second PMOS tube MP2 when turned on, or to be turned off. Therefore, the voltage V1 is a high level VCC, and the undervoltage signal becomes a low level 0V.

[0057] When the voltage of the first working power source VCC recovers to a higher level, due to the feedback effect of the third NMOS transistor MP3, the first working power source VCC needs a voltage higher than the undervoltage trigger threshold to restore the undervoltage signal to a high level VCC.

[0058] The first resistor R1 and the second resistor R2 are proportional resistors, and it is best to ensure a certain degree of matching accuracy. The undervoltage protection threshold (undervoltage trigger threshold and undervoltage recovery threshold) can be adjusted by adjusting R1 / R2.

[0059] In this embodiment, the third resistor R3 is a dummy resistor of the first resistor R1 and the second resistor R2. The third resistor R3 can be connected to the circuit or not. Connecting the third resistor R3 can increase the filtering time of the undervoltage protection circuit 100; if the third resistor R3 is not connected, the gates of the first NMOS tube MN1 and the second NMOS tube MN2 are directly connected between the first resistor R1 and the second resistor R2, and the filtering time 100 of the undervoltage protection circuit 100 is reduced. Among them, the dummy resistor can prevent the influence of the noise signal in the circuit on the key signal.

[0060] Compared to Figure 2 The undervoltage protection circuit 100 shown in the embodiment has an undervoltage filtering function. If the undervoltage filtering function is not required, the first capacitor C1 can be deleted and the third resistor R3 can be disconnected from the circuit.

[0061] Compared with the solution in which the first PMOS tube MP1 and the second PMOS tube MP2 are combined into one PMOS tube and connected with the third NMOS tube MP3 to form a feedback circuit, the first NMOS tube MN1 and the second NMOS tube MN2 are combined into one NMOS tube. The undervoltage protection circuit 100 described in this embodiment does not increase the device area, and this solution has higher accuracy, lower temperature drift and good parameter consistency, that is, the undervoltage protection threshold voltage error of this solution is small, the change of semiconductor device parameters caused by temperature change is low, and the circuit made according to this solution is more consistent with the design.

[0062] Compared to Figure 2 If the undervoltage protection circuit 100 shown in the embodiment also does not use the filtering function, the resistor area in the undervoltage protection circuit 100 described in the embodiment only needs to be 7300 μm 2 , which is reduced by about 60%, and the number of components is significantly reduced. In addition to the resistor, only 4 PMOS transistors, 3 NMOS transistors and a voltage regulator are needed. Moreover, the power consumption of the undervoltage protection circuit 100 is reduced by about 50%, that is, if the same power consumption is used, the resistor area can be further reduced.

[0063] In some embodiments, Figure 5 As shown, the voltage divider subcircuit 101 includes a first voltage regulator tube D1, a second voltage regulator tube D2, a first resistor R1, a second resistor R2 and a first triode Q1; wherein, the cathode of the first voltage regulator tube D1 is connected to the first working power supply VCC, the anode of the first voltage regulator tube D1 is connected to the control end of the first switch unit 1021 and the cathode of the second voltage regulator tube D2 respectively, the anode of the second voltage regulator tube D2 is connected to the first end of the first resistor, the second end of the first resistor R1 is connected to the collector and base of the first triode Q1 and the control end of the second switch unit 1022 respectively, the emitter of the first triode Q1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the second working power supply VSS.

[0064] The first resistor R1 and the second resistor R2 are proportional resistors, and it is best to ensure a certain degree of matching accuracy. The undervoltage protection threshold (undervoltage trigger threshold and undervoltage recovery threshold) can be adjusted by adjusting R1 / R2.

[0065] In this embodiment, if Figure 5 The voltage divider subcircuit 101 shown in FIG. Figure 4 On the basis of the voltage regulator, a voltage regulator tube is added. The undervoltage protection threshold can be set between 8V and 11.5V according to different applications. Therefore, this solution uses a voltage regulator tube of about 5V. Figure 5 The resistor area of ​​the undervoltage protection circuit 100 is reduced to 4000 μm 2 , add a voltage regulator tube, and the area of ​​the voltage regulator tube is generally 850μm2 the following.

[0066] In some embodiments, Figure 5 As shown, the first switch unit 1021 includes a first PMOS tube MP1, a source and a substrate of the first PMOS tube MP1 are connected to the first working power supply VCC, a gate of the first PMOS tube MP1 is connected to the anode of the first voltage regulator tube D1, and a drain of the first PMOS tube MP1 is connected to the first node.

[0067] In some embodiments, Figure 5 As shown, the second switch unit 1022 includes a second transistor Q2, the collector of the second transistor Q2 is connected to the first node, the base of the second transistor Q2 is connected to the base of the first transistor Q1, and the emitter of the second transistor is connected to the second working power supply VSS.

[0068] In some embodiments, Figure 5 As shown, the undervoltage protection circuit 100 also includes a second PMOS tube MP2, a source and a substrate of the second PMOS tube MP2 are connected to the first working power supply VCC, a gate of the second PMOS tube MP2 is connected to the third end of the output sub-circuit 103, and a drain of the second PMOS tube MP2 is connected to the first node.

[0069] In this embodiment, the first PMOS transistor MP1 and the second transistor Q2 form a structure similar to a Schmitt trigger. The second PMOS transistor MP2 plays a feedback role to achieve the hysteresis of the undervoltage protection, even if the undervoltage trigger threshold and the recovery threshold are different.

[0070] The first voltage regulator D1 fixes the VGS of the first PMOS transistor MP1 , that is, its ability to pass current is determined; the current of the branch can be adjusted by adjusting the width-to-length ratio of the first PMOS transistor MP1 .

[0071] When the first working power supply VCC is high and the undervoltage protection is not triggered, the first resistor R1, the first transistor Q1 and the second resistor R2 divide the voltage and current. The base voltage and current of the second transistor Q2 make the second transistor Q2 have a larger overcurrent capacity, and the collector voltage of the second transistor Q2 is pulled to 0V. At this time, the undervoltage signal is a high level VCC.

[0072] When the first working power supply VCC decreases, the base voltage and current of the second transistor Q2 will decrease until the overcurrent capability of the second transistor Q2 is lower than that of the first PMOS tube MP1, or the second transistor Q2 is turned off, i.e., the undervoltage protection is triggered, so that the collector voltage of the second transistor Q2 becomes a high level, and the undervoltage signal becomes a low level 0V.

[0073] When the first working power source VCC recovers to a higher level, due to the feedback effect of the second PMOS transistor MP2, the first working power source VCC needs a voltage higher than the trigger threshold to restore the undervoltage signal.

[0074] In some embodiments, Figure 5 As shown, the undervoltage protection circuit 100 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the gate of the first PMOS transistor MP1, and a second end of the first capacitor C1 is connected to the second working power supply VSS. The capacitor C1 is a filter capacitor.

[0075] In some embodiments, Figure 5 As shown, the output sub-circuit 103 includes a fourth PMOS transistor MP4 and a third NMOS transistor MN3; wherein, the source and substrate of the fourth PMOS transistor MP4 are connected to the first working power supply VCC, the source and substrate of the third NMOS transistor MN3 are connected to the second working power supply, the gate of the third NMOS transistor MN3 and the gate of the fourth PMOS transistor MP4 are connected to the first node, and the drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4, and serves as the output terminal UV of the undervoltage protection circuit 100.

[0076] In this embodiment, the fourth PMOS transistor MP4 and the third NMOS transistor MN3 form an inverter to output an undervoltage signal. Figure 5 Compared with the undervoltage protection circuit 100 shown in FIG. Figure 4 The undervoltage protection circuit 100 shown in the figure has two fewer NMOS transistors, but two more transistors. The area of ​​the transistor is about 50% smaller than that of the NMOS transistor (the NMOS transistor needs isolation protection), so Figure 5 The undervoltage protection circuit 100 shown in the figure has a smaller area, but its undervoltage protection threshold can be set within a range that is limited by the withstand voltage of the voltage regulator tube. Figure 4 The undervoltage protection circuit 100 shown has a wide range and is flexible, but its accuracy, parameter consistency and temperature drift are not as good as Figure 4 The undervoltage protection circuit 100 is shown.

[0077] In some embodiments, Figure 6 As shown, the voltage divider subcircuit 101 includes a first voltage regulator tube D1, a second voltage regulator tube D2, a first resistor R1, and a second resistor R2; wherein, the cathode of the first voltage regulator tube D1 is connected to the first working power supply VCC, the anode of the first voltage regulator tube D1 is connected to the control end of the first switch unit 1021 and the cathode of the second voltage regulator tube D2, respectively, the anode of the second voltage regulator tube D2 is connected to the first end of the first resistor R1 and the first end of the second resistor R2, respectively, the second end of the first resistor R1 is connected to the control end of the second switch unit 1022, and the second end of the second resistor R2 is connected to the second working power supply VSS.

[0078] In some embodiments, Figure 6 As shown, the first switch unit 1021 includes a first PMOS tube MP1, a source and a substrate of the first PMOS tube MP1 are connected to the first working power supply VCC, a gate of the first PMOS tube MP1 is connected to the anode of the first voltage regulator tube D1, and a drain of the first PMOS tube MP1 is connected to the first node.

[0079] In some embodiments, Figure 6 As shown, the second switch unit 1022 includes a second transistor Q2, the collector of the second transistor Q2 is connected to the first node, the base of the second transistor Q2 is connected to the first resistor R1, and the emitter of the second transistor Q2 is connected to the second working power supply VSS.

[0080] In some embodiments, Figure 6 As shown, the undervoltage protection circuit 100 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the gate of the first PMOS transistor MP1, and a second end of the first capacitor C1 is connected to the second working power supply VSS. The capacitor C1 is a filter capacitor.

[0081] In some embodiments, Figure 6 As shown, the output sub-circuit 103 includes a fourth PMOS transistor MP4 and a third NMOS transistor MN3; wherein, the source and substrate of the fourth PMOS transistor MP4 are connected to the first working power supply VCC, the source and substrate of the third NMOS transistor MN3 are connected to the second working power supply VSS, the gate of the third NMOS transistor MN3 and the gate of the fourth PMOS transistor MP4 are connected to the first node, and the drain of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4, and serves as the output terminal UV of the undervoltage protection circuit 100.

[0082] In some embodiments, Figure 6 As shown, the undervoltage protection circuit 100 also includes a second PMOS tube MP2, a source and a substrate of the second PMOS tube MP2 are connected to the first working power supply VCC, a gate of the second PMOS tube MP2 is connected to the third end of the output sub-circuit 103, and a drain of the second PMOS tube MP2 is connected to the first node.

[0083] In this embodiment, compared with Figure 5 The undervoltage protection circuit 100 shown in the figure reduces the first transistor Q1; the second PMOS transistor MP2 can be removed or retained. If removed, C1 is required for filtering.

[0084] The base of the second transistor Q2 is connected in series with a resistor R1 to limit the current. Figure 6The undervoltage protection circuit 100 shown is also limited by the voltage of the Zener diode. If a 5V Zener diode is used, the undervoltage protection threshold is approximately between 10V and 10.7V. This solution will increase power consumption because the first resistor R1 and the second resistor R2 are almost connected in parallel. However, in this embodiment, the first resistor R1 and the second resistor R2 do not need to be proportional resistors, and the matching degree requirement is not high. Therefore, resistors with smaller widths and flexible layout methods can be used to appropriately increase resistance and reduce power consumption while keeping the circuit area unchanged. Figure 6 The accuracy, parameter consistency, and temperature drift of the undervoltage protection circuit 100 shown are not as good as those of the Figure 4 The undervoltage protection circuit 100 is shown.

[0085] In summary, the undervoltage protection circuit of the embodiment of the present invention reduces the area of ​​the high-voltage island occupied by it, reduces the area of ​​the high-voltage island, thereby reducing the area of ​​the chip and reducing the chip cost. The reduction of the high-voltage island also reduces the parasitic capacitance between it and the substrate. It can be seen from the capacitive coupling formula i=C*dv / dt that the risk brought by dv / dt during circuit operation is reduced, where i is current and C is capacitance. The undervoltage protection circuit is more effective when used in the high-voltage side circuit of HVIC, and the undervoltage protection circuit can also be used in the low-voltage side circuit of HVIC. Because the low-voltage side circuit of HVIC has a large area and many circuits, the reduction in the area of ​​the undervoltage protection circuit has an effect on the low-voltage side, but it is not significant enough. However, the reduction in the area of ​​the undervoltage protection circuit has a relatively large impact on the high-voltage island. The reduction of the high-voltage island can drive the reduction of the high-voltage withstand voltage ring, so that the size of the entire chip can be reduced.

[0086] Figure 7 It is a structural block diagram of a high-voltage integrated circuit chip according to an embodiment of the present invention.

[0087] like Figure 7 As shown, the high voltage integrated circuit chip 700 includes: the above-mentioned undervoltage protection circuit 100.

[0088] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0089] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0090] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0091] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0092] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0093] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. An undervoltage protection circuit, characterized in that: include: A voltage divider subcircuit, a switch subcircuit and an output subcircuit, wherein the switch subcircuit comprises a first switch unit and a second switch unit, wherein the first end of the voltage divider subcircuit, the first end of the first switch unit and the first end of the output subcircuit are connected to a first working power supply, the second end of the voltage divider subcircuit, the second end of the second switch unit and the second end of the output subcircuit are connected to a second working power supply, the second end of the first switch unit is connected to the first end of the second switch unit to form a first node, the control end of the first switch unit is connected to the third end of the voltage divider subcircuit, the control end of the second switch unit is connected to the fourth end of the voltage divider subcircuit, the control end of the output subcircuit is connected to the first node, and the third end of the output subcircuit serves as the output end of the undervoltage protection circuit.

2. The undervoltage protection circuit according to claim 1, characterized in that: When the voltage of the first working power supply is greater than the target undervoltage threshold, the fourth terminal of the voltage divider subcircuit outputs a first control signal to control the second switch unit to be turned on, and the first node outputs a second control signal to control the third terminal of the output subcircuit to output an undervoltage signal of a first level; When the voltage of the first working power supply is less than or equal to the target under-voltage threshold, the third end of the voltage divider sub-circuit outputs a third control signal to control the first switch unit to be turned on, and the first node outputs a fourth control signal to control the third end of the output sub-circuit to output an under-voltage signal of a second level.

3. The undervoltage protection circuit according to claim 1, characterized in that: The voltage divider subcircuit includes a first resistor, a second resistor and a first voltage regulator tube; wherein, The cathode of the first voltage regulator is connected to the first working power supply, the anode of the first voltage regulator is respectively connected to the first end of the first resistor and the control end of the first switch unit, the second end of the first resistor is respectively connected to the first end of the second resistor and the control end of the second switch unit, and the second end of the second resistor is connected to the second working power supply.

4. The undervoltage protection circuit according to claim 3, characterized in that: The first switch unit includes a first PMOS tube and a second PMOS tube; wherein, The source and substrate of the first PMOS tube are connected to the first working power supply, the gate of the first PMOS tube is connected to the anode of the first voltage regulator tube and the gate of the second PMOS tube respectively, the drain of the first PMOS tube is connected to the source of the second PMOS tube, the substrate of the second PMOS tube is connected to the first working power supply, and the drain of the second PMOS tube is connected to the first node.

5. The undervoltage protection circuit according to claim 3, characterized in that: The second switch unit includes a first NMOS tube and a second NMOS tube; wherein, The drain of the first NMOS tube is connected to the first node, the substrate of the first NMOS tube is connected to the second working power supply, the gate of the first NMOS tube is connected to the second end of the first resistor and the gate of the second NMOS tube respectively, the source of the first NMOS tube is connected to the drain of the second NMOS tube, and the substrate and source of the second NMOS tube are connected to the second working power supply.

6. The undervoltage protection circuit according to claim 4, characterized in that: The switch subcircuit also includes a third PMOS tube, a source of the third PMOS tube is connected to the drain of the first PMOS tube, a substrate of the third PMOS tube is connected to the first working power supply, a drain of the third PMOS tube is connected to the second working power supply, and a gate of the third PMOS tube is connected to the first node.

7. The undervoltage protection circuit according to claim 5, characterized in that: The circuit further includes a third resistor R3, a first end of the third resistor is connected to the second end of the first resistor, and a second end of the third resistor is connected to the gate of the first NMOS transistor.

8. The undervoltage protection circuit according to claim 5, characterized in that: The circuit further includes a first capacitor, a first end of the first capacitor is connected to the gate of the first NMOS transistor, and a second end of the first capacitor is connected to the second working power supply.

9. The undervoltage protection circuit according to claim 1, characterized in that: The voltage divider subcircuit includes a first voltage regulator tube, a second voltage regulator tube, a first resistor, a second resistor and a first triode; wherein, The cathode of the first voltage-stabilizing tube is connected to the first working power supply, the anode of the first voltage-stabilizing tube is connected to the control end of the first switch unit and the cathode of the second voltage-stabilizing tube respectively, the anode of the second voltage-stabilizing tube is connected to the first end of the first resistor, the second end of the first resistor is connected to the collector and base of the first transistor and the control end of the second switch unit respectively, the emitter of the first transistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the second working power supply.

10. The undervoltage protection circuit according to claim 1, characterized in that: The voltage divider subcircuit includes a first voltage regulator tube, a second voltage regulator tube, a first resistor, and a second resistor; wherein, The cathode of the first voltage-stabilizer tube is connected to the first working power supply, the anode of the first voltage-stabilizer tube is connected to the control end of the first switch unit and the cathode of the second voltage-stabilizer tube respectively, the anode of the second voltage-stabilizer tube is connected to the first end of the first resistor and the first end of the second resistor respectively, the second end of the first resistor is connected to the control end of the second switch unit, and the second end of the second resistor is connected to the second working power supply.

11. The undervoltage protection circuit according to claim 3, 9 or 10, characterized in that: The first resistor and the second resistor are proportional resistors.

12. The undervoltage protection circuit according to claim 9 or 10, characterized in that: The first switch unit includes a first PMOS tube, a source and a substrate of the first PMOS tube are connected to the first working power supply, a gate of the first PMOS tube is connected to the anode of the first voltage regulator tube, and a drain of the first PMOS tube is connected to the first node.

13. The undervoltage protection circuit according to claim 9, characterized in that: The second switch unit includes a second transistor, the collector of the second transistor is connected to the first node, the base of the second transistor is connected to the base of the first transistor, and the emitter of the second transistor is connected to the second working power supply.

14. The undervoltage protection circuit according to claim 10, characterized in that: The second switch unit includes a second transistor, a collector of the second transistor is connected to the first node, a base of the second transistor is connected to the second end of the first resistor, and an emitter of the second transistor is connected to the second working power supply.

15. The undervoltage protection circuit according to claim 9 or 10, characterized in that: The circuit also includes a second PMOS tube, a source and a substrate of the second PMOS tube are connected to the first working power supply, a gate of the second PMOS tube is connected to the third end of the output subcircuit, and a drain of the second PMOS tube is connected to the first node.

16. The undervoltage protection circuit according to claim 12, characterized in that: The circuit further includes a first capacitor, a first end of the first capacitor is connected to the gate of the first PMOS tube, and a second end of the first capacitor is connected to the second working power supply.

17. The undervoltage protection circuit according to claim 3, 9 or 10, characterized in that: The output subcircuit includes a fourth PMOS tube and a third NMOS tube; wherein, The source and substrate of the fourth PMOS tube are connected to the first working power supply, the source and substrate of the third NMOS tube are connected to the second working power supply, the gate of the third NMOS tube and the gate of the fourth PMOS tube are connected to the first node, and the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube, and serves as the output end of the undervoltage protection circuit.

18. A high voltage integrated circuit chip, characterized in that: The invention comprises an undervoltage protection circuit as claimed in any one of claims 1 to 17.

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