Peak current generation circuit, converter, chip, and electronic device

Abstract

The invention relates to the technical field of converters, in particular to a peak current generation circuit, a converter, a chip and electronic equipment. The peak current generating circuit comprises an output voltage sampling circuit, a reference voltage generating circuit, an adjusting signal generating circuit and a current adjusting circuit; the adjusting signal generating circuit is used for generating a first adjusting signal and a second adjusting signal according to the magnitude relation of the first reference voltage, the second reference voltage and the output voltage; and the current adjusting circuit is used for increasing the current value of the output current according to the first adjusting signal or decreasing the current value of the output current according to the second adjusting signal, and taking the adjusted output current as the peak current of the energy storage circuit. Therefore, the peak value of the inductive current can be adaptively adjusted according to the output voltage of the output end of the converter, so that the peak value of the inductive current can meet the current on-load requirement of the converter, the alternating current loss of the converter can be reduced, and the working efficiency of the converter is improved.

Description

Technical Field

[0001] The present application relates to the technical field of converters, and in particular to a peak current generating circuit, a converter, a chip and an electronic device. Background Art

[0002] As a common functional circuit, converter is often used in various electronic devices. It can boost or buck the input voltage and then output a stable supply voltage at the load end.

[0003] In an application scenario, when the output end of the converter is lightly loaded, in order to save the power consumption of the converter, the converter is usually controlled to operate in a discontinuous conduction mode (DCM), and when the converter is in the DCM mode, the setting of the peak value of the inductor current is particularly important. If the peak value of the inductor current is set too small, the load capacity of the converter will be insufficient. If the peak value of the inductor current is set too large, the inductor current ripple will be too large, thereby increasing the AC loss of the converter. Because, in the related art, in order to give priority to the load capacity of the converter, the peak value of the inductor current of the converter is usually set to a larger fixed value. Although this can meet the load capacity under different input voltage and output voltage combinations, for some input voltage and output voltage combinations, an excessively large peak value of the inductor current will increase the AC loss of the converter, resulting in a lower working efficiency of the converter. Summary of the invention

[0004] The present application provides a peak current generating circuit, a converter, a chip and an electronic device to solve the technical problem of low converter working efficiency in the related art.

[0005] In a first aspect, the present application provides a peak current generating circuit for use in a converter, wherein the converter comprises an energy storage circuit and a power supply circuit; an input end of the energy storage circuit is used to receive an input voltage, and an output end of the energy storage circuit is connected to an input end of the power supply circuit; an output end of the power supply circuit is used to connect a load; the energy storage circuit is used to store energy when the power supply circuit is in a closed state; and the power supply circuit is used to supply power to the load;

[0006] Wherein, the peak current generating circuit includes an output voltage sampling circuit, a reference voltage generating circuit, an adjustment signal generating circuit and a current regulating circuit;

[0007] The output voltage sampling circuit is used to sample the output voltage at the output end of the power supply circuit;

[0008] The reference voltage generating circuit is used to generate a first reference voltage and a second reference voltage, wherein the first reference voltage and the second reference voltage are both lower than the input voltage, and the second reference voltage is higher than the first reference voltage;

[0009] The regulating signal generating circuit is configured to generate a first regulating signal when it is determined that both the first reference voltage and the second reference voltage are less than the output voltage; and to generate a second regulating signal when it is determined that both the first reference voltage and the second reference voltage are greater than the output voltage;

[0010] The current regulating circuit is used to increase the current value of the output current according to the first regulating signal, or to decrease the current value of the output current according to the second regulating signal, and to use the regulated output current as the peak current of the energy storage circuit.

[0011] In a possible design, the adjustment signal generating circuit is further configured to output a current holding signal when it is determined that the first reference voltage is less than the output voltage and the second reference voltage is greater than the output voltage;

[0012] The current regulating circuit is used to maintain the output current adjusted last time as the peak current of the energy storage circuit according to the current holding signal.

[0013] In a possible design, the reference voltage generating circuit is further used to increase the first reference voltage and the second reference voltage according to a first adjustment signal, and to decrease the first reference voltage and the second reference voltage according to the second adjustment signal.

[0014] In a possible design, the input end of the reference voltage generating circuit is used to receive the input voltage, and the output end of the reference voltage generating circuit is grounded;

[0015] A plurality of voltage-dividing resistors are sequentially connected in series between the input and output ends of the reference voltage generating circuit, and a reference voltage output end is provided on the input end of each voltage-dividing resistor, and different reference voltage output ends are used to output reference voltages;

[0016] The voltage-dividing resistor corresponding to the second reference voltage is close to the input end of the reference voltage generating circuit, and the voltage-dividing voltage corresponding to the first reference voltage is close to the output end of the reference voltage generating circuit.

[0017] In one possible design, the adjustment signal generating circuit includes a first latch comparator, a second latch comparator, an XNOR gate, an AND gate, and a counter;

[0018] The output end of the first latch comparator is connected to the count control pin of the counter; the output ends of the first latch comparator and the second latch comparator are connected to the input end of the XNOR gate, the output end of the XNOR gate is connected to the first input end of the AND gate, the second input end of the AND gate is used to receive the lower tube drive signal, and the output end of the AND gate is connected to the clock input pin of the counter;

[0019] The first latch comparator is used to output a first logic signal when it is determined that the first reference voltage is less than the output voltage; the second latch comparator is used to output a second logic signal when it is determined that the second reference voltage is less than the output voltage; the XOR gate and the AND gate are used to calculate the first logic signal, the second logic signal and the lower tube drive signal to obtain a first clock signal; the counter is used to output the first adjustment signal according to the first clock signal and the first logic signal;

[0020] In a possible design, the first latch comparator is also used to output a third logic signal when it is determined that the first reference voltage is greater than the output voltage; the second latch comparator is used to output a fourth logic signal when it is determined that the second reference voltage is greater than the output voltage; the XNOR gate and the AND gate are used to operate the third logic signal, the fourth logic signal and the lower tube drive signal to obtain a second clock signal; the counter is used to output the second adjustment signal according to the second clock signal and the third logic signal.

[0021] In a possible design, the first latch comparator is also used to output a first logic signal when it is determined that the first reference voltage is less than the output voltage; the second latch comparator is used to output a fourth logic signal when it is determined that the second reference voltage is greater than the output voltage; the XOR gate and the AND gate are used to operate the first logic signal, the fourth logic signal and the lower tube drive signal to obtain a third clock signal; the counter is used to output the current holding signal according to the third clock signal and the first logic signal.

[0022] In a possible design, the adjustment signal generating circuit further includes a first digital selector and a second digital selector;

[0023] The input ends of the first digital selector and the second digital selector are respectively connected to different reference voltage output ends of the reference voltage generating circuit, and the output ends of the first digital selector and the second digital selector are respectively connected to the input ends of the first latch comparator and the second latch comparator;

[0024] The input ends of the first digital selector and the second digital selector are also used to receive the first adjustment signal, the second adjustment signal or the current holding signal, and the input ends of the first digital selector and the second digital selector are adjusted to be connected to different reference voltage output ends respectively according to the first adjustment signal, the second adjustment signal or the current holding signal, so as to output different reference voltages.

[0025] In a possible design, the current regulating circuit includes a current output main circuit and a current adjustable unit, the current adjustable unit includes a plurality of current output branches arranged in parallel, the output end of each current output branch is connected to the output end of the current output main circuit, and the current value outputted by each current output branch is different;

[0026] The current adjustable unit is used to receive the first adjustment signal, the second adjustment signal and the current holding signal, and control different current output branches to be turned on according to the first adjustment signal, the second adjustment signal or the current holding signal.

[0027] In a second aspect, the present application further provides a converter, which includes an energy storage circuit, a power supply circuit and a control circuit; the input end of the energy storage circuit is used to receive an input voltage, and the output end of the energy storage circuit is connected to the input end of the power supply circuit; the output end of the power supply circuit is used to connect a load; the energy storage circuit is used to store energy when the power supply circuit is in a closed state; the power supply circuit is used to discharge the load when the energy storage circuit is in a closed state;

[0028] The control circuit includes a peak current generating circuit as described in any one of the above items, and the control circuit is used to adjust the peak value of the inductor current in the energy storage circuit according to the peak current output by the peak current generating circuit.

[0029] In a possible design, the converter or the control circuit further includes a current sampling circuit, which is used to collect the inductor current value on the energy storage circuit and output the sampled inductor current value on the energy storage circuit to the control circuit.

[0030] In a possible design, the control circuit 40 is further used to monitor in real time through the current sampling circuit whether the inductor current value on the energy storage circuit reaches a set inductor current peak value after controlling the first transistor to turn on. When it is monitored that the inductor current value on the first inductor reaches the set inductor current peak value, a shutdown drive signal is output to the control end of the first transistor to control the first transistor to turn off.

[0031] In a third aspect, the present application further provides a chip, wherein the chip includes the peak current generating circuit as described in any one of the above items, or the chip includes the converter as described in the above items.

[0032] In a fourth aspect, the present application further provides an electronic device, wherein the electronic device includes the peak current generating circuit as described in any one of the above items, or the electronic device includes the converter as described above.

[0033] According to the peak current generating circuit provided in the first aspect above, the peak current generating circuit is used in the converter to generate an adaptive inductor current peak value. The peak current generating circuit includes an output voltage sampling circuit, a reference voltage generating circuit, an adjustment signal generating circuit and a current regulating circuit; the output voltage sampling circuit is used to sample the output voltage at the output end of the power supply circuit; the reference voltage generating circuit is used to generate a first reference voltage and a second reference voltage, the first reference voltage and the second reference voltage are both less than the input voltage, and the second reference voltage is greater than the first reference voltage; the adjustment signal generating circuit is used to generate a first adjustment signal when it is determined that the first reference voltage and the second reference voltage are both less than the output voltage; and to generate a second adjustment signal when it is determined that the first reference voltage and the second reference voltage are both greater than the output voltage; the current regulating circuit is used to increase the current value of the output current according to the first adjustment signal, or to decrease the current value of the output current according to the second adjustment signal, and use the adjusted output current as the peak current of the energy storage circuit. In this way, the peak value of the inductor current can be adaptively adjusted according to the output voltage at the output end of the converter, so that the peak value of the inductor current can meet the current load demand of the converter, and can reduce the AC loss of the converter, thereby improving the working efficiency of the converter.

[0034] The beneficial effects provided in the above-mentioned other aspects and the possible designs of the above-mentioned other aspects can be referred to the beneficial effects brought about by the above-mentioned first aspect and the possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 One of the schematic diagrams of a converter structure provided in an embodiment of the present application;

[0036] Figure 2 A schematic diagram of the overall structure of a peak current generating circuit provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of the reference voltage generation circuit structure provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of the structure of the adjustment signal generating circuit provided in an embodiment of the present application;

[0039] Figure 5 A schematic diagram of the structure of a current regulating circuit provided in an embodiment of the present application;

[0040] Figure 6A schematic diagram of the specific structure of the peak current generating circuit provided in an embodiment of the present application;

[0041] Figure 7 This is a second schematic diagram of a converter structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0043] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0044] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0045] The transistor in the present application is a three-terminal transistor, and its three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor.

[0046] In the related art, the peak value of the converter's inductor current is usually set to a relatively large fixed value. Although this can meet the load capacity under different input voltage and output voltage combinations, for some input voltage and output voltage combinations, an excessively large peak value of the inductor current will increase the converter's AC loss, thereby resulting in lower converter operating efficiency.

[0047] In order to overcome the shortcomings of the above-mentioned related technologies, the present application provides a peak current generating circuit, which includes an output voltage sampling circuit, a reference voltage generating circuit, an adjustment signal generating circuit and a current regulating circuit; an output voltage sampling circuit, which is used to sample the output voltage at the output end of the power supply circuit; a reference voltage generating circuit, which is used to generate a first reference voltage and a second reference voltage, the first reference voltage and the second reference voltage are both less than the input voltage, and the second reference voltage is greater than the first reference voltage; an adjustment signal generating circuit, which is used to generate a first adjustment signal when it is determined that the first reference voltage and the second reference voltage are both less than the output voltage; and to generate a second adjustment signal when it is determined that the first reference voltage and the second reference voltage are both greater than the output voltage; a current regulating circuit, which is used to increase the current value of the output current according to the first adjustment signal, or to decrease the current value of the output current according to the second adjustment signal, and use the adjusted output current as the peak current of the energy storage circuit. In this way, the peak value of the inductor current can be adaptively adjusted according to the output voltage, so that the peak value of the inductor current can meet different load requirements and reduce the AC loss of the converter, thereby improving the working efficiency of the converter.

[0048] Figure 1 This is one of the schematic diagrams of a converter structure provided in the embodiment of the present application, see Figure 1 As shown, the converter includes an energy storage circuit 10 and a power supply circuit 20; the input end of the energy storage circuit 10 is used to receive an input voltage VIN, and the output end of the energy storage circuit 10 is connected to the input end of the power supply circuit 20; the output end of the power supply circuit 20 is used to connect a load; the energy storage circuit 10 is used to store energy when the power supply circuit 20 is in a closed state; the power supply circuit 20 is used to supply power to the load.

[0049] The energy storage circuit 10 includes a first transistor Q1 and a first inductor L1, wherein the first electrode of the first transistor Q1 is used to connect to a power supply to receive an input voltage VIN, the second electrode of the first transistor Q1 is connected to a first end of the first inductor L1, and the second end of the first inductor L1 is grounded; the first inductor L1 is used to store energy during the charging process. Specifically, in this embodiment, the first electrode of the first transistor Q1 is the input end of the energy storage circuit 10, and the first end of the first inductor L1 is the output end of the energy storage circuit 10.

[0050] The power supply circuit 20 includes a second transistor Q2 and a first capacitor C1, a first electrode of the second transistor Q2 is connected to a first end of the first inductor L1, a second electrode of the second transistor Q2 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded. Specifically, in this embodiment, the first electrode of the second transistor Q2 is an input end of the power supply circuit 20, and the first end of the first capacitor C1 is an output end of the power supply circuit 20.

[0051] Among them, the first transistor Q1 is also commonly referred to as a high-side power tube, and the second transistor Q2 is also commonly referred to as a low-side power tube. In the conduction phase of the first transistor Q1, the energy of the input voltage VIN will be stored in the first inductor L1. In this phase, the second transistor Q2 is in an off state, and the energy stored in the first capacitor C1 is used to power the load at the output end; in the conduction phase of the second transistor Q2, the energy stored in the first inductor L1 is used to power the load at the output end.

[0052] The control electrode of the first transistor Q1 and the control electrode of the second transistor Q2 are both connected to the control circuit to receive the driving signal output by the control circuit, so as to control the on and off of the first transistor Q1 and the second transistor Q2.

[0053] Specifically, the first transistor Q1 and the second transistor Q2 in the converter of this embodiment can both be NMOS (N-Metal-Oxide-Semiconductor) tubes. In other embodiments, the first transistor Q1 of this embodiment can also be PMOS (P-Metal-Oxide-Semiconductor) tubes. For example, when the first transistor Q1 and the second transistor Q2 are NMOS tubes, their first pole is the drain, their second pole is the source, and their control pole is the gate.

[0054] It should be noted that this embodiment is only based on Figure 1 The peak current generating circuit provided in the present application is described by taking the converter structure provided as an example, and is limited to the peak current generating circuit provided in the present application can only be applied to Figure 1 In the converter structure shown.

[0055] In addition, this embodiment Figure 1 The converter structure provided is a half-bridge Buck-boost circuit structure composed of two transistors. In other embodiments, the converter structure can also be a full-bridge Buck-boost circuit structure composed of four transistors; and the converter structure of this embodiment can also be specifically a Buck circuit or a boost circuit, which is not limited here.

[0056] Figure 2 For the overall structure diagram of the peak current generating circuit provided in the embodiment of the present application, please refer to Figure 2 As shown, the peak current generating circuit 200 of the present embodiment includes an output voltage sampling circuit 30 , a reference voltage generating circuit 21 , an adjustment signal generating circuit 22 and a current adjusting circuit 23 .

[0057] It should be noted that the output voltage sampling circuit 30 is used to sample the output voltage VO. In actual application scenarios, in order to facilitate logical calculations, the sampled output voltage VO can be amplified or reduced by a certain proportion during sampling to obtain a sampling signal VO_S. In this way, the sampling signal VO_S output by the output voltage sampling circuit 30 can represent the output voltage VO.

[0058] The output voltage sampling circuit 30 is used to sample the output voltage VO at the output end of the power supply circuit 20 to output the corresponding sampling signal VO_S; the reference voltage generating circuit 21 is used to generate a first reference voltage VIN1 and a second reference voltage VIN2, the first reference voltage VIN1 and the second reference voltage VIN2 are both less than the input voltage VIN, and the second reference voltage VIN2 is greater than the first reference voltage VIN1. The regulating signal generating circuit 22 is used to generate a first regulating signal when it is determined that the first reference voltage VIN1 and the second reference voltage VIN2 are both less than the sampling signal VO_S; and to generate a second regulating signal when it is determined that the first reference voltage VIN1 and the second reference voltage VIN2 are both greater than the sampling signal VO_S; the current regulating circuit 23 is used to increase the current value of the output current according to the first regulating signal, or decrease the current value of the output current according to the second regulating signal, and use the regulated output current as the peak current of the inductor current of the energy storage circuit 10.

[0059] It can be seen that according to the peak current generating circuit 200 provided in this embodiment, when the first reference voltage VIN1 and the second reference voltage VIN2 are both less than the sampling signal VO_S, the peak current of the inductor current of the energy storage circuit 10 is increased, and when the first reference voltage VIN1 and the second reference voltage VIN2 are both greater than the sampling signal VO_S, the peak current of the inductor current of the energy storage circuit 10 is decreased. In this way, under different combinations of input voltage VIN and sampling signal VO_S, the peak value of the inductor current can be made to be at the best adaptation value through continuous adjustment. Under the setting of the peak value of the inductor current, the load requirements of different loads can be met, and the AC loss of the converter can be reduced, thereby improving the working efficiency of the converter.

[0060] In one embodiment, the adjustment signal generating circuit 22 is further used to output a current holding signal when it is determined that the first reference voltage VIN1 is less than the sampling signal VO_S and the second reference voltage VIN2 is greater than the sampling signal VO_S; the current adjustment circuit 23 is used to maintain the output current after the last adjustment as the peak current of the energy storage circuit according to the current holding signal.

[0061] It can be understood that when it is detected that the sampling signal VO_S output by the converter is greater than the first reference voltage VIN1 and less than the second reference voltage VIN2, it means that the current peak value of the inductor current of the converter is in a certain proportional relationship with the sampling signal VO_S and the input voltage VIN, and the converter system is in the best stable state, then there is no need to adjust the peak value of the inductor current, that is, maintain the output current after the last adjustment as the peak current of the energy storage circuit.

[0062] In one embodiment, the reference voltage generating circuit 21 is further used to increase the first reference voltage VIN1 and the second reference voltage VIN2 according to the first adjustment signal, and to decrease the first reference voltage VIN1 and the second reference voltage VIN2 according to the second adjustment signal.

[0063] It is understandable that in one application scenario, when it is detected that the first reference voltage VIN1 and the second reference voltage VIN2 are both less than the sampling signal VO_S, it indicates that the sampling signal VO_S at the output end of the converter has not yet reached the required target voltage, so it is necessary to increase the first reference voltage VIN1 and the second reference voltage VIN2 according to the first adjustment signal. In another application scenario, when it is detected that the first reference voltage VIN1 and the second reference voltage VIN2 are both greater than the sampling signal VO_S, it indicates that the sampling signal VO_S at the output end of the converter is greater than the required target voltage, so it is necessary to decrease the first reference voltage VIN1 and the second reference voltage VIN2 according to the second adjustment signal. In this way, the output voltage VO of the converter output can be gradually adjusted to the target voltage, and the peak value of the inductor current can be adjusted at the same time to adapt to the current input voltage VIN and output voltage VO.

[0064] It can be understood that, in the present embodiment, the voltage value difference between the first reference voltage VIN1 and the second reference voltage VIN2 is relatively small. By comparing the sampling signal VO_S output by the converter with the first reference voltage VIN1 and the second reference voltage VIN2 respectively, so that the sampling signal VO_S is located between the first reference voltage VIN1 and the second reference voltage VIN2 as defined in the range, it is equivalent to continuously adjusting the input voltage VIN and the output voltage VO, and at the same time adaptively adjusting the input voltage VIN and the output voltage VO to the most suitable inductance circuit peak value, thereby ensuring that the load requirements of different loads can be met and the AC loss of the converter can be reduced, thereby improving the working efficiency of the converter.

[0065] In one embodiment, the reference voltage generating circuit 21 can be a voltage divider circuit, which includes a plurality of different voltage divider output terminals to output voltage values ​​at a plurality of voltage divider points, so that different voltages can be outputted at different voltage divider output terminals. Specifically, the input terminal of the reference voltage generating circuit 21 of this embodiment is used to receive the input voltage VIN, and the output terminal of the reference voltage generating circuit 21 is grounded GND; a plurality of voltage divider resistors are sequentially connected in series between the input terminal and the output terminal of the reference voltage generating circuit 21, and a reference voltage output terminal is provided at the input terminal of each voltage divider resistor, and different reference voltage output terminals are used to output reference voltages. Among them, the voltage divider resistor corresponding to the second reference voltage VIN2 is close to the input terminal of the reference voltage generating circuit 21, and the voltage divider voltage corresponding to the first reference voltage VIN1 is close to the output terminal of the reference voltage generating circuit 21.

[0066] Figure 3 For a schematic diagram of the reference voltage generation circuit structure provided in the embodiment of the present application, see Figure 3 As shown, the input end of the reference voltage generating circuit 21 is used to receive the input voltage VIN, the output end of the reference voltage generating circuit 21 is grounded GND, and 18 voltage-dividing resistors are connected in series between the input end and the output end of the reference voltage generating circuit 21. The 18 voltage-dividing resistors are respectively a resistor R1 and 17 resistors R0. The resistance values ​​of the 17 resistors R0 are the same. For ease of understanding, it can be considered that the resistance value of the resistor R1 is R1, and the resistance value of the resistor R0 is R0. Among them, a reference voltage output end is provided on the input end of each voltage-dividing resistor, and different reference voltage output ends are used to output reference voltages, such as Figure 3As shown, the reference voltage generating circuit 21 has 17 reference voltage output terminals, and the 17 reference voltage output terminals are respectively VIN <0> 、VIN <1> ……VIN <16> The 17 reference voltage output terminals respectively output different reference voltages, wherein the closer the reference voltage output terminal is to the input terminal of the reference voltage generating circuit 21, the greater the output voltage value. For example, the voltage dividing resistor corresponding to the second reference voltage VIN2 is close to the input terminal of the reference voltage generating circuit 21, and the voltage dividing voltage corresponding to the first reference voltage VIN1 is close to the output terminal of the reference voltage generating circuit 21.

[0067] Generally, the resistance of resistor R1 is much larger than the resistance of each resistor R0, so that the voltage division of resistor R1 accounts for a larger proportion, and the voltage division on each resistor R0 is smaller. In this way, when different reference voltage output terminals are selected to be turned on, the change amplitude of the output reference voltage will not be too large, thereby improving the adjustment speed and accuracy of the optimal peak current.

[0068] Figure 4 For a schematic diagram of the structure of the adjustment signal generating circuit provided in the embodiment of the present application, please refer to Figure 4 As shown, the adjustment signal generating circuit 22 includes a first latch comparator CMP1, a second latch comparator CMP2, an XNOR gate XNOR, an AND gate and a counter COUNTER.

[0069] Among them, the output end of the first latch comparator CMP1 is connected to the counting control pin UP of the counter COUNTER; the output ends of the first latch comparator CMP1 and the second latch comparator CMP are connected to the input end of the XNOR gate XNOR, the output end of the XNOR gate XNOR is connected to the first input end of the AND gate and, the second input end of the AND gate and is used to receive the lower tube drive signal LSON, and the output end of the AND gate and is connected to the clock input pin CLK of the counter COUNTER.

[0070] For example, in this embodiment, the output voltage VO is amplified by K times to obtain a sampling signal VO_S corresponding to the output voltage VO, that is, the sampling signal VO_S is a voltage signal proportional to the absolute value of the output voltage VO, so it can represent the output voltage VO.

[0071] Specifically, the counter COUNTER of this embodiment is an UP-DOWN counter. If the signal input to the UP pin is 1, the counter COUNTER counts forward once at the rising edge of the CLK pin signal. If the signal input to the UP pin is 0, the counter COUNTER counts backward once at the rising edge of the CLK pin signal.

[0072] The positive input terminal of the first latch comparator CMP1 is used to receive the sampling signal VO_S corresponding to the output voltage VO, the negative input terminal of the first latch comparator CMP1 is used to receive the first reference voltage VIN1, and the first latch comparator CMP1 is used to output a first logic signal when it is determined that the first reference voltage VIN1 is less than the sampling signal VO_S, that is, the logic state of the first logic signal is 1. The positive input terminal of the second latch comparator CMP2 is also used to receive the sampling signal VO_S, and the negative input terminal of the second latch comparator CMP2 is used to receive the second reference voltage VIN2. The second latch comparator CMP2 is used to output a second logic signal when it is determined that the second reference voltage VIN2 is less than the sampling signal VO_S; the XNOR gate XNOR and the AND gate and are used to calculate the first logic signal, the second logic signal and the lower tube drive signal LSON to obtain the first clock signal CLK1; the counter COUNTER is used to output a first adjustment signal according to the first clock signal and the first logic signal.

[0073] Among them, the first latch comparator CMP1 and the second latch comparator CMP2 are also used to receive an enable signal HSON, which is also a drive signal of the first transistor Q1. When the enable signal HSON is at a high level, the first transistor Q1 is driven to turn on; at the same time, when the enable signal HSON is at a high level, the first latch comparator CMP1 and the second latch comparator CMP2 work.

[0074] It can be understood that when the first reference voltage VIN1 is less than the sampling signal VO_S, the first logic signal output by the first latch comparator CMP1 is high level, and when the second reference voltage VIN2 is less than the sampling signal VO_S, the second logic signal output by the second latch comparator CMP2 is also high level. At this time, the signal output by the XNOR gate is 1. When the lower tube drive signal LSON is 1, that is, when the drive signal LSON of the second transistor Q2 is 1, the first clock signal CLK1 output by the AND gate is 1. When the first logic signal corresponding to the input of the UP terminal of the counter COUNTER is high level, the counter COUNTER actively adds 1 and outputs the first adjustment signal after adding 1. The first adjustment signal is used to control the current value output by the current adjustment circuit 23.

[0075] In one application scenario, when the first latch comparator CMP1 is determined to be greater than the sampling signal VO_S corresponding to the output voltage VO, it is also used to output a third logic signal, and the logic state of the third logic signal is opposite to that of the first logic signal, that is, the third logic signal is at a low level; the second latch comparator CMP2 is used to output a fourth logic signal when it is determined that the second reference voltage VIN2 is greater than the sampling signal VO_S, and the logic state of the fourth logic signal is opposite to that of the second logic signal, that is, the logic state of the fourth logic signal is at a low level. The XNOR gate XNOR and the AND gate and are used to operate the third logic signal, the fourth logic signal and the lower tube drive signal LSON to obtain the second clock signal CLK2; the counter COUNTER is used to output the second adjustment signal according to the second clock signal CLK2 and the third logic signal.

[0076] It can be understood that when the first reference voltage VIN1 is greater than the sampling signal VO_S, the third logic signal output by the first latch comparator CMP1 is low level, and when the second reference voltage VIN2 is also greater than the sampling signal VO_S, the fourth logic signal output by the second latch comparator CMP2 is also low level. At this time, the signal output by the XNOR gate is 1. When the lower tube drive signal LSON is 1, that is, the drive signal LSON of the second transistor Q2 is 1, the second clock signal CLK1 output by the AND gate is 1. When the third logic signal corresponding to the input of the UP terminal of the counter COUNTER is low level, the counter COUNTER actively decreases by 1 and outputs the second adjustment signal after decreasing by 1. The second adjustment signal is used to control the current value output by the current adjustment circuit 23.

[0077] In one embodiment, the first latch comparator CMP1 is further used to output a first logic signal when it is determined that the first reference voltage VIN is less than the sampling signal VO_S, that is, the logic state of the output of the first latch comparator CMP1 is 1; the second latch comparator CMP2 is used to output a fourth logic signal when it is determined that the second reference voltage VIN2 is greater than the sampling signal VO_S; the XNOR gate XNOR and the AND gate and are used to operate the first logic signal, the fourth logic signal and the lower tube drive signal LSON to obtain a third clock signal CLK3; the counter COUNTER is used to output a current holding signal according to the third clock signal CLK3 and the first logic signal.

[0078] It can be understood that when the first reference voltage VIN1 is less than the sampling signal VO_S, the first logic signal output by the first latch comparator CMP1 is high level, and when the second reference voltage VIN2 is also greater than the sampling signal VO_S, the fourth logic signal output by the second latch comparator CMP2 is also low level. At this time, the signal output by the XNOR gate XNOR is 0. When the lower tube drive signal LSON is 1, that is, the drive signal LSON of the second transistor Q2 is 1, the third clock signal CLK3 output by the AND gate is 0. At this time, although the first logic signal corresponding to the input of the UP end of the counter COUNTER is high level, since the clock signal input by the counter COUNTER is 0, the counter COUNTER does not work, that is, the count does not increase or decrease, that is, the counter COUNTER outputs a current holding signal. The current holding signal is used to control the current regulating circuit 23 to maintain the current value output during the last regulation.

[0079] Please continue to see Figure 4 As shown, the adjustment signal generating circuit 22 also includes a first digital selector MUX1 and a second digital selector MUX2; the input ends of the first digital selector MUX1 and the second digital selector MUX2 are respectively connected to different reference voltage output ends on the reference voltage generating circuit 21, and the output ends of the first digital selector MUX1 and the second digital selector MUX2 are respectively connected to the input ends of the first latch comparator CMP1 and the second latch comparator CMP2; the input ends of the first digital selector MUX1 and the second digital selector MUX2 are also used to receive the first adjustment signal, the second adjustment signal or the current holding signal, and the input ends of the first digital selector MUX1 and the second digital selector MUX2 are adjusted to be connected to different reference voltage output ends according to the first adjustment signal, the second adjustment signal or the current holding signal, thereby outputting different reference voltages.

[0080] Specifically, the structures of the first selector MUX1 and the second selector MUX2 are the same. Figure 3 As shown, the first selector MUX1 includes 16 input pins, and the 16 input pins are respectively connected to the reference voltage output terminal VIN <0> 、VIN <1> ……VIN <15> The second selector MUX2 also includes 16 input pins, and these 16 input pins are respectively connected to the reference voltage output terminal VIN <1> 、VIN <1> ……VIN <16> The connections are corresponding, and one input pin corresponds to one reference voltage output terminal.

[0081] Among them, the control pins Q of the first digital selector MUX1 and the second digital selector MUX2 are both connected to the output end of the counter COUNTER. The first digital selector MUX1 and the second digital selector MUX2 can select the input pin with a higher voltage and the reference voltage output end to be turned on next time according to the first adjustment signal output by the counter COUNTER, so that the input first reference voltage VIN1 and the second reference voltage VIN2 increase. On the contrary, the first digital selector MUX1 and the second digital selector MUX2 can select the input pin with a lower voltage and the reference voltage output end to be turned on next time according to the second adjustment signal output by the counter COUNTER, so that the input first reference voltage VIN1 and the second reference voltage VIN2 decrease. Alternatively, the first digital selector MUX1 and the second digital selector MUX2 keep the current input pin and the reference voltage output end turned on according to the current holding signal output by the counter COUNTER, so that the input first reference voltage VIN1 and the second reference voltage VIN2 remain unchanged.

[0082] Figure 5 For a schematic diagram of the structure of the current regulation circuit provided in the embodiment of the present application, please refer to Figure 5 As shown, the current regulating circuit 23 includes a current output main circuit 24 and a current adjustable unit 231. The current adjustable unit 231 includes a plurality of current output branches arranged in parallel. The output end of each current output branch is connected to the output end of the current output main circuit 24. The current value outputted from each current output branch is different. The current adjustable unit 231 is used to receive a first regulating signal, a second regulating signal and a current holding signal, and control different current output branches to be turned on according to the first regulating signal, the second regulating signal or the current holding signal.

[0083] For details, see Figure 5 As shown, the first current value output by the current output main circuit 24 is I1, and the current adjustable unit 231 includes five current output branches. Assuming that the second current value output by the first current output branch is I0, the current values ​​output by the remaining four current output branches are 2I0, 4I0, 8I0, and 16I0, respectively. Each time when adjusting, at least one current output branch is turned on, and the sum of the current values ​​output by each current output branch and I1 output by the current output main circuit 24 is the peak current output after this adjustment.

[0084] Generally, the first current value I1 of the current output main circuit 24 is much larger than the current value I0 on each current output branch, so that the current value I0 accounts for a smaller proportion of the final output peak current. In this way, when adjusting the output peak current, when different current output branches are selected to be turned on, the change amplitude of the output peak current will not be too large, thereby improving the adjustment speed and accuracy of the optimal peak current.

[0085] Figure 6 For a specific structural diagram of the peak current generating circuit provided in the embodiment of the present application, please refer to Figure 6 As shown, the counts between the first digital selector MUX1, the second digital selector MUX2 and the counter COUNTER are all represented by a set of binary information. For example, if the count signal Q<4:0> output by the current counter COUNTER is 1000, the current regulating circuit 23 controls, and the corresponding flag bit of the current branch where 8I0 is located is 1, then the current branch where 8I0 is located is turned on, and the peak current output at this time is (I1+8I0). If the counter COUNTER outputs the first regulating signal at this time, then in the next cycle, the count signal Q<4:0> counts forward once, that is, the count signal Q<4:0> is 1001 at this time, then the binary 1001 is converted into a decimal signal of 9, and the first digital selector MUX1 controls the reference voltage output pin VIN <8> The second selector MUX2 controls the reference voltage output pin VIN. <9> On the contrary, if the counter COUNTER outputs the second adjustment signal at this time, then in the next cycle, the counting signal Q<4:0> counts backward once, that is, the counting signal Q<4:0> is 0111 at this time, then the binary 0111 is converted into a decimal signal of 7, then the first selector MUX1 controls the reference voltage output pin VIN <7> The second selector MUX2 controls the reference voltage output pin VIN. <8> Conductivity.

[0086] It should be noted that, through the above-mentioned gating design, the second reference voltage VIN2 is always greater than the first reference voltage VIN1. Therefore, when the sampling signal VO_S is compared with the first reference voltage VIN1 and the second reference voltage VIN2, one of the first reference voltage VIN1 and the second reference voltage VIN2 will always be flipped first, and then the output signal is latched, which avoids the counter COUNTER flipping again in the next cycle and causing the code value to add and subtract back and forth at the ideal value, thereby causing the control response speed of the converter to be slow.

[0087] Please continue to combine Figure 6 As shown in the figure, the converter will definitely work in DCM mode. Therefore, when the converter system works in the junction of continuous conduction mode (CCM) and DCM mode, the load current corresponding to the converter is the maximum load current that can be reached by the peak value of the inductor current. Taking the buck-boost converter system as an example, only the low-side power tube (i.e. Figure 1The power stage can only provide charge to the output during the period when the second transistor Q2 in the converter is turned on. However, the peak current of the inductor in this converter system cannot be adjusted according to the loop. When the converter system is at the junction of CCM and DCM, the conduction time of the low-side power tube has reached the upper limit. Therefore, the converter system can no longer provide a larger load capacity. Taking the structure suitable for buck-boost converter as an example, the relationship between the maximum load current ILOAD, the inductor peak current IP, the input voltage VIN and the output voltage absolute value VO in the DCM mode can be expressed as:

[0088]

[0089] From the relationship shown in the above formula (1), it can be seen that the inductor peak current IP is related to the ratio of the maximum load current ILOAD, the output voltage VO and the input voltage VIN. In the actual design process, the ILOAD in the above formula can be taken as the maximum load current that the converter can reach. In this way, the inductor current peak IP can be generated according to different input voltages VIN and set output voltages VO, so as to achieve the above balance between load capacity and power consumption.

[0090] According to this embodiment Figure 6 The peak current generation circuit structure provided is as follows, where VIN is the converter input voltage; HSON is the high-side power tube drive start signal, that is, HSON is Figure 1 The drive signal of the first transistor Q1 in the converter circuit shown in FIG. 1 is LSON, which is the low-side power transistor start signal. Figure 1 The driving signal of the first transistor Q1 in the converter circuit shown is VO_S, which is a signal proportional to the absolute value of the output voltage: VO_S=k*VO, where VO is the absolute value of the output voltage.

[0091] Please continue to see Figure 6 As shown, the reference voltage generating circuit 21 provided in this embodiment has 17 resistors with a resistance value of R0 connected in series, VIN <m>=VIN*(m*R0) / [R1+17*R0]; the first digital selector MUX1 and the second digital selector MUX2 are 5-bit digital selectors. If the binary code value corresponding to the counting signal Q<4:0> is converted into a decimal value m, the first reference low voltage VIN1 = VIN <m>, the second reference voltage VIN2 = VIN<m+1> ; The clock signals of the first latch comparator CMP1 and the second latch comparator CMP2 are the lower tube drive signal HSON, and the second input end of the AND gate receives the lower tube drive signal LSON. The UP-DOWN COUNTER is a counter that can increase or decrease the output binary code value Q<4:0> by one bit cycle by cycle according to the UP signal. The output current IPEAK of the current regulating circuit 23 on the far right can control the peak value IP of the inductor current, and IPEAK is proportional to IP, IPEAK=I1+m*I0.

[0092] When the rising edge of the upper tube drive signal HSON arrives, the first latch comparator CMP1 and the second latch comparator CMP2 will compare the sampling signal VO_S with the first reference voltage VIN1 and the second reference voltage VIN2. If the first reference voltage VIN1 and the second reference voltage VIN2 are both less than the sampling signal VO_S at this time, the outputs of the first latch comparator CMP1 and the second latch comparator CMP2 are both high level, that is, the input signal of the count control pin UP of the counter COUNTER is high level, and the XNOR gate XNOR outputs a high level to control the AND gate AND to open. When the low-side power tube Q2 is turned on, the clock input pin CLK of the counter COUNTER receives the first clock signal CLK1, and the first clock signal CLK1 triggers the rising edge to control the counter COUNTER to count forward once, and the counting signal Q<4:0> increases by one bit, thereby controlling the first reference voltage VIN1, the second reference voltage VIN2 and the output current IPEAK to increase by one bit. After several working cycles, the second reference voltage VIN2 will rise to the sampling signal VO_S before the first reference voltage VIN1. At this time, it is considered that the counting signal Q<4:0> has reached the ideal value, the output voltage of the second latch comparator CMP2 becomes low level, and the output voltage of the first latch comparator CMP1 is still high level. In order to prevent the counter COUNTER from flipping again in the next cycle and causing the code value to add and subtract back and forth at the ideal value, the XNOR gate XNOR outputs a low level to control the AND gate and shield the lower tube drive signal LSON, thereby ensuring that the counter COUNTER no longer counts. Since the first reference voltage VIN1 and the first reference voltage VIN1 have a small change in adjacent code values, they can be approximately regarded as VIN <m>≈VIN<m+1> , that is, VIN <m>=VO_S, so the relationship between IPEAK, VIN and VO can be expressed as:

[0093]

[0094] In the above formula (2), the first current I1, the second current I0, the coefficient k, the resistor R1 and the resistor R0 are all constants. According to the maximum load current required by the specific application scenario, the above constants are reasonably designed to ensure that this formula (2) is the same as the above formula (1), that is, the inductor peak current IP and the maximum load current ILOAD, the output voltage VO and the input voltage VIN are in a fixed ratio. In this way, the best adapted inductor current peak IP can be set according to different input voltage VIN and output voltage VO setting values. Under the setting of the inductor current peak IP, the load requirements of different loads can be met, and the AC loss of the converter can be reduced, thereby improving the working efficiency of the converter.

[0095] When the rising edge of the upper tube drive signal HSON arrives, the first latch comparator CMP1 and the second latch comparator CMP2 will compare the sampling signal VO_S with the first reference voltage VIN1 and the second reference voltage VIN2. If the first reference voltage VIN1 and the second reference voltage VIN2 are both greater than the sampling signal VO_S at this time, the outputs of the first latch comparator CMP1 and the second latch comparator CMP2 are both low level, that is, the input signal of the count control pin UP of the counter COUNTER is low level, and the XNOR gate XNOR outputs a high level to control the AND gate AND to open. When the low-side power tube Q2 is turned on, the clock input pin CLK of the counter COUNTER receives the second clock signal CLK2, and the second clock signal CLK2 triggers the rising edge to control the counter COUNTER to count backward once, and the counting signal Q<4:0> is reduced by one bit, thereby controlling the first reference voltage VIN1, the second reference voltage VIN2 and the output current IPEAK to be reduced by one bit. After several working cycles, the first reference voltage VIN1 will drop to the sampling signal VO_S before the second reference voltage VIN2. At this time, it is considered that the counting signal Q<4:0> has reached the ideal value, the output voltage of the first latch comparator CMP1 becomes high level, and the output voltage of the second latch comparator CMP2 is still low level. In order to prevent the counter COUNTER from flipping again in the next cycle and causing the code value to add and subtract back and forth at the ideal value, the XNOR gate XNOR outputs a low level to control the AND gate and shield the lower tube drive signal LSON, thereby ensuring that the counter COUNTER no longer counts.

[0096] In one embodiment, in order to improve the calculation accuracy of the peak current generating circuit, the number of bits of the counting signal Q can be increased, for example, the 16-bit code value of the present embodiment is increased to 32 bits. The number of series resistors in the corresponding reference voltage generating circuit 21 is also increased to 33, so that the reference voltage generating circuit 21 has 33 reference voltage output terminals, so that the voltage difference outputted from adjacent reference voltage output terminals is small, so that the reference voltage amplitude adjusted each time is also smaller, so that the converter output voltage VO can be limited to a relatively small voltage range through the first reference voltage VIN1 and the second reference voltage VIN2, that is, the first reference voltage VIN1 and the second reference voltage VIN2 are closer to the output voltage VO, and the voltage regulation accuracy is improved. Correspondingly, the current output branch included in the current adjustable unit 231 in the current regulating circuit 23 also needs to be expanded to 6, so that the current granularity on the current output branch is divided finer, that is, the adjustment amount of the output current is smaller when the current is increased by one bit or decreased by one bit, so that the peak current outputted in the end is closer to the ideal value.

[0097] It can be seen that according to the peak current generating circuit provided in this embodiment, a dual latch comparator structure of a first latch comparator CMP1 and a second latch comparator CMP2 is used to realize the comparison between the output voltage VO and the reference voltage, so that the comparison result flips faster and the average power consumption is smaller; and, in this embodiment, the first selector MUX1, the second selector MUX2 and the counter COUNTER are all digital circuits, so the power consumption they consume is also relatively small, so that the overall power consumption of the peak current generating circuit of this embodiment is lower.

[0098] Figure 7 The second schematic diagram of a converter structure provided in the embodiment of the present application is shown in FIG. Figure 7 As shown, the converter includes an energy storage circuit 10, a power supply circuit 20, a current sampling circuit 50 and a control circuit 40. The input end of the energy storage circuit 10 is used to receive the input voltage VIN, and the output end of the energy storage circuit 10 is connected to the input end of the power supply circuit 20; the output end of the power supply circuit 20 is used to connect the load; the energy storage circuit 10 is used to store energy when the power supply circuit 20 is in a closed state; the power supply circuit 20 is used to discharge the load when the energy storage circuit 10 is in a closed state. The energy storage circuit 10 includes a first transistor Q1 and a first inductor L1, the first electrode of the first transistor Q1 is used to connect to the power supply to receive the input voltage VIN, the second electrode of the first transistor Q1 is connected to the first end of the first inductor L1, and the second end of the first inductor L1 is grounded; the first inductor L1 is used to store energy during the charging process. Specifically, in this embodiment, the first electrode of the first transistor Q1 is the input end of the energy storage circuit 10, and the first end of the first inductor L1 is the output end of the energy storage circuit 10. The power supply circuit 20 includes a second transistor Q2 and a first capacitor C1, a first electrode of the second transistor Q2 is connected to a first end of the first inductor L1, a second electrode of the second transistor Q2 is connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is grounded. Specifically, in this embodiment, the first electrode of the second transistor Q2 is an input end of the power supply circuit 20, and the first end of the first capacitor C1 is an output end of the power supply circuit 20. The control electrode of the first transistor Q1 and the control electrode of the second transistor Q2 are both connected to the control circuit 40 to receive a driving signal output by the control circuit, thereby controlling the conduction and disconnection of the first transistor Q1 and the second transistor Q2.

[0099] Specifically, the first transistor Q1 and the second transistor Q2 in the converter of this embodiment can both adopt NMOS (N-Metal-Oxide-Semiconductor) tubes. When the first transistor Q1 and the second transistor Q2 adopt NMOS tubes, their first pole is the drain, their second pole is the source, and their control pole is the gate.

[0100] The control circuit 40 of this embodiment includes the peak current generating circuit 200 provided in the above embodiments. The control circuit 40 is used to adjust the peak value IP of the inductor current in the energy storage circuit 10 according to the current IPEAK output by the peak current generating circuit 200 .

[0101] The output voltage sampling circuit 30 in the peak current generating circuit 200 is used to sample the output voltage VO, and the sampled voltage VO_S outputted from its output terminal can represent the output voltage VO. At the same time, the output terminal of the output voltage sampling circuit 30 is connected to the positive input terminals of the first latch comparator CMP1 and the second latch comparator CMP2 in the peak current generating circuit 200, so as to output the sampled output voltage VO to the first latch comparator CMP1 and the second latch comparator CMP2.

[0102] Also, see Figure 2 As shown, the peak current generating circuit 200 of this embodiment further includes a reference voltage generating circuit 21, an adjusting signal generating circuit 22 and a current adjusting circuit 23. The output voltage sampling circuit 30 is used to sample the output voltage VO at the output end of the power supply circuit 20; the reference voltage generating circuit 21 is used to generate a first reference voltage VIN1 and a second reference voltage VIN2, the first reference voltage VIN1 and the second reference voltage VIN2 are both less than the input voltage VIN, and the second reference voltage VIN2 is greater than the first reference voltage VIN1. The adjusting signal generating circuit 22 is used to generate a first adjusting signal when it is determined that the first reference voltage VIN1 and the second reference voltage VIN2 are both less than the sampling signal VO_S; and to generate a second adjusting signal when it is determined that the first reference voltage VIN1 and the second reference voltage VIN2 are both greater than the sampling signal VO_S; the current adjusting circuit 23 is used to increase the current value of the output current according to the first adjusting signal, or decrease the current value of the output current according to the second adjusting signal, and use the adjusted output current as the peak current of the inductor current of the energy storage circuit 10.

[0103] In one embodiment, the adjustment signal generating circuit 22 is further used to output a current holding signal when it is determined that the first reference voltage VIN1 is less than the sampling signal VO_S and the second reference voltage VIN2 is greater than the sampling signal VO_S; the current adjustment circuit 23 is used to maintain the output current after the last adjustment as the peak current of the energy storage circuit according to the current holding signal.

[0104] In one embodiment, the reference voltage generating circuit 21 is further used to increase the first reference voltage VIN1 and the second reference voltage VIN2 according to the first adjustment signal, and to decrease the first reference voltage VIN1 and the second reference voltage VIN2 according to the second adjustment signal.

[0105] The reference voltage generating circuit 21, the regulating signal generating circuit 22 and the current regulating circuit 23 provided in this embodiment can refer to the description of the above embodiments, and will not be described in detail here.

[0106] The converter of this embodiment further includes a current sampling circuit 50 , which is used to collect the inductor current value on the energy storage circuit 10 and output the sampled inductor current value on the energy storage circuit 10 to the control circuit 40 .

[0107] In one working condition, the control circuit 40 of this embodiment first outputs an upper tube drive signal HSON to the control terminal KQ1 of the first transistor Q1 to control the first transistor Q1 to be turned on. After the first transistor Q1 is turned on, the input voltage VIN charges the first inductor L1, so that the inductor current on the first inductor L1 continues to increase.

[0108] The control circuit 40 of this embodiment is also used to monitor whether the inductor current value on the energy storage circuit 10 reaches the set inductor current peak IP in real time through the current information transmitted by the current sampling circuit 50 after the first transistor Q1 is turned on. When the inductor current value on the first inductor L1 reaches the set inductor current peak IP, it is determined that the charging of the first inductor L1 is completed, and a shutdown drive signal is output to the control terminal KQ1 of the first transistor Q1 to control the first transistor Q1 to turn off. In addition, while controlling the first transistor Q1 to turn off, the control circuit 40 of this embodiment is also used to output a lower tube drive signal LSON to the control electrode KQ2 of the second transistor Q2 to drive the second transistor Q2 to turn on, so that the first inductor L1 can supply power to the load at the output end. When the control circuit 40 monitors that the inductor current is reduced to 0A, it is determined that the discharge of the first inductor L1 is completed, and the second transistor Q2 is controlled to be turned off, and then the first capacitor C1 can continue to discharge the load.

[0109] When the first reference voltage VIN1 and the second reference voltage VIN2 are both less than the sampling signal VO_S, the peak current of the inductor current of the energy storage circuit 10 is increased, and when the first reference voltage VIN1 and the second reference voltage VIN2 are both greater than the sampling signal VO_S, the peak current of the inductor current of the energy storage circuit 10 is decreased. In this way, under different combinations of input voltage VIN and output voltage VO, the peak value of the inductor current can be kept at the best adaptation value through continuous adjustment. Among them, the control circuit 40 of this embodiment also receives the adjusted inductor current peak IP output by the peak current generating circuit 200 in each cycle, and uses the adjusted inductor current peak IP as the inductor current peak IP of the first inductor L1 during a working cycle. In this way, under the current combination of input voltage VIN and output voltage VO, the most ideal inductor current peak IP can be adaptively matched and set, that is, the load requirements of different loads can be met, and the AC loss of the converter can be reduced, thereby improving the working efficiency of the converter.

[0110] In an application scenario, when the load at the output end of the converter changes, the output voltage VO outputted from the output end of the converter will also change accordingly. The peak current generating circuit 200 provided in this embodiment can continuously adjust the inductor current peak IP of the first inductor L1 according to the changed output voltage VO, so that after multiple working cycles, the counter COUNTER outputs a current holding signal, thereby maintaining the inductor current peak IP in the most ideal state.

[0111] In addition, based on the peak current generating circuit 20 provided in the above embodiments, the embodiment of the present application further provides a chip, which includes the peak current generating circuit 20 provided in the above embodiments. Alternatively, in another embodiment, the chip includes the converter circuit provided in the above embodiments.

[0112] On the basis of the above embodiments, an embodiment of the present application further provides an electronic device, which includes a peak current generating circuit 20 as provided in the above embodiments; or, in other embodiments, the electronic device includes a converter circuit as provided in the above embodiments; or in other embodiments, the electronic device includes a chip as provided in the above embodiments.

[0113] The electronic device in this embodiment may be a power adapter, a smart phone, a tablet computer, a laptop computer, or other electronic device.

[0114] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.< / m> < / m> < / m> < / m>

Claims

1. A peak current generating circuit, used in a converter, the converter comprising an energy storage circuit and a power supply circuit; the input end of the energy storage circuit is used to receive an input voltage, the output end of the energy storage circuit is connected to the input end of the power supply circuit; the output end of the power supply circuit is used to connect a load; the energy storage circuit is used to store energy when the power supply circuit is in a closed state; the power supply circuit is used to supply power to the load; It is characterized in that The peak current generating circuit comprises an output voltage sampling circuit, a reference voltage generating circuit, an adjustment signal generating circuit and a current regulating circuit; The output voltage sampling circuit is used to sample the output voltage at the output end of the power supply circuit; The reference voltage generating circuit is used to generate a first reference voltage and a second reference voltage, wherein the first reference voltage and the second reference voltage are both lower than the input voltage, and the second reference voltage is higher than the first reference voltage; The regulating signal generating circuit is used to generate a first regulating signal when it is determined that both the first reference voltage and the second reference voltage are smaller than the output voltage; and generating a second adjustment signal when it is determined that both the first reference voltage and the second reference voltage are greater than the output voltage; The current regulating circuit is used to increase the current value of the output current according to the first regulating signal, or to decrease the current value of the output current according to the second regulating signal, and to use the regulated output current as the peak current of the energy storage circuit.

2. The peak current generating circuit according to claim 1, characterized in that: The regulating signal generating circuit is further configured to output a current holding signal when it is determined that the first reference voltage is less than the output voltage and the second reference voltage is greater than the output voltage; The current regulating circuit is used to maintain the output current adjusted last time as the peak current of the energy storage circuit according to the current holding signal.

3. The peak current generating circuit according to claim 1 or 2, characterized in that: The reference voltage generating circuit is further used for increasing the first reference voltage and the second reference voltage according to the first adjusting signal, and decreasing the first reference voltage and the second reference voltage according to the second adjusting signal.

4. The peak current generating circuit according to claim 3, characterized in that: The input end of the reference voltage generating circuit is used to receive the input voltage, and the output end of the reference voltage generating circuit is grounded; A plurality of voltage-dividing resistors are sequentially connected in series between the input and output ends of the reference voltage generating circuit, and a reference voltage output end is provided on the input end of each voltage-dividing resistor, and different reference voltage output ends are used to output reference voltages; The voltage-dividing resistor corresponding to the second reference voltage is close to the input end of the reference voltage generating circuit, and the voltage-dividing voltage corresponding to the first reference voltage is close to the output end of the reference voltage generating circuit.

5. The peak current generating circuit according to claim 4, characterized in that: The adjustment signal generating circuit includes a first latch comparator, a second latch comparator, an XNOR gate, an AND gate and a counter; The output end of the first latch comparator is connected to the count control pin of the counter; the output ends of the first latch comparator and the second latch comparator are connected to the input end of the XNOR gate, the output end of the XNOR gate is connected to the first input end of the AND gate, the second input end of the AND gate is used to receive the lower tube drive signal, and the output end of the AND gate is connected to the clock input pin of the counter; The first latch comparator is used to output a first logic signal when it is determined that the first reference voltage is less than the output voltage; the second latch comparator is used to output a second logic signal when it is determined that the second reference voltage is less than the output voltage; the XOR gate and the AND gate are used to calculate the first logic signal, the second logic signal and the lower tube drive signal to obtain a first clock signal; the counter is used to output the first adjustment signal according to the first clock signal and the first logic signal; Alternatively, the first latch comparator is further used to output a third logic signal when it is determined that the first reference voltage is greater than the output voltage; the second latch comparator is used to output a fourth logic signal when it is determined that the second reference voltage is greater than the output voltage; the XNOR gate and the AND gate are used to operate the third logic signal, the fourth logic signal and the lower tube drive signal to obtain a second clock signal; the counter is used to output the second adjustment signal according to the second clock signal and the third logic signal.

6. The peak current generating circuit according to claim 5, characterized in that: The first latch comparator is further used to output a first logic signal when it is determined that the first reference voltage is less than the output voltage; the second latch comparator is used to output a fourth logic signal when it is determined that the second reference voltage is greater than the output voltage; the XOR gate and the AND gate are used to operate the first logic signal, the fourth logic signal and the lower tube drive signal to obtain a third clock signal; the counter is used to output the current holding signal according to the third clock signal and the first logic signal.

7. The peak current generating circuit according to claim 5, characterized in that: The adjustment signal generating circuit further includes a first digital selector and a second digital selector; The input ends of the first digital selector and the second digital selector are respectively connected to different reference voltage output ends of the reference voltage generating circuit, and the output ends of the first digital selector and the second digital selector are respectively connected to the input ends of the first latch comparator and the second latch comparator; The input ends of the first digital selector and the second digital selector are also used to receive the first adjustment signal, the second adjustment signal or the current holding signal, and the input ends of the first digital selector and the second digital selector are adjusted to be connected to different reference voltage output ends respectively according to the first adjustment signal, the second adjustment signal or the current holding signal, so as to output different reference voltages.

8. The peak current generating circuit according to claim 1 or 2, characterized in that: The current regulating circuit comprises a current output main circuit and a current adjustable unit, wherein the current adjustable unit comprises a plurality of current output branches arranged in parallel, the output end of each current output branch is connected to the output end of the current output main circuit, and the current value outputted by each current output branch is different; The current adjustable unit is used to receive the first adjustment signal, the second adjustment signal and the current holding signal, and control different current output branches to be turned on according to the first adjustment signal, the second adjustment signal or the current holding signal.

9. A converter, characterized in that: It includes an energy storage circuit, a power supply circuit and a control circuit; the input end of the energy storage circuit is used to receive an input voltage, and the output end of the energy storage circuit is connected to the input end of the power supply circuit; the output end of the power supply circuit is used to connect a load; the energy storage circuit is used to store energy when the power supply circuit is in a closed state; the power supply circuit is used to discharge the load when the energy storage circuit is in a closed state; The control circuit comprises a peak current generating circuit as described in any one of claims 1 to 8, and the control circuit is used to adjust the peak value of the inductor current in the energy storage circuit according to the peak current output by the peak current generating circuit.

10. A chip, characterized in that: The chip includes the peak current generating circuit according to any one of claims 1 to 8, or the chip includes the converter according to claim 9.

11. An electronic device, characterized in that: The electronic device comprises the peak current generating circuit according to any one of claims 1 to 8, or the electronic device comprises the converter according to claim 9.

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