A synchronous rectification circuit and a control method thereof

Abstract

The application relates to the technical field of synchronous rectification control, and relates to a synchronous rectification circuit and a control method thereof. The method comprises the following steps: in a first working phase, a first MOS tube, a fourth MOS tube and a fifth MOS tube are controlled to be turned on, and other MOS tubes are controlled to be turned off; in a second working phase, a full-bridge rectification circuit and a sixth MOS tube are controlled to be turned off, and the fifth MOS tube is controlled to be turned on; in a third working phase, the full-bridge rectification circuit is controlled to be turned off, and the fifth MOS tube and the sixth MOS tube are controlled to be turned on; in a fourth working phase, the full-bridge rectification circuit and the fifth MOS tube are controlled to be turned off, and the sixth MOS tube is controlled to be turned on; in a fifth working phase, a second MOS tube, a third MOS tube and the sixth MOS tube are controlled to be turned on, and other MOS tubes are controlled to be turned off; in a sixth working phase, the full-bridge rectification circuit and the fifth MOS tube are controlled to be turned off, and the sixth MOS tube is controlled to be turned on; in a seventh working phase, the full-bridge rectification circuit is controlled to be turned off, and the fifth MOS tube and the sixth MOS tube are controlled to be turned on; and in an eighth working phase, the full-bridge rectification circuit and the sixth MOS tube are controlled to be turned off, and the fifth MOS tube is controlled to be turned on. The application can reduce loss and improve efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of synchronous rectification control, in particular to a synchronous rectification circuit and a control method thereof. BACKGROUND

[0002] The synchronous rectification circuit is suitable for medium and high power occasions, which replaces the rectifier diode in general applications by using a synchronous rectification MOS tube, that is, the MOS tube is used for rectification on the secondary side of the transformer, which reduces the loss and improves the system efficiency compared with the rectification mode of the diode.

[0003] However, in the existing synchronous rectification mode using the MOS tube, the conduction and turn-off of the synchronous rectification MOS tube are completely synchronized and consistent with the opposite-angle MOS tube on the primary side, which causes the secondary side freewheeling inductor current to flow through the body diode of the synchronous rectification MOS tube, resulting in a large loss and reducing the system efficiency.

[0004] Therefore, the existing synchronous rectification mode using the MOS tube is not ideal in terms of loss and system efficiency, and needs to be further optimized. SUMMARY

[0005] The technical problem to be solved by the embodiments of the present application is to provide a synchronous rectification circuit and a control method thereof to solve the problem that the existing synchronous rectification mode using the MOS tube is not ideal in terms of loss and system efficiency.

[0006] The present application discloses a synchronous rectification control method applied to a synchronous rectification circuit, wherein the synchronous rectification circuit comprises a fifth MOS tube, a sixth MOS tube, a transformer, an inductor, an energy storage capacitor, and a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube connected to form a full-bridge rectification circuit, the same name end of the primary side of the transformer is connected to the middle node of the first MOS tube and the second MOS tube, the different name end of the primary side of the transformer is connected to the middle node of the third MOS tube and the fourth MOS tube, the fifth MOS tube is connected in parallel with the sixth MOS tube, the drain of the fifth MOS tube is connected to the different name end of the secondary side of the transformer, the drain of the sixth MOS tube is connected to the same name end of the secondary side of the transformer, the source of the fifth MOS tube and the source of the sixth MOS tube are both connected to the negative pole of the power output end, the inductor is connected in series between the tap end of the secondary side of the transformer and the positive pole of the power output end, the energy storage capacitor is connected in parallel between the positive pole and the negative pole of the power output end, and one switching cycle comprises a plurality of continuous working stages, the synchronous rectification control method comprises:

[0007] In the first working stage, the first MOS tube, the fourth MOS tube, and the fifth MOS tube are controlled to be turned on, and other MOS tubes are disconnected, so that the energy is transmitted from the primary side of the transformer to the secondary side;

[0008] In the second working phase, all MOSFETs and the sixth MOSFET of the full-bridge rectifier circuit are disconnected, and the fifth MOSFET is turned on to provide freewheeling current for the inductor.

[0009] In the third working stage, all MOSFETs of the full-bridge rectifier circuit are disconnected, and the fifth and sixth MOSFETs are turned on to provide freewheeling current for the inductor.

[0010] In the fourth operating phase, all MOSFETs and the fifth MOSFET of the full-bridge rectifier circuit are disconnected, and the sixth MOSFET is turned on to provide freewheeling current for the inductor.

[0011] In the fifth operating phase, the second, third, and sixth MOSFETs are turned on, while the other MOSFETs are turned off, transferring energy from the primary side of the transformer to the secondary side.

[0012] In the sixth operating phase, all MOSFETs and the fifth MOSFET of the full-bridge rectifier circuit are disconnected, and the sixth MOSFET is turned on to provide freewheeling current for the inductor.

[0013] In the seventh operating phase, all MOSFETs of the full-bridge rectifier circuit are disconnected, and the fifth and sixth MOSFETs are turned on to provide freewheeling current for the inductor.

[0014] In the eighth operating phase, all MOSFETs and the sixth MOSFET of the full-bridge rectifier circuit are disconnected, and the fifth MOSFET is turned on to provide freewheeling current for the inductor.

[0015] Optionally, a first driving signal is used to control the first MOSFET and the fourth MOSFET, a second driving signal is used to control the second MOSFET and the third MOSFET, a third driving signal is used to control the fifth MOSFET, and a fourth driving signal is used to control the sixth MOSFET. The first driving signal and the second driving signal are out of phase by 180°, the first driving signal and the third driving signal are complementary, and the second driving signal and the fourth driving signal are complementary.

[0016] Optionally, the maximum duty cycle of both the first drive signal and the second drive signal does not exceed 50%.

[0017] Optionally, the second, fourth, sixth, and eighth working stages are all the same in time.

[0018] Optionally, the synchronous rectification control method further includes:

[0019] The inductor current value is sampled and compared with a preset current value;

[0020] If the inductor current value is greater than the preset current value, a normal drive signal is generated to control the conduction state of the fifth MOSFET and the sixth MOSFET.

[0021] If the inductor current value is less than the preset current value, no drive signal is generated to disconnect the fifth MOSFET and the sixth MOSFET.

[0022] This invention also discloses a synchronous rectification circuit, which includes a main control chip, a fifth MOSFET, a sixth MOSFET, a transformer, an inductor, an energy storage capacitor, and a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET connected in a full-bridge rectifier circuit. The intermediate node of the first MOSFET and the second MOSFET is connected to the same-name terminal of the primary side of the transformer, and the intermediate node of the third MOSFET and the fourth MOSFET is connected to the opposite-name terminal of the primary side of the transformer. The fifth MOSFET and the sixth MOSFET are connected in parallel. The drain of the fifth MOSFET is connected to the opposite-name terminal of the secondary side of the transformer, and the drain of the sixth MOSFET is connected to the same-name terminal of the secondary side of the transformer. The sources of the fifth MOSFET and the sixth MOSFET are both connected to the negative terminal of the power supply output. The inductor is connected in series between the tap terminal of the secondary side of the transformer and the positive terminal of the power supply output. The energy storage capacitor is connected in parallel between the positive and negative terminals of the power supply output. The main control chip is connected to the gates of all MOSFETs and is controlled by the synchronous rectification control method as described in any one of claims 1-5.

[0023] Optionally, the synchronous rectification circuit further includes a current sampling unit, a current comparison unit, a wave-by-wave current limiting unit, and a driving unit. The current sampling unit is used to sample and acquire the inductor current and transmit it to the current comparison unit. The current comparison unit compares the received inductor current with a preset current value and outputs a wave-by-wave current limiting signal. The wave-by-wave current limiting unit generates a PWM signal based on the driving signal for the fifth and sixth MOSFETs output by the main control chip and the wave-by-wave current limiting signal. The driving unit generates a synchronous rectification driving signal based on the PWM signal to drive the fifth and sixth MOSFETs.

[0024] Optionally, the wave-by-wave current limiting unit includes a first Schmitt trigger, a second Schmitt trigger, a first AND gate, and a second AND gate. The clock input of the first Schmitt trigger receives the PWMH signal output by the main control chip, and its output is connected to the first input of the first AND gate. The clock input of the second Schmitt trigger receives the PWML signal output by the main control chip, and its output is connected to the first input of the second AND gate. The reset inputs of both the first and second Schmitt triggers receive the wave-by-wave current limiting signal output by the current comparison unit. The second input of the first AND gate receives the PWMH signal output by the main control chip, and the second input of the second AND gate receives the PWML signal output by the main control chip. The outputs of both the first and second AND gates are connected to the driving unit.

[0025] Optionally, the current sampling unit includes a sampling resistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first comparator. The sampling resistor is connected in series between the source of the fifth MOS transistor and the negative terminal of the power supply output. The first resistor is connected in series between one end of the sampling resistor and the non-inverting input of the first comparator. The second resistor is connected in series between the other end of the sampling resistor and the inverting input of the first comparator. The third resistor is connected in series between the external reference voltage point and the non-inverting input of the first comparator. The fourth resistor is connected in series between the output and inverting input of the first comparator. The output of the first comparator is also connected to the wave-by-wave current limiting unit.

[0026] Optionally, the wave-by-wave current limiting unit includes a second comparator, a fifth resistor, and a sixth resistor. The fifth resistor is connected in series between the output terminal of the first comparator and the non-inverting input terminal of the second comparator. The inverting input terminal of the second comparator is used to receive a preset current value. The sixth resistor is connected in series between the external power supply and the output terminal of the second comparator. The output terminal of the second comparator is also connected to the reset input terminals of the first Schmitt trigger and the second Schmitt trigger.

[0027] Compared with the prior art, the beneficial effects of the synchronous rectification circuit and its control method provided by the embodiments of the present invention are as follows: by dividing the switching cycle of the MOSFET into multiple continuous working stages, on the basis of normally controlling the energy transfer from the primary side to the secondary side of the transformer, the conduction time of the fifth and sixth MOSFETs is increased when all four MOSFETs on the primary side are turned off, so as to allow freewheeling current in the inductor. Furthermore, the dead time, namely the second, fourth, sixth, and eighth working stages, is reasonably increased in the control of the fifth and sixth MOSFETs to avoid short circuits and ensure reliable system operation. Compared with the existing method of turning off the MOSFETs and allowing freewheeling current through the body diodes of the MOSFETs, the losses are reduced and the system efficiency is improved. Attached Figure Description

[0028] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0029] Figure 1 This is a circuit diagram of an embodiment of the synchronous rectification circuit provided in this invention;

[0030] Figure 2 This is a flowchart illustrating an embodiment of the synchronous rectification control method provided in this invention.

[0031] Figure 3 This is a driving waveform diagram of driving the first to sixth MOS transistors in the synchronous rectification control method provided in the embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of another embodiment of the synchronous rectification circuit provided in this invention.

[0033] Figure 5 This is a circuit diagram showing the connection between the wave-by-wave current limiting unit and the main control chip and the driving unit provided in an embodiment of the present invention;

[0034] Figure 6 This is a circuit diagram showing the connection between the current sampling unit and the current comparison unit provided in an embodiment of the present invention.

[0035] The labels for the attached figures are as follows:

[0036] U1, Main control chip; Q1, First MOSFET; Q2, Second MOSFET; Q3, Third MOSFET; Q4, Fourth MOSFET; Q5, Fifth MOSFET; Q6, Sixth MOSFET; T1, Transformer; L1, Inductor; C1, Energy storage capacitor; Q1A, First Schmitt trigger; Q1B, Second Schmitt trigger; U1A, First AND gate; U1B, Second AND gate; R1, Sampling resistor; R2, First resistor; R3, Second resistor; R4, Third resistor; R5, Fourth resistor; R6, Fifth resistor; R7, Sixth resistor; U2A, First comparator; U2B, Second comparator; 110, Current sampling unit; 120, Current comparison unit; 130, Wave-by-wave current limiting unit; 140, Drive unit. Detailed Implementation

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0038] This invention provides a synchronous rectification control method, applied in a synchronous rectification circuit. (See reference...) Figure 1The synchronous rectifier circuit includes a fifth MOSFET Q5, a sixth MOSFET Q6, a transformer T1, an inductor L1, an energy storage capacitor C1, and a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, and a fourth MOSFET Q4 connected in a full-bridge rectifier circuit. The intermediate node of the first MOSFET Q1 and the second MOSFET Q2 is connected to the same-name terminal of the primary side of the transformer T1, and the intermediate node of the third MOSFET Q3 and the fourth MOSFET Q4 is connected to the opposite-name terminal of the primary side of the transformer T1. The fifth MOSFET Q5 and the sixth MOSFET Q6 are connected in parallel. The drain of the fifth MOSFET Q5 is connected to the opposite-name terminal of the secondary side of the transformer T1, and the drain of the sixth MOSFET Q6 is connected to the same-name terminal of the secondary side of the transformer T1. The sources of the fifth MOSFET Q5 and the sixth MOSFET Q6 are both connected to the negative terminal of the power output. The inductor L1 is connected in series between the tap terminal of the secondary side of the transformer T1 and the positive terminal of the power output. The energy storage capacitor C1 is connected in parallel between the positive and negative terminals of the power output.

[0039] The existing control method for synchronous rectification circuits is as follows: during the time period when all MOSFETs of the full-bridge rectifier are off, the fifth MOSFET Q5 and the sixth MOSFET Q6, which are responsible for synchronous rectification on the secondary side, are not conducting. The current in inductor L1 is freewheeled through the body diodes of the fifth MOSFET Q5 and the sixth MOSFET Q6. Half of the current in inductor L1 flows through the body diodes of the fifth MOSFET Q5 and the sixth MOSFET Q6. Moreover, the length of this time period increases with the increase of the input voltage, which leads to a longer time for the synchronous rectification freewheeling current to flow through the body diodes, resulting in greater conduction losses and lower system efficiency.

[0040] In this embodiment of the application, a switching cycle includes multiple consecutive operating phases, such as... Figure 1 and Figure 2 As shown, the synchronous rectification control method in this application includes:

[0041] S110, First working stage: Control the conduction of the first MOSFET Q1, the fourth MOSFET Q4 and the fifth MOSFET Q5, and disconnect the other MOSFETs to transfer energy from the primary side of transformer T1 to the secondary side;

[0042] S120, Second working stage: Control the disconnection of all MOSFETs and the sixth MOSFET Q6 in the full-bridge rectifier circuit, and control the conduction of the fifth MOSFET Q5 to provide freewheeling current for inductor L1;

[0043] S130, the third working stage, controls the disconnection of all MOSFETs in the full-bridge rectifier circuit, and controls the conduction of the fifth MOSFET Q5 and the sixth MOSFET Q6 to freewheel inductor L1;

[0044] S140, Fourth working stage: Control all MOSFETs and the fifth MOSFET Q5 of the full-bridge rectifier circuit to disconnect, and control the sixth MOSFET Q6 to turn on to provide freewheeling current for inductor L1;

[0045] S150, the fifth working stage, controls the conduction of the second MOSFET Q2, the third MOSFET Q3 and the sixth MOSFET Q6, and disconnects the other MOSFETs, transferring energy from the primary side of transformer T1 to the secondary side;

[0046] S160, the sixth working stage, controls the disconnection of all MOSFETs in the full-bridge rectifier circuit and the fifth MOSFET Q5, and controls the conduction of the sixth MOSFET Q6 to provide freewheeling current for inductor L1;

[0047] S170, the seventh working stage, controls the disconnection of all MOSFETs in the full-bridge rectifier circuit, and controls the conduction of the fifth MOSFET Q5 and the sixth MOSFET Q6 to provide freewheeling for inductor L1;

[0048] S180, the eighth operating stage, controls the disconnection of all MOSFETs in the full-bridge rectifier circuit and the sixth MOSFET Q6, and controls the conduction of the fifth MOSFET Q5 to provide freewheeling current for inductor L1.

[0049] This application divides the switching cycle of the MOSFET into multiple consecutive operating stages. While normally controlling the transfer of energy from the primary to the secondary side of transformer T1, it adds the conduction time of the fifth MOSFET Q5 and the sixth MOSFET Q6 when all four primary MOSFETs are off, allowing freewheeling current through inductor L1. Furthermore, it reasonably increases the dead time (the second, fourth, sixth, and eighth operating stages) in the control of the fifth MOSFET Q5 and the sixth MOSFET Q6 to avoid short circuits and ensure reliable system operation. Compared to existing methods that use the MOSFET's body diode for freewheeling when it is off, this reduces losses and improves system efficiency.

[0050] Specifically, in the first operating stage, the first MOSFET Q1 and the fourth MOSFET Q4 in the full-bridge rectifier circuit are turned on, and the input voltage is applied to the primary side of transformer T1. The voltage across transformer T1 is positive at the top and negative at the bottom. Based on the polarity of transformer T1, the fifth MOSFET Q5 on the secondary side is turned on, providing a current path for the input energy to be transferred to the secondary side. In the second operating stage, all four MOSFETs in the full-bridge rectifier circuit on the primary side of transformer T1 are turned off, the primary voltage of transformer T1 is 0, and the fifth MOSFET Q5 on the secondary side is turned on, providing freewheeling current to inductor L1. The sixth MOSFET Q6 on the secondary side is turned off, and no freewheeling current flows. In the third operating stage, all four MOSFETs in the full-bridge rectifier circuit on the primary side are turned off, the primary voltage of transformer T1 is 0, and the fifth MOSFET Q4... When MOSFETs Q5 and Q6 are simultaneously turned on, they provide freewheeling current to inductor L1, each providing half of the inductor L1 current freewheeling path. Because the inductor L1 current freewheeling path is divided into two parts, the voltage drop across each synchronous rectifier is halved, helping to reduce the power consumption and heat loss of each synchronous rectifier. In the fourth operating phase, all four MOSFETs in the full-bridge rectifier circuit are turned off, and the primary voltage of transformer T1 is 0. A dead time is set during this period to avoid short-circuiting the secondary side of transformer T1. During this time, all four MOSFETs in the primary side of the full-bridge rectifier circuit are turned off, and the sixth MOSFET Q6 on the secondary side is turned on, continuing to provide freewheeling current to inductor L1. In the first stage, the current in inductor L1 freewheels, and the fifth MOSFET Q5 on the secondary side is off, so there is no freewheeling current. In the second stage, the second and third MOSFETs Q2 and Q3 of the input full-bridge rectifier circuit are turned on, and the input voltage Vin is applied to the primary side of transformer T1. The voltage of transformer T1 is positive at the bottom and negative at the top. According to the polarity of transformer T1, the sixth MOSFET Q6 on the secondary side is turned on, providing a current path, and the input energy is transferred to the secondary side. In the sixth stage, all four MOSFETs of the primary full-bridge rectifier circuit are turned off, and the voltage of the primary side of transformer T1 is 0. During this period, a dead time is set to avoid short circuit on the secondary side of transformer T1. During this time, all four MOSFETs on the primary side are turned off, and the sixth MOSFET Q6 on the secondary side is turned on, allowing the current in inductor L1 to freewheel. In the seventh operating stage, all four MOSFETs in the primary-side full-bridge rectifier circuit are off, the primary voltage of transformer T1 is 0, and the fifth MOSFET Q5 and the sixth MOSFET Q6 are simultaneously turned on, providing freewheeling current to inductor L1, each providing half of the inductor L1 current freewheeling path; in the eighth operating stage, all four MOSFETs in the primary-side full-bridge rectifier circuit are off, the primary voltage of transformer T1 is 0, and a dead time is set during this period to avoid short circuit on the secondary side of transformer T1. During this time, all four primary-side MOSFETs are off, the fifth MOSFET Q5 on the secondary side is turned on, continuing to provide freewheeling current to inductor L1, and the sixth MOSFET Q6 on the secondary side is off, without freewheeling current.

[0051] In this embodiment, a first drive signal controls the first MOSFET Q1 and the fourth MOSFET Q4, a second drive signal controls the second MOSFET Q2 and the third MOSFET Q3, a third drive signal controls the fifth MOSFET Q5, and a fourth drive signal controls the sixth MOSFET Q6. The first drive signal and the second drive signal are 180° out of phase, and the conduction states of the first MOSFET Q1 and the fourth MOSFET Q4 are staggered from the conduction states of the second MOSFET Q2 and the third MOSFET Q3. The first drive signal and the third drive signal are complementary, and the second drive signal and the fourth drive signal are complementary, achieving synchronous rectification function with relatively simple control logic.

[0052] In an optional embodiment of this application, the maximum duty cycle of both the first drive signal and the second drive signal does not exceed 50% to prevent shoot-through of the upper and lower transistors on the primary side of transformer T1. Simultaneously, this reduces the switching losses of the corresponding MOSFETs and improves efficiency. Optionally, the maximum duty cycle of both the first drive signal and the second drive signal is 45%.

[0053] The driving waveforms of the first, second, third, and fourth driving signals are as follows: Figure 3 As shown in the figure. Among them, the time period T0-T1 corresponds to the first working stage, the time period T1-T2 corresponds to the second working stage, T2-T3 corresponds to the third working stage, T3-T4 corresponds to the fourth working stage, T4-T5 corresponds to the fifth working stage, T5-T6 corresponds to the sixth working stage, T6-T7 corresponds to the seventh working stage, and T7-T8 corresponds to the eighth working stage.

[0054] In an optional embodiment of this application, the times of the second, fourth, sixth, and eighth working stages are all the same. The times of the second, fourth, sixth, and eighth working stages are dead times set to avoid short circuits on the secondary side of transformer T1. Setting these dead times to be the same can simplify the control logic and reduce the complexity of the design.

[0055] In optional embodiments of this application, the synchronous rectification control method further includes:

[0056] Sample the current value of inductor L1 and compare it with the preset current value;

[0057] If the current value of inductor L1 is greater than the preset current value, a normal drive signal is generated to control the conduction state of the fifth MOSFET Q5 and the sixth MOSFET Q6.

[0058] If the current value of inductor L1 is less than the preset current value, no drive signal will be generated to disconnect the fifth MOSFET Q5 and the sixth MOSFET Q6.

[0059] The current value of inductor L1 is sampled and compared with a preset current value. Based on the comparison result, the conduction state of the fifth MOSFET Q5 and the sixth MOSFET Q6 is controlled. When the current of inductor L1 is less than the preset current value, the fifth MOSFET Q5 and the sixth MOSFET Q6 are turned off to realize automatic detection of the direction of the output current of inductor L1. When the current of inductor L1 is reversed, the synchronous rectifier is automatically turned off to prevent current backflow, protect the synchronous rectifier circuit, improve the stability of the circuit system, and extend the service life of the circuit.

[0060] This application also provides a synchronous rectification circuit. For example... Figure 1 and Figure 2 As shown, the synchronous rectification circuit includes a main control chip U1, a fifth MOSFET Q5, a sixth MOSFET Q6, a transformer T1, an inductor L1, an energy storage capacitor C1, and a first MOSFET Q1, a second MOSFET Q2, a third MOSFET Q3, and a fourth MOSFET Q4 connected in a full-bridge rectifier circuit. The intermediate node of the first MOSFET Q1 and the second MOSFET Q2 is connected to the same-name terminal of the primary side of the transformer T1, and the intermediate node of the third MOSFET Q3 and the fourth MOSFET Q4 is connected to the opposite-name terminal of the primary side of the transformer T1. The fifth MOSFET Q5 and the sixth MOSFET Q6... MOSFETs Q6 are connected in parallel. The drain of the fifth MOSFET Q5 is connected to the opposite terminal of the secondary side of transformer T1. The drain of the sixth MOSFET Q6 is connected to the same terminal of the secondary side of transformer T1. The sources of the fifth MOSFET Q5 and the sixth MOSFET Q6 are both connected to the negative terminal of the power output. Inductor L1 is connected in series between the tap terminal of the secondary side of transformer T1 and the positive terminal of the power output. Energy storage capacitor C1 is connected in parallel between the positive and negative terminals of the power output. The main control chip U1 is connected to the gate of all MOSFETs and is controlled using the synchronous rectification control method described above.

[0061] This application divides the switching cycle of the MOSFET into multiple continuous operating stages. While the main control chip U1 normally controls the transfer of energy from the primary side to the secondary side of the transformer T1, it adds the conduction time of the fifth MOSFET Q5 and the sixth MOSFET Q6 when all four primary MOSFETs are off, allowing freewheeling current through the inductor L1. Furthermore, it reasonably increases the dead time (i.e., the second, fourth, sixth, and eighth operating stages) in the control of the fifth MOSFET Q5 and the sixth MOSFET Q6 to avoid short circuits and ensure reliable system operation. Compared to existing methods that use the body diode of the MOSFET for freewheeling when the MOSFET is off, this reduces losses and improves system efficiency.

[0062] The synchronous rectifier circuit of this application embodiment can be applied in a DC-DC converter.

[0063] refer to Figure 4The synchronous rectification circuit also includes a current sampling unit 110, a current comparison unit 120, a wave-by-wave current limiting unit 130, and a driving unit 140. The current sampling unit 110 is used to sample and acquire the current of inductor L1 and transmit it to the current comparison unit 120. The current comparison unit 120 compares the received current of inductor L1 with a preset current value and outputs a wave-by-wave current limiting signal. The wave-by-wave current limiting unit 130 generates a PWM signal based on the driving signal for the fifth MOSFET Q5 and the sixth MOSFET Q6 output by the main control chip U1 and the wave-by-wave current limiting signal. The driving unit 140 generates a synchronous rectification driving signal based on the PWM signal to drive the fifth MOSFET Q5 and the sixth MOSFET Q6.

[0064] The current sampling unit 110 can effectively sample the current of inductor L1 and transmit the sampled current of inductor L1 to the current comparison unit 120. In this embodiment, the current of inductor L1 is compared with a preset current value, and based on the comparison result and the drive signals for the fifth MOSFET Q5 and the sixth MOSFET Q6 output by the main control chip U1, a synchronous rectification drive signal is generated to drive the fifth MOSFET Q5 and the sixth MOSFET Q6. This ensures that when the current of inductor L1 reverses, the fifth MOSFET Q5 and the sixth MOSFET Q6 are automatically and promptly disconnected to prevent current backflow.

[0065] refer to Figure 4 and Figure 5 In an optional embodiment of this application, the wave-by-wave current limiting unit 130 includes a first Schmitt trigger Q1A, a second Schmitt trigger Q1B, a first AND gate U1A, and a second AND gate U1B. The clock input terminal of the first Schmitt trigger Q1A receives the PWMH signal output by the main control chip U1, and its output terminal is connected to the first input terminal of the first AND gate U1A. The clock input terminal of the second Schmitt trigger Q1B receives the PWML signal output by the main control chip U1, and its output terminal is connected to the first input terminal of the second AND gate U1B. The reset input terminals of the first Schmitt trigger Q1A and the second Schmitt trigger Q1B both receive the wave-by-wave current limiting signal output by the current comparison unit 120. The second input terminal of the first AND gate U1A receives the PWMH signal output by the main control chip U1, and the second input terminal of the second AND gate U1B receives the PWML signal output by the main control chip U1. The output terminals of the first AND gate U1A and the second AND gate U1B are both connected to the driving unit 140.

[0066] A Schmitt trigger is a comparator circuit that includes positive feedback. For a standard Schmitt trigger, the output is high when the input voltage is higher than the positive threshold voltage; the output is low when the input voltage is lower than the negative threshold voltage; and the output does not change when the input is between the positive and negative threshold voltages. In other words, the threshold voltages corresponding to the output flipping from a high level to a low level or from a low level to a high level are different.

[0067] An AND gate is a basic logic gate circuit that performs an AND operation.

[0068] By setting the first Schmitt trigger Q1A, the second Schmitt trigger Q1B, the first AND gate U1A, and the second AND gate U1B, the current sampling unit 110 samples the current of the output inductor L1. The sampled current of the inductor L1 is compared with the preset current value, i.e., the preset inductor L1 current reverse current threshold, to generate a wave-by-wave current limiting signal. The wave-by-wave current limiting signal and the PWM signal generated by the main controller are passed through the first Schmitt trigger Q1A, the second Schmitt trigger Q1B, the first AND gate U1A, and the second AND gate U1B to generate a PWM drive signal, which is then driven by the drive unit 140 to drive the fifth MOSFET Q5 and the sixth MOSFET Q6.

[0069] When the current in inductor L1 is greater than the preset current value, the current comparison unit 120 outputs a high level of normal signal. When the current in inductor L1 is less than the preset current value, the current comparison unit 120 outputs a low level of abnormal signal. Both the high and low levels are input to the reset input of the first Schmitt trigger Q1A and the reset input of the second Schmitt trigger Q1B. Specifically, the clock input terminal of the first Schmitt trigger Q1A receives the PWMH signal generated by the main control chip U1, and the clock input terminal of the second Schmitt trigger Q1B receives the PWML signal generated by the main control chip U1. When the current of inductor L1 is normal, the output of the first Schmitt trigger Q1A is equivalent to the PWMH signal output by the main control chip U1. This PWMH signal is sent to the second input terminal of the first AND gate U1A, and after the first AND gate U1A outputs the PWMH signal, it is sent to the drive unit 140. The output of the second Schmitt trigger Q1B is equivalent to the PWML signal output by the main control chip U1. This PWML signal is sent to the second input terminal of the second AND gate U1B, and after the second AND gate U1B outputs the PWML signal, it is sent to the drive unit 140. When the current in inductor L1 is abnormal, the current comparison unit 120 outputs a low level of abnormal signal. After the PWMLH and PWML signals generated by the main control chip U1 are processed by the wave-by-wave current limiting unit 130, no drive signal is generated, thereby turning off the synchronous rectifier. This operation can prevent the current backflow caused by the synchronous rectifier MOSFET being turned on for a long time during low-power charging.

[0070] like Figure 4 and Figure 6As shown, in an optional embodiment of this application, the current sampling unit 110 includes a sampling resistor R1, a first resistor R2, a second resistor R3, a third resistor R4, a fourth resistor R5, and a first comparator U2A. The sampling resistor R1 is connected in series between the source of the fifth MOS transistor Q5 and the negative terminal of the power supply output. The first resistor R2 is connected in series between one end of the sampling resistor R1 and the non-inverting input terminal of the first comparator U2A. The second resistor R3 is connected in series between the other end of the sampling resistor R1 and the inverting input terminal of the first comparator U2A. The third resistor R4 is connected in series between the external reference voltage point and the non-inverting input terminal of the first comparator U2A. The fourth resistor R5 is connected in series between the output terminal and the inverting input terminal of the first comparator U2A. The output terminal of the first comparator U2A is also connected to the wave-by-wave current limiting unit 130.

[0071] By setting a sampling resistor R1, the current of inductor L1 is sampled using the current differential method to obtain a current differential signal. Since the differential signal contains the difference between the two signals, it has a good suppression effect on common-mode interference, which makes the differential sampling method more stable in noisy environments. Moreover, the differential sampling method does not require a very precise reference voltage, but only needs to ensure that the reference voltages of the two signals are the same, which reduces the system's requirements for reference voltage stability.

[0072] The first resistor R2, the second resistor R3, the third resistor R4, and the fourth resistor R5, together with the first comparator U2A, constitute an operational amplifier circuit. This circuit amplifies the current differential signal, making the amplitude of the output signal increase by the required multiple compared to the input signal, thereby enhancing the signal strength. The operational amplifier circuit features high input impedance and low output impedance, which can effectively isolate the input signal source and the output load, ensuring the stability and reliability of signal transmission. Furthermore, the circuit structure is simple.

[0073] refer to Figures 4 to 6 In an optional embodiment of this application, the wave-by-wave current limiting unit 130 includes a second comparator U2B, a fifth resistor R6, and a sixth resistor R7. The fifth resistor R6 is connected in series between the output terminal of the first comparator U2A and the non-inverting input terminal of the second comparator U2B. The inverting input terminal of the second comparator U2B is used to receive a preset current value. The sixth resistor R7 is connected in series between the external power supply and the output terminal of the second comparator U2B. The output terminal of the second comparator U2B is also connected to the reset input terminals of the first Schmitt trigger Q1A and the second Schmitt trigger Q1B.

[0074] By setting up a current comparison circuit with the second comparator U2B, the fifth resistor R6, and the sixth resistor R7, the sampled current of inductor L1 is compared with a preset current value to obtain a wave-by-wave current limiting signal. The wave-by-wave current limiting signal is used as the input signal to the reset input terminal of the first Schmitt trigger Q1A and the second Schmitt trigger Q1B. After being processed by the Schmitt trigger and the corresponding logic gate, a normal drive signal is output, or no drive signal is generated.

[0075] In an optional embodiment of this application, the driving unit 140 may employ a dual-channel MOS transistor driving chip, which can output synchronous rectification driving signals to drive the fifth MOS transistor Q5 and the sixth MOS transistor Q6 based on the PWMH signal output by the first AND gate U1A and the PWML signal output by the second AND gate U1B.

[0076] Dual-channel MOSFET driver chips feature fast response, strong driving capability, and low power consumption. They integrate multiple functional modules, which can simplify circuit design, reduce the number of external components, reduce overall circuit complexity, and improve system stability and reliability.

[0077] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Those skilled in the art can modify the technical solutions described in the above embodiments, or make equivalent substitutions for some of the technical features; and all such modifications and substitutions should fall within the protection scope of the appended claims of the present invention.

Claims

1. A synchronous rectification control method, applied in a synchronous rectification circuit, characterized in that, The synchronous rectification circuit includes a fifth MOSFET, a sixth MOSFET, a transformer, an inductor, an energy storage capacitor, and a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET connected in a full-bridge rectifier circuit. The intermediate node of the first and second MOSFETs is connected to the same-name terminal of the primary side of the transformer, and the intermediate node of the third and fourth MOSFETs is connected to the opposite-name terminal of the primary side of the transformer. The fifth MOSFET is connected in parallel with the sixth MOSFET. The drain of the fifth MOSFET is connected to the opposite-name terminal of the secondary side of the transformer, and the drain of the sixth MOSFET is connected to the same-name terminal of the secondary side of the transformer. The sources of both the fifth and sixth MOSFETs are connected to the negative terminal of the power supply output. The inductor is connected in series between the tap of the secondary side of the transformer and the positive terminal of the power supply output. The energy storage capacitor is connected in parallel between the positive and negative terminals of the power supply output. One switching cycle includes multiple consecutive operating stages. The synchronous rectification control method includes: In the first working stage, the first, fourth, and fifth MOSFETs are turned on, while the other MOSFETs are turned off, so that energy is transferred from the primary side of the transformer to the secondary side. In the second working phase, all MOSFETs and the sixth MOSFET of the full-bridge rectifier circuit are disconnected, and the fifth MOSFET is turned on to provide freewheeling current for the inductor. In the third working stage, all MOSFETs of the full-bridge rectifier circuit are disconnected, and the fifth and sixth MOSFETs are turned on to provide freewheeling current for the inductor. In the fourth operating phase, all MOSFETs and the fifth MOSFET of the full-bridge rectifier circuit are disconnected, and the sixth MOSFET is turned on to provide freewheeling current for the inductor. In the fifth operating phase, the second, third, and sixth MOSFETs are turned on, while the other MOSFETs are turned off, transferring energy from the primary side of the transformer to the secondary side. In the sixth operating phase, all MOSFETs and the fifth MOSFET of the full-bridge rectifier circuit are disconnected, and the sixth MOSFET is turned on to provide freewheeling current for the inductor. In the seventh operating phase, all MOSFETs of the full-bridge rectifier circuit are disconnected, and the fifth and sixth MOSFETs are turned on to provide freewheeling current for the inductor. In the eighth operating phase, all MOSFETs and the sixth MOSFET of the full-bridge rectifier circuit are disconnected, and the fifth MOSFET is turned on to provide freewheeling current for the inductor.

2. The synchronous rectification control method according to claim 1, characterized in that, The first MOSFET and the fourth MOSFET are controlled by a first driving signal, the second MOSFET and the third MOSFET are controlled by a second driving signal, the fifth MOSFET is controlled by a third driving signal, and the sixth MOSFET is controlled by a fourth driving signal. The first driving signal and the second driving signal are out of phase by 180°, the first driving signal and the third driving signal are complementary, and the second driving signal and the fourth driving signal are complementary.

3. The synchronous rectification control method according to claim 2, characterized in that, The maximum duty cycle of both the first drive signal and the second drive signal does not exceed 50%.

4. The synchronous rectification control method according to claim 1, characterized in that, The second, fourth, sixth, and eighth working phases all have the same duration.

5. The synchronous rectification control method according to any one of claims 1 to 4, characterized in that, The synchronous rectification control method further includes: The inductor current value is sampled and compared with a preset current value; If the inductor current value is greater than the preset current value, a normal drive signal is generated to control the conduction state of the fifth MOSFET and the sixth MOSFET. If the inductor current value is less than the preset current value, no drive signal is generated to disconnect the fifth MOSFET and the sixth MOSFET.

6. A synchronous rectifier circuit, characterized in that, The synchronous rectification circuit includes a main control chip, a fifth MOSFET, a sixth MOSFET, a transformer, an inductor, an energy storage capacitor, and a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET connected in a full-bridge rectifier circuit. The intermediate node of the first MOSFET and the second MOSFET is connected to the same-name terminal of the primary side of the transformer, and the intermediate node of the third MOSFET and the fourth MOSFET is connected to the opposite-name terminal of the primary side of the transformer. The fifth MOSFET and the sixth MOSFET are connected in parallel. The drain of the fifth MOSFET is connected to the opposite-name terminal of the secondary side of the transformer, and the drain of the sixth MOSFET is connected to the same-name terminal of the secondary side of the transformer. The sources of the fifth MOSFET and the sixth MOSFET are both connected to the negative terminal of the power output terminal. The inductor is connected in series between the tap terminal of the secondary side of the transformer and the positive terminal of the power output terminal. The energy storage capacitor is connected in parallel between the positive and negative terminals of the power output terminal. The main control chip is connected to the gate of all MOSFETs and is controlled by the synchronous rectification control method as described in any one of claims 1-5.

7. The synchronous rectifier circuit according to claim 6, characterized in that, The synchronous rectification circuit further includes a current sampling unit, a current comparison unit, a wave-by-wave current limiting unit, and a driving unit. The current sampling unit is used to sample and acquire the inductor current and transmit it to the current comparison unit. The current comparison unit compares the received inductor current with a preset current value and outputs a wave-by-wave current limiting signal. The wave-by-wave current limiting unit generates a PWM signal based on the driving signal for the fifth and sixth MOSFETs output by the main control chip and the wave-by-wave current limiting signal. The driving unit generates a synchronous rectification driving signal based on the PWM signal to drive the fifth and sixth MOSFETs.

8. The synchronous rectifier circuit according to claim 7, characterized in that, The wave-by-wave current limiting unit includes a first Schmitt trigger, a second Schmitt trigger, a first AND gate, and a second AND gate. The clock input of the first Schmitt trigger receives the PWMH signal output by the main control chip, and its output is connected to the first input of the first AND gate. The clock input of the second Schmitt trigger receives the PWML signal output by the main control chip, and its output is connected to the first input of the second AND gate. The reset inputs of both the first and second Schmitt triggers receive the wave-by-wave current limiting signal output by the current comparison unit. The second input of the first AND gate receives the PWMH signal output by the main control chip, and the second input of the second AND gate receives the PWML signal output by the main control chip. The outputs of both the first and second AND gates are connected to the driving unit.

9. The synchronous rectifier circuit according to claim 8, characterized in that, The current sampling unit includes a sampling resistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first comparator. The sampling resistor is connected in series between the source of the fifth MOS transistor and the negative terminal of the power supply output. The first resistor is connected in series between one end of the sampling resistor and the non-inverting input of the first comparator. The second resistor is connected in series between the other end of the sampling resistor and the inverting input of the first comparator. The third resistor is connected in series between the external reference voltage point and the non-inverting input of the first comparator. The fourth resistor is connected in series between the output and inverting input of the first comparator. The output of the first comparator is also connected to the wave-by-wave current limiting unit.

10. The synchronous rectifier circuit according to claim 9, characterized in that, The wave-by-wave current limiting unit includes a second comparator, a fifth resistor, and a sixth resistor. The fifth resistor is connected in series between the output terminal of the first comparator and the non-inverting input terminal of the second comparator. The inverting input terminal of the second comparator is used to receive a preset current value. The sixth resistor is connected in series between the external power supply and the output terminal of the second comparator. The output terminal of the second comparator is also connected to the reset input terminals of the first Schmitt trigger and the second Schmitt trigger.

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