Two-level inverter

Abstract

The invention relates to the technical field of inverters, and discloses a two-level inverter which comprises three parallel inversion branches and bus capacitor branches connected to the two ends of the inversion branches in parallel, an intermediate node of each inversion branch is electrically connected with an inductance branch, and each inductance branch comprises an output inductor and a common mode inductor which are sequentially connected in series from the intermediate node; for each inductance branch, at least one node of one end of the output inductor, the other end of the output inductor and one end, which is not electrically connected with the common mode inductor, of the filter capacitor is connected to the bus capacitor branch through the bridging capacitor; during use, the bridging capacitor is arranged at at least one node between the middle point of the inversion branch and the common mode inductor, and the bridging capacitor is connected to the bus capacitor branch, so that a flowing path is provided for common mode current, the common mode current flows to the bus capacitor branch, the common mode current is prevented from flowing to the common mode inductor and the Y capacitor, and the reliability of the common mode current is improved. The problem of abnormal temperature rise of the common-mode inductor and the Y capacitor due to common-mode current is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of inverters, and in particular to a two-level inverter. Background Art

[0002] As a high-power AC power equipment, three-level inverters are used in many fields due to their advantages such as small output ripple current, flexible control modulation, increased switching frequency, low switch tube stress and low electromagnetic interference. However, three-level inverters also have the problem of many power devices, and unbalanced loads will cause unbalanced bus midpoint voltage, affecting inverter output performance and increasing system losses.

[0003] Compared with the three-level inverter, the two-level inverter can improve the bus voltage utilization by adopting PWM control and injecting the third harmonic into the modulation signal. It has the ability to carry unbalanced loads and also has the advantages of small size, low cost and fewer power devices.

[0004] For two-level inverters, although they can suppress common-mode voltage and reduce common-mode current to a certain extent by changing the modulation mode, they cannot fundamentally solve the harm caused by common-mode current. When the two-level inverter is actually used, when the common-mode current flows through the common-mode inductor and Y capacitor of the inverter and circulates in the circuit continuously, it will cause abnormal temperature rise of the common-mode inductor and Y capacitor. Moreover, the higher the voltage level, the higher the switching frequency, the heavier the load and the more severe the unbalanced load, the greater the common-mode current, and the more serious the abnormal temperature rise of the common-mode inductor and Y capacitor. Summary of the invention

[0005] In view of the shortcomings of the background technology, the present invention provides a two-level inverter. The technical problem to be solved is that when the existing two-level inverter is actually used, the common-mode current in the circuit circulates continuously, causing abnormal temperature rise of the common-mode inductor and Y capacitor in the circuit.

[0006] To solve the above technical problems, in a first aspect, the present invention provides the following technical solutions: a two-level inverter, comprising three parallel inverter branches, bus capacitor branches connected in parallel at both ends of the inverter branches, each inverter branch comprising an upper switch tube and a lower switch tube connected in series; The middle node of each inverter branch is electrically connected to an inductor branch, and each inductor branch includes an output inductor and a common mode inductor connected in series in sequence from the middle node; For each inductor branch, one end of the output inductor electrically connected to one end of the common-mode inductor is electrically connected to a filter capacitor, and the other end of the common-mode inductor is electrically connected to a Y capacitor; the ends of the filter capacitors on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other; the ends of the Y capacitors on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and grounded; For each inductor branch, at least one node among one end of the output inductor, the other end of the output inductor and one end of the filter capacitor not electrically connected to the common mode inductor is connected to the bus capacitor branch through a jumper capacitor.

[0007] In a certain implementation manner of the first aspect, the end of the filter capacitor that is not electrically connected to the common mode inductor is connected to the head end, tail end or an intermediate node of the bus capacitor branch through a jumper capacitor C1; Or one end of the output inductor in the three inductor branches is electrically connected to a jumper capacitor C2 respectively, and one end of the three jumper capacitors C2 that is not electrically connected to the output inductor is electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch; Or the other ends of the output inductors in the three inductor branches are electrically connected to jumper capacitors C3 respectively, and the ends of the three jumper capacitors C3 not electrically connected to the output inductors are electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch.

[0008] In a second aspect, the present invention provides a two-level inverter of another structure, comprising three parallel inverter branches, a bus capacitor branch and a split capacitor branch connected in parallel at both ends of the inverter branch, each inverter branch comprising an upper switch tube and a lower switch tube connected in series; The middle node of each inverter branch is electrically connected to an inductor branch, and each inductor branch includes an output inductor and a common mode inductor connected in series in sequence from the middle node; For each inductor branch, one end of the output inductor electrically connected to one end of the common-mode inductor is electrically connected to a filter capacitor, and the other end of the common-mode inductor is electrically connected to a Y capacitor; the ends of the filter capacitors on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other; the ends of the Y capacitors on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and grounded; For each inductor branch, at least one node among one end of the output inductor, the other end of the output inductor and one end of the filter capacitor not electrically connected to the common mode inductor is connected to the split capacitor branch through a jumper capacitor.

[0009] In a certain implementation manner of the second aspect, the end of the filter capacitor that is not electrically connected to the common mode inductor is connected to the head end, tail end or an intermediate node of the split capacitor branch through a jumper capacitor C11; Or one end of the output inductor in the three inductor branches is electrically connected to a jumper capacitor C12 respectively, and one end of the three jumper capacitors C12 that is not electrically connected to the output inductor is electrically connected to each other and connected to the head end, tail end or an intermediate node of the split capacitor branch; Or the other ends of the output inductors in the three inductor branches are electrically connected to jumper capacitors C13 respectively, and the ends of the three jumper capacitors C13 not electrically connected to the output inductors are electrically connected to each other and connected to the head end, tail end or an intermediate node of the split capacitor branch.

[0010] In a third aspect, the present invention provides a two-level inverter of another structure, comprising four parallel inverter branches, bus capacitor branches connected in parallel at both ends of the inverter branches, each inverter branch comprising an upper switch tube and a lower switch tube connected in series; The middle node of each inverter branch is electrically connected to an inductor branch, and each inductor branch includes an output inductor and a common mode inductor connected in series in sequence from the middle node; For three of the four inductor branches, one end of the output inductor in each inductor branch electrically connected to one end of the common-mode inductor is respectively connected to one end of the output inductor in the remaining inductor branch electrically connected to one end of the common-mode inductor through a filter capacitor; For the four inductor branches, the other end of the common-mode inductor is electrically connected to a Y capacitor; the ends of the Y capacitors on the four inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and are grounded; For at least one inductor branch among the four inductor branches, at least one node between one end of the output inductor and the other end of the output inductor is connected to the bus capacitor branch through a jumper capacitor.

[0011] In a certain implementation manner of the third aspect, at least one node between one end of the output inductor and the other end of the output inductor in the residual inductor branch is connected to the head end, tail end or an intermediate node of the bus capacitor branch through a jumper capacitor C21; Or one end of the output inductor in the four inductor branches is electrically connected to a jumper capacitor C22 respectively, and one end of the four jumper capacitors C22 that is not electrically connected to the output inductor is electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch; Or the other ends of the output inductors in the four inductor branches are electrically connected to jumper capacitors C23 respectively, and the ends of the four jumper capacitors C23 not electrically connected to the output inductors are electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch.

[0012] In a fourth aspect, the present invention provides a two-level inverter of another structure, comprising four parallel inverter branches, a bus capacitor branch and a split capacitor branch connected in parallel at both ends of the inverter branch, each inverter branch comprising an upper switch tube and a lower switch tube connected in series; The middle node of each inverter branch is electrically connected to an inductor branch, and each inductor branch includes an output inductor and a common mode inductor connected in series in sequence from the middle node; For three of the four inductor branches, one end of the output inductor in each inductor branch electrically connected to one end of the common-mode inductor is respectively connected to one end of the output inductor in the remaining inductor branch electrically connected to one end of the common-mode inductor through a filter capacitor; For the four inductor branches, the other end of the common-mode inductor is electrically connected to a Y capacitor; the ends of the Y capacitors on the four inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and are grounded; For at least one inductor branch among the four inductor branches, at least one node between one end of the output inductor and the other end of the output inductor is connected to the split capacitor branch.

[0013] In a certain embodiment of the fourth aspect, for at least one of the four inductor branches, at least one node between one end of the output inductor and the other end of the output inductor is connected to the beginning, the end or an intermediate node of the split capacitor branch.

[0014] In addition, in a certain implementation manner, the upper switch tube and the lower switch tube are both NMOS tubes; the bus capacitor branch includes a bus capacitor C51 and a bus capacitor C52 connected in series.

[0015] In addition, in some embodiments, the split capacitor branch includes a split capacitor C61 and a split capacitor C62 connected in series.

[0016] Compared with the prior art, the present invention has the following beneficial effects: a jumper capacitor is arranged at at least one node between the midpoint of the inverter branch and the common-mode inductor, and the jumper capacitor is connected to the bus capacitor branch, thereby providing a flow path for the common-mode current, allowing the common-mode current to flow to the bus capacitor branch, thereby preventing the common-mode current from flowing into the common-mode inductor and the Y capacitor, and solving the problem of abnormal temperature rise of the common-mode inductor and the Y capacitor due to the common-mode current. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the first structure of the present invention in Embodiment 1; Figure 2 It is a schematic diagram of the second structure of the present invention in the first embodiment; Figure 3 It is a schematic diagram of the structure of the present invention in Embodiment 2; Figure 4 It is a schematic diagram of the first structure of the present invention in Embodiment 3; Figure 5 It is a schematic diagram of the second structure of the present invention in Embodiment 3; Figure 6 It is a structural schematic diagram of the present invention in embodiment 4. DETAILED DESCRIPTION

[0018] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0019] Embodiment 1 like Figure 1 As shown, a two-level inverter includes three parallel inverter branches 2, bus capacitor branches 2 connected in parallel at both ends of the inverter branch 1, each inverter branch 2 includes an upper switch tube and a lower switch tube connected in series, and the upper switch tube and the lower switch tube are both NMOS tubes; taking the leftmost inverter branch 2 as an example, the upper switch tube S1 and the lower switch tube S2 form an inverter branch 2, while the upper switch tube S3 and the lower switch tube S4 form an inverter branch 2, and the upper switch tube S5 and the lower switch tube S6 form an inverter branch 2; The middle nodes of each inverter branch 2 are electrically connected to an inductor branch 3, respectively. Each inductor branch 3 includes an output inductor and a common-mode inductor connected in series in sequence from the middle node; specifically, the output inductor L1 and the common-mode inductor L11 form an inductor branch 3, the output inductor L2 and the common-mode inductor L12 form an inductor branch 3, and the output inductor L3 and the common-mode inductor L13 form an inductor branch; For each inductor branch 3, one end of the output inductor electrically connected to one end of the common-mode inductor is electrically connected to a filter capacitor C101, and the other end of the common-mode inductor is electrically connected to a Y capacitor C100; the ends of the filter capacitors C101 on the three inductor branches 3 that are not electrically connected to the common-mode inductor are electrically connected to each other; the ends of the Y capacitors C100 on the three inductor branches 3 that are not electrically connected to the common-mode inductor are electrically connected to each other and grounded; For each inductor branch 3, at least one node among one end of the output inductor, the other end of the output inductor and one end of the filter capacitor C101 not electrically connected to the common mode inductor is connected to the bus capacitor branch 1 through a jumper capacitor.

[0020] In this embodiment, in one implementation, Figure 1 As shown, the end of the filter capacitor C101 that is not electrically connected to the common mode inductor is connected to the beginning, the end or an intermediate node of the busbar capacitor branch 1 through the jumper capacitor C1.

[0021] In addition Figure 1 In the figure, the bus capacitor branch 1 includes bus capacitors C51 and C52 connected in series, so there are three nodes, namely node M1 (the beginning of bus capacitor branch 1), node M2 ​​(middle node) and node M3 (the end of bus capacitor branch 1); therefore, the end of filter capacitor C101 that is not electrically connected to the common-mode inductor can be connected to node M1, node M2 ​​or node M3 through jumper capacitor C1.

[0022] In this embodiment, in another implementation manner, Figure 2 As shown, one end of the output inductor in the three inductor branches 3 is electrically connected to a jumper capacitor C2 respectively, and the ends of the three jumper capacitors C2 that are not electrically connected to the output inductor are electrically connected to each other and connected to the head end of the bus capacitor branch 1, i.e., the node M1; wherein one end of the output inductor is the end of the output inductor electrically connected to the common mode inductor; In addition, in actual implementation, one end of the output inductors in the three inductor branches 3 is electrically connected to the jumper capacitor C2 respectively, and the ends of the three jumper capacitors C2 that are not electrically connected to the output inductors can also be connected to the node M2 ​​or the node M3.

[0023] In actual use, by electrically connecting one end of the output inductors in the three inductor branches 3 to the cross-over capacitor C2 respectively, the current withstand value of the cross-over capacitor C2 can be effectively reduced, making the selection range of the cross-over capacitor C2 wider.

[0024] In a certain embodiment, the other ends of the output inductors in the three inductor branches 3 are respectively electrically connected to the jumper capacitors C3, and the ends of the three jumper capacitors C3 that are not electrically connected to the output inductors are electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch; wherein the other end of the output inductor is the end of the output inductor that is not electrically connected to the common-mode inductor.

[0025] In some implementations, the nodes to which the three cross-over capacitors C2 or the three cross-over capacitors C3 are connected to the bus capacitor branch 1 may be different. For example, taking the three cross-over capacitors C2 as an example: One jumper capacitor C2 can be connected to the node M1, another jumper capacitor C2 can be connected to the node M2, and the remaining jumper capacitor C2 can be connected to the node M3; Alternatively, two jumper capacitors C2 can be connected to one node of the bus capacitor branch 1 at the same time, and another jumper capacitor C2 can be connected to one of the remaining two nodes of the bus capacitor branch 1.

[0026] In a certain implementation manner, both ends of the output inductor in each inductor branch 3 can be connected to the bus capacitor branch 1 via a jumper capacitor.

[0027] It should also be noted that although connecting the jumper capacitor to node M2 ​​of bus capacitor branch 1 can solve the common-mode inductance and heating problem of Y capacitor C100 caused by common-mode current, it will cause unbalanced bus midpoint voltage, and an additional midpoint balance control strategy needs to be added.

[0028] In actual use, the two-level inverter in this embodiment provides a flow path for the common-mode current by setting a jumper capacitor at at least one node between the midpoint of the inverter branch 2 and the common-mode inductor, and connecting the jumper capacitor to the bus capacitor branch 1, so as to make the common-mode current flow to the bus capacitor branch 1, thereby preventing the common-mode current from flowing into the common-mode inductor and the Y capacitor C101, and solving the problem of abnormal temperature rise of the common-mode inductor and the Y capacitor C101 due to the common-mode current.

[0029] Embodiment 2 like Figure 3 As shown, this embodiment provides a two-level inverter of another structure, including three parallel inverter branches 2, a bus capacitor branch 1 and a split capacitor branch 4 connected in parallel at both ends of the inverter branch 2, each inverter branch 2 includes an upper switch tube and a lower switch tube connected in series; the upper switch tube and the lower switch tube are both NMOS tubes; taking the leftmost inverter branch 2 as an example, the upper switch tube S1 and the lower switch tube S2 form an inverter branch 2, while the upper switch tube S3 and the lower switch tube S4 form an inverter branch 2, and the upper switch tube S5 and the lower switch tube S6 form an inverter branch 2. The middle nodes of each inverter branch 2 are electrically connected to an inductor branch 3, respectively. Each inductor branch includes an output inductor and a common-mode inductor connected in series in sequence from the middle node; specifically, the output inductor L1 and the common-mode inductor L11 form an inductor branch 3, the output inductor L2 and the common-mode inductor L12 form an inductor branch 3, and the output inductor L3 and the common-mode inductor L13 form an inductor branch; For each inductor branch 3, one end of the output inductor electrically connected to one end of the common-mode inductor is electrically connected to a filter capacitor C101, and the other end of the common-mode inductor is electrically connected to a Y capacitor C100; the ends of the filter capacitors C101 on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other; the ends of the Y capacitors C100 on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and grounded; For each inductor branch 3, at least one node among one end of the output inductor, the other end of the output inductor and one end of the filter capacitor C101 not electrically connected to the common mode inductor is connected to the split capacitor branch 4 through a jumper capacitor.

[0030] In this embodiment, in one implementation, the end of the filter capacitor C101 that is not electrically connected to the common mode inductor is connected to the head end, tail end or an intermediate node of the split capacitor branch 4 through the jumper capacitor C11.

[0031] In addition Figure 3In the figure, the split capacitor branch 4 includes a split capacitor C61 and a split capacitor C62 connected in series, so there are three nodes, namely node M10 (the beginning of the split capacitor branch 4), node M11 (the middle node) and node M12 (the end of the split capacitor branch 4); therefore, the end of the filter capacitor C101 that is not electrically connected to the common-mode inductor can be connected to node M10, node M11 or node M12 through the jumper capacitor C1.

[0032] In this embodiment, Figure 3 As shown, one end of the output inductor in the three inductor branches 3 is electrically connected to a cross-over capacitor C12 respectively, and the ends of the three cross-over capacitors C12 that are not electrically connected to the output inductor are electrically connected to each other and connected to the middle node of the split capacitor branch 1, that is, the node M11; wherein one end of the output inductor is the end where the output inductor is electrically connected to the common mode inductor; In addition, in actual implementation, one end of the output inductor in the three inductor branches 3 is electrically connected to a jumper capacitor C12, and one end of the three jumper capacitors C12 that is not electrically connected to the output inductor can also be connected to the node M10 or the node M12; In a certain embodiment, the other ends of the output inductors in the three inductor branches 3 are respectively electrically connected to the jumper capacitors C13, and the ends of the three jumper capacitors C13 that are not electrically connected to the output inductors are electrically connected to each other and connected to the beginning, end or an intermediate node of the split capacitor branch 4; wherein the other end of the output inductor is the end of the output inductor that is not electrically connected to the common-mode inductor.

[0033] In some implementations, the nodes to which the three cross-over capacitors C12 or the three cross-over capacitors C13 are connected to the split capacitor branch 4 may be different. For example, taking the three cross-over capacitors C12 as an example: One jumper capacitor C12 may be connected to the node M10, another jumper capacitor C12 may be connected to the node M11, and the remaining jumper capacitor C2 may be connected to the node M12; Alternatively, two jumper capacitors C12 can be connected to one node of the split capacitor branch 4 at the same time, and another jumper capacitor C12 can be connected to one of the remaining two nodes of the split capacitor branch 4.

[0034] In a certain implementation manner, both ends of the output inductor in each inductor branch 3 can be connected to the split capacitor branch 4 via a jumper capacitor, respectively.

[0035] It should also be noted that although connecting the jumper capacitor to the node M11 of the split capacitor branch 4 can solve the common-mode inductance and heating problem of the Y capacitor C100 caused by the common-mode current, it will cause an unbalanced bus midpoint voltage, and an additional midpoint balance control strategy needs to be added.

[0036] Embodiment 3 like Figure 4 As shown, this embodiment provides a two-level inverter of another structure, including four parallel inverter branches 2, bus capacitor branches 1 connected in parallel at both ends of the inverter branches 2, each inverter branch 2 includes an upper switch tube and a lower switch tube connected in series; the upper switch tube and the lower switch tube are both NMOS tubes; taking the leftmost inverter branch 2 as an example, the upper switch tube S1 and the lower switch tube S2 form an inverter branch 2, while the upper switch tube S3 and the lower switch tube S4 form an inverter branch 2, the upper switch tube S5 and the lower switch tube S6 form an inverter branch 2, and the upper switch tube S7 and the lower switch tube S8 form an inverter branch 2; The middle nodes of each inverter branch 2 are electrically connected to an inductor branch 3, respectively. Each inductor branch 3 includes an output inductor and a common-mode inductor connected in series in sequence from the middle node; specifically, the output inductor L1 and the common-mode inductor L11 form an inductor branch 3, the output inductor L2 and the common-mode inductor L12 form an inductor branch 3, the output inductor L3 and the common-mode inductor L13 form an inductor branch 3, and the output inductor L4 and the common-mode inductor L14 form an inductor branch 3; For three of the four inductor branches 3, one end of the output inductor in each inductor branch 3 electrically connected to one end of the common-mode inductor is connected to one end of the output inductor in the remaining inductor branch 3 electrically connected to one end of the common-mode inductor through the filter capacitor C101; For the four inductor branches 3, the other end of the common-mode inductor is electrically connected to a Y capacitor; the ends of the Y capacitors on the four inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and are grounded; For at least one inductor branch 3 among the four inductor branches 3 , at least one node between one end of the output inductor and the other end of the output inductor is connected to the bus capacitor branch 1 via a jumper capacitor.

[0037] In this embodiment, in one implementation, Figure 4 As shown, one end of the output inductor L4 in the residual inductor branch is connected to the head end, tail end or an intermediate node of the bus capacitor branch 1 through the jumper capacitor C21; wherein one end of the output inductor L4 in the residual inductor branch is the end where the output inductor L4 is electrically connected to the common mode inductor L14.

[0038] In addition Figure 1 In the figure, the bus capacitor branch 1 includes bus capacitors C51 and C52 connected in series, so there are three nodes, namely node M1 (the beginning of bus capacitor branch 1), node M2 ​​(the middle node) and node M3 (the end of bus capacitor branch 1); so one end of the output inductor L4 in the remaining inductor branch can be connected to node M1, node M2 ​​or node M3 through the jumper capacitor C21.

[0039] In addition, in actual implementation, the other end of the output inductor L4 in the remaining inductor branch can also be connected to the beginning, the end or an intermediate node of the busbar capacitor branch 1 through the jumper capacitor C21.

[0040] In another embodiment, Figure 5 As shown, one end of the output inductor in the four inductor branches 3 is electrically connected to a jumper capacitor C22 respectively, and the ends of the four jumper capacitors C22 that are not electrically connected to the output inductor are electrically connected to each other and connected to the head end of the bus capacitor branch 1, i.e., the node M1; wherein one end of the output inductor is the end of the output inductor electrically connected to the common mode inductor; In addition, in actual implementation, one end of the output inductor in the four inductor branches 3 is electrically connected to a jumper capacitor C22, and one end of the four jumper capacitors C22 that is not electrically connected to the output inductor can also be connected to the node M2 ​​or the node M3; In a certain embodiment, the other ends of the output inductors in the four inductor branches 3 are respectively electrically connected to the jumper capacitors C23, and the ends of the four jumper capacitors C23 that are not electrically connected to the output inductors are electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch 1; wherein the other end of the output inductor is the end of the output inductor that is not electrically connected to the common-mode inductor.

[0041] In some implementations, the nodes to which the four cross-over capacitors C22 or the three cross-over capacitors C23 are connected to the bus capacitor branch 1 may be different. For example, taking the four cross-over capacitors C22 as an example: Three cross-over capacitors C22 can be connected to a node of the bus capacitor branch 1, and the remaining cross-over capacitor C22 is connected to one of the remaining two nodes of the bus capacitor branch 1; Alternatively, two cross-over capacitors C22 may be connected to a node of the bus capacitor branch 1, and the remaining two cross-over capacitors C22 may be connected to one of the remaining two nodes of the bus capacitor branch 1; Alternatively, two jumper capacitors C22 can be connected to one node of the bus capacitor branch 1, another jumper capacitor C22 can be connected to another node of the bus capacitor branch 1, and the remaining jumper capacitor C22 can be connected to the remaining node of the bus capacitor branch 1.

[0042] In a certain implementation manner, both ends of the output inductor in each inductor branch 3 can be connected to the bus capacitor branch 1 via a jumper capacitor.

[0043] It should also be noted that although connecting the jumper capacitor to node M2 ​​of bus capacitor branch 1 can solve the common-mode inductance and heating problem of Y capacitor C100 caused by common-mode current, it will cause unbalanced bus midpoint voltage, and an additional midpoint balance control strategy needs to be added.

[0044] Embodiment 4 like Figure 6 As shown, this embodiment provides a two-level inverter of another structure, including four parallel inverter branches 2, a bus capacitor branch 1 and a split capacitor branch 4 connected in parallel at both ends of the inverter branch 2, each inverter branch 2 includes an upper switch tube and a lower switch tube connected in series; the upper switch tube and the lower switch tube are both NMOS tubes; taking the leftmost inverter branch 2 as an example, the upper switch tube S1 and the lower switch tube S2 form an inverter branch 2, while the upper switch tube S3 and the lower switch tube S4 form an inverter branch 2, the upper switch tube S5 and the lower switch tube S6 form an inverter branch 2, and the upper switch tube S7 and the lower switch tube S8 form an inverter branch 2; The intermediate nodes of each inverter branch are electrically connected to an inductor branch, and each inductor branch includes an output inductor and a common-mode inductor connected in series in sequence from the intermediate node; specifically, the output inductor L1 and the common-mode inductor L11 form an inductor branch 3, the output inductor L2 and the common-mode inductor L12 form an inductor branch 3, the output inductor L3 and the common-mode inductor L13 form an inductor branch 3, and the output inductor L4 and the common-mode inductor L14 form an inductor branch 3. For three of the four inductor branches 3, one end of the output inductor in each inductor branch 3 electrically connected to one end of the common-mode inductor is respectively connected to one end of the output inductor in the remaining inductor branch 3 electrically connected to one end of the common-mode inductor through the filter capacitor C101; For the four inductor branches 3, the other end of the common mode inductor is electrically connected to a Y capacitor C101; the ends of the Y capacitors on the four inductor branches 3 that are not electrically connected to the common mode inductor are electrically connected to each other and are grounded; For at least one inductor branch 3 among the four inductor branches 3 , at least one node between one end of the output inductor and the other end of the output inductor is connected to the split capacitor branch 4 .

[0045] In addition Figure 6 In the figure, the split capacitor branch 4 includes a split capacitor C61 and a split capacitor C62 connected in series, so there are three nodes, namely node M10 (the beginning of the split capacitor branch 4), node M11 (the middle node) and node M12 (the end of the split capacitor branch 4); so for at least one of the four inductor branches 3, one end of the output inductor can be connected to node M10, node M11 or node M12; wherein one end of the output inductor is an end at which the output inductor is electrically connected to the common-mode inductor.

[0046] In a certain implementation manner, for at least one inductor branch 3 among the four inductor branches 3 , the other end of the output inductor may also be connected to the node M10 , the node M11 , or the node M12 .

[0047] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A two-level inverter, characterized in that: It includes three parallel inverter branches, bus capacitor branches connected in parallel at both ends of the inverter branches, and each inverter branch includes an upper switch tube and a lower switch tube connected in series; The middle node of each inverter branch is electrically connected to an inductor branch, and each inductor branch includes an output inductor and a common mode inductor connected in series in sequence from the middle node; For each inductor branch, one end of the output inductor electrically connected to one end of the common-mode inductor is electrically connected to a filter capacitor, and the other end of the common-mode inductor is electrically connected to a Y capacitor; the ends of the filter capacitors on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other; the ends of the Y capacitors on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and grounded; For each inductor branch, at least one node among one end of the output inductor, the other end of the output inductor and one end of the filter capacitor not electrically connected to the common mode inductor is connected to the bus capacitor branch through a jumper capacitor.

2. A two-level inverter according to claim 1, characterized in that: The end of the filter capacitor that is not electrically connected to the common mode inductor is connected to the head end, tail end or an intermediate node of the bus capacitor branch through the jumper capacitor C1; Or one end of the output inductor in the three inductor branches is electrically connected to a jumper capacitor C2 respectively, and one end of the three jumper capacitors C2 that is not electrically connected to the output inductor is electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch; Or the other ends of the output inductors in the three inductor branches are electrically connected to jumper capacitors C3 respectively, and the ends of the three jumper capacitors C3 not electrically connected to the output inductors are electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch.

3. A two-level inverter, characterized in that: It includes three parallel inverter branches, a bus capacitor branch and a split capacitor branch connected in parallel at both ends of the inverter branch, and each inverter branch includes an upper switch tube and a lower switch tube connected in series; The middle node of each inverter branch is electrically connected to an inductor branch, and each inductor branch includes an output inductor and a common mode inductor connected in series in sequence from the middle node; For each inductor branch, one end of the output inductor electrically connected to one end of the common-mode inductor is electrically connected to a filter capacitor, and the other end of the common-mode inductor is electrically connected to a Y capacitor; the ends of the filter capacitors on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other; the ends of the Y capacitors on the three inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and grounded; For each inductor branch, at least one node among one end of the output inductor, the other end of the output inductor and one end of the filter capacitor not electrically connected to the common mode inductor is connected to the split capacitor branch through a jumper capacitor.

4. A two-level inverter according to claim 3, characterized in that: The end of the filter capacitor that is not electrically connected to the common mode inductor is connected to the head end, tail end or an intermediate node of the split capacitor branch through the jumper capacitor C11; Or one end of the output inductor in the three inductor branches is electrically connected to a jumper capacitor C12 respectively, and one end of the three jumper capacitors C12 that is not electrically connected to the output inductor is electrically connected to each other and connected to the head end, tail end or an intermediate node of the split capacitor branch; Or the other ends of the output inductors in the three inductor branches are electrically connected to the jumper capacitors C3 respectively, and the ends of the three jumper capacitors C13 not electrically connected to the output inductors are electrically connected to each other and connected to the head end, tail end or an intermediate node of the split capacitor branch.

5. A two-level inverter, characterized in that: It includes four parallel inverter branches, bus capacitor branches connected in parallel at both ends of the inverter branches, and each inverter branch includes an upper switch tube and a lower switch tube connected in series; The middle node of each inverter branch is electrically connected to an inductor branch, and each inductor branch includes an output inductor and a common mode inductor connected in series in sequence from the middle node; For three of the four inductor branches, one end of the output inductor in each inductor branch electrically connected to one end of the common-mode inductor is respectively connected to one end of the output inductor in the remaining inductor branch electrically connected to one end of the common-mode inductor through a filter capacitor; For the four inductor branches, the other end of the common-mode inductor is electrically connected to a Y capacitor; the ends of the Y capacitors on the four inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and are grounded; For at least one inductor branch among the four inductor branches, at least one node between one end of the output inductor and the other end of the output inductor is connected to the bus capacitor branch through a jumper capacitor.

6. A two-level inverter according to claim 5, characterized in that: At least one node of one end of the output inductor and the other end of the output inductor in the residual inductor branch is connected to the head end, tail end or an intermediate node of the bus capacitor branch through the jumper capacitor C21; Or one end of the output inductor in the four inductor branches is electrically connected to a jumper capacitor C22 respectively, and one end of the four jumper capacitors C22 that is not electrically connected to the output inductor is electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch; Or the other ends of the output inductors in the four inductor branches are electrically connected to jumper capacitors C23 respectively, and the ends of the four jumper capacitors C23 not electrically connected to the output inductors are electrically connected to each other and connected to the head end, tail end or an intermediate node of the bus capacitor branch.

7. A two-level inverter, characterized in that: It includes four parallel inverter branches, bus capacitor branches and split capacitor branches connected in parallel at both ends of the inverter branches, and each inverter branch includes an upper switch tube and a lower switch tube connected in series; The middle node of each inverter branch is electrically connected to an inductor branch, and each inductor branch includes an output inductor and a common mode inductor connected in series in sequence from the middle node; For three of the four inductor branches, one end of the output inductor in each inductor branch electrically connected to one end of the common-mode inductor is respectively connected to one end of the output inductor in the remaining inductor branch electrically connected to one end of the common-mode inductor through a filter capacitor; For the four inductor branches, the other end of the common-mode inductor is electrically connected to a Y capacitor; the ends of the Y capacitors on the four inductor branches that are not electrically connected to the common-mode inductor are electrically connected to each other and are grounded; For at least one inductor branch among the four inductor branches, at least one node between one end of the output inductor and the other end of the output inductor is connected to the split capacitor branch.

8. The two-level inverter according to claim 7, characterized in that: For at least one of the four inductor branches, at least one node between one end of the output inductor and the other end of the output inductor is connected to the head end, the tail end or an intermediate node of the split capacitor branch.

9. A two-level inverter according to any one of claims 1 to 8, characterized in that: The upper switch tube and the lower switch tube are both NMOS tubes; the bus capacitor branch includes a bus capacitor C51 and a bus capacitor C52 connected in series.

10. A two-level inverter according to claim 3, 4, 7 or 8, characterized in that: The split capacitor branch includes a split capacitor C61 and a split capacitor C62 connected in series.

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