Image sensor

Abstract

An image sensor includes a semiconductor substrate including a plurality of pixels, a first surface, and a second surface opposite the first surface, and a device isolation layer in a trench that passes through the first surface and the second surface of the semiconductor substrate and separates the pixels from each other. The device isolation layer may include a conductive spacer layer extending from the first surface toward the second surface, an insulating liner interposed between the conductive spacer layer and the semiconductor substrate, and a cap spacer layer extending in a direction from the second surface to the first surface and contacting the conductive spacer layer.

Description

Technical Field

[0001] Various example embodiments relate to an image sensor. Background Art

[0002] The image sensor may include a plurality of pixels arranged in two dimensions. Each pixel may include a photodiode as a photoelectric conversion element, and a device isolation layer may be formed between the photoelectric conversion elements or may define the photoelectric conversion elements to separate the photoelectric conversion elements from each other. The device isolation layer may exhibit a light absorption effect depending on its material. Therefore, when light is absorbed on the light incident side, the intensity of light incident on the photoelectric conversion element may be reduced. Summary of the invention

[0003] Various example embodiments may provide an image sensor that significantly reduces optical loss, which may improve photoelectric conversion efficiency.

[0004] Alternatively or additionally, various example embodiments may provide an image sensor that significantly reduces optical loss while significantly reducing pixel defects to prevent degradation of the image sensor.

[0005] According to some example embodiments, an image sensor includes: a semiconductor substrate including a plurality of pixels, a first surface, and a second surface opposite to the first surface and having a first height; a device isolation layer in a groove, the groove penetrating the first surface and the second surface of the semiconductor substrate and separating the pixels from each other; and a microlens on the second surface. The device isolation layer may include a conductive separation layer having a second height less than the first height, a cover separation layer on the conductive separation layer to cover an upper surface of the conductive separation layer, and an insulating pad extending in a direction from the first surface to the second surface, contacting the conductive separation layer and having a height less than the first height and greater than or equal to the second height.

[0006] Alternatively or additionally, according to various example embodiments, an image sensor may include: a semiconductor substrate including a plurality of pixels, a first surface, and a second surface opposite to the first surface; a device isolation layer in a groove, the groove penetrating the first surface and the second surface of the semiconductor substrate and separating the pixels from each other; and a microlens provided on the second surface. Each pixel may include a photoelectric conversion element in the semiconductor substrate, and the upper surface of the semiconductor substrate of each pixel separated by the device isolation layer has a lens shape convex on one side, the lens shape being configured to refract the path of light incident on the upper surface of the semiconductor substrate so that the light travels to the photoelectric conversion element.

[0007] Alternatively or additionally, according to various example embodiments, an image sensor may include: a semiconductor substrate including a plurality of pixels, a first surface, and a second surface opposite to the first surface; a device isolation layer in a groove, the groove penetrating the first surface and the second surface of the semiconductor substrate and separating the pixels from each other; and a microlens on the second surface. The groove may define a first groove having a first width and a second groove having a second width greater than the first width. The device isolation layer may include a conductive separation layer within the first groove, a cover separation layer on the conductive separation layer to cover the upper surface of the conductive separation layer and within the second groove, and an insulating pad extending in a direction from the first surface to the second surface and between the semiconductor substrate and the conductive separation layer. The upper surface of the semiconductor substrate of each pixel separated by the device isolation layer has a lens shape convex on one side, and the lens shape is configured to refract the path of light incident on the upper surface of the semiconductor substrate so that the light travels to the photoelectric conversion element. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram of an image sensor according to various example embodiments.

[0010] Figure 2 is a plan view illustrating a portion of a pixel array according to some example embodiments.

[0011] Figure 3 is along Figure 2 A cross-sectional view taken along line AA'.

[0012] Figure 4 yes Figure 3 An enlarged cross-sectional view of portion P1.

[0013] Figure 5 is a cross-sectional view illustrating only a semiconductor substrate within a single pixel in an image sensor according to some example embodiments.

[0014] Fig. 6A is a cross-sectional view illustrating an image sensor according to some example embodiments, Figure 6B yes Fig. 6A is an enlarged view of part P2, and Figure 6C Only shows Fig. 6A A cross-sectional view of a semiconductor substrate within a single pixel in an image sensor is shown.

[0015] Fig. 7A is a cross-sectional view illustrating an image sensor according to some example embodiments, Figure 7B yes Fig. 7AAn enlarged view of part P3, and Figure 7C Only shows Fig. 7A A cross-sectional view of a semiconductor substrate within a single pixel in an image sensor is shown.

[0016] Figure 8 is a cross-sectional view illustrating an image sensor according to some example embodiments.

[0017] Fig. 9 and Fig.10 are cross-sectional views each illustrating an image sensor according to some example embodiments.

[0018] Fig.11 is a circuit diagram of a pixel in an image sensor according to some example embodiments.

[0019] Fig.12 is a plan view illustrating an image sensor according to some example embodiments.

[0020] FIG. 13A to FIG. 13E It is shown Fig.12 A conceptual plan view of a pixel array in a pixel array area of ​​. DETAILED DESCRIPTION

[0021] The present disclosure may be modified in various ways and may have various embodiments, wherein specific example embodiments will be described in detail with reference to the accompanying drawings. However, it should be understood that the description of the specific embodiments of the present disclosure is not intended to limit the present disclosure to a specific implementation mode, and the present disclosure will cover all modifications, equivalents and substitutes within the spirit and technical scope of the various described example embodiments.

[0022] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote the same elements, and redundant descriptions thereof will be omitted.

[0023] Figure 1 is a block diagram of an image sensor according to example embodiments.

[0024] refer to Figure 1 , an image sensor according to some example embodiments may include a pixel array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7, and an input / output buffer (I / O buffer) 8.

[0025] The pixel array 1 may include a plurality of pixels arranged in two dimensions and may convert an optical signal into an electrical signal. The pixel array 1 may be driven by a plurality of driving signals (such as one or more of a pixel selection signal, a reset signal, and a charge transfer signal from a row driver 3). In some example embodiments, the converted electrical signal may be provided to a correlated double sampler 6.

[0026] The row driver 3 may provide a plurality of driving signals to the pixel array 1 to drive a plurality of pixels based on the decoding result from the row decoder 2. When the pixels are arranged in a matrix form such as a rectangular or square form, a driving signal may be provided for each row.

[0027] The timing generator 5 may provide timing signals and control signals to the row decoder 2 and the column decoder 4 .

[0028] The correlated double sampler 6 may receive, hold and sample the electrical signal generated by the pixel array 1. The correlated double sampler 6 may perform a double sampling operation on a specific noise level and signal level of the electrical signal to output a difference level corresponding to the difference between the noise level and the signal level.

[0029] The analog-to-digital converter 7 may convert an analog signal corresponding to the difference level output from the correlated double sampler 6 into a digital signal. Then, the analog-to-digital converter 7 may output the converted digital signal.

[0030] The input / output buffer 8 may latch the digital signal, and may sequentially output the latched digital signal to a video signal processor (not shown) based on the decoding result from the column decoder 4 .

[0031] refer to Figure 1 Any or all of the elements described may be used with reference to Figure 1 For example, any element may communicate with any or all other elements described. Figure 1 Any or all other elements in the system may perform unidirectional and / or bidirectional and / or broadcast communication to transmit and / or exchange and / or receive information, such as but not limited to data and / or commands, in a manner such as serial and / or parallel via a bus such as a wireless and / or wired bus (not shown). The information may be encoded in various formats, such as analog and / or digital formats.

[0032] Figure 2 is a plan view showing a portion of a pixel array according to some example embodiments, Figure 3 It is along Figure 2 A cross-sectional view taken along line AA' of Figure 4 yes Figure 3 An enlarged cross-sectional view of a portion P1 of FIG. An image sensor according to some example embodiments may include a pixel array of pixels arranged two-dimensionally in a matrix form. In this regard, Figure 2 Four pixels of the pixel array are shown as an example; however, example embodiments are not limited thereto.

[0033] refer to Figures 2 to 4 , a pixel array of an image sensor according to some example embodiments may include a semiconductor substrate 110 provided with a photoelectric conversion element PD, a circuit interconnection layer 120 , a device isolation layer 130 , a color filter CF, a barrier pattern 150 , and a microlens ML.

[0034] The semiconductor substrate 110 may have a first surface 110a and a second surface 110b opposite to each other. The first surface 110a of the semiconductor substrate 110 may be or may be referred to as or may correspond to a front surface, and the second surface 110b may be or may be referred to as or may correspond to a rear surface. Light may be incident on the second surface 110b of the semiconductor substrate 110. In this case, the second surface 110b may be or may be referred to as a light incident surface.

[0035] The semiconductor substrate 110 may include a substrate formed of (or including) various semiconductor materials, for example, one or more of a silicon semiconductor substrate, a germanium semiconductor substrate, or a silicon germanium semiconductor substrate. The semiconductor substrate 110 may include an impurity having a first conductivity type, for example, an impurity concentration much greater than an impurity of a second conductivity type. Therefore, the semiconductor substrate 110 may have a first conductivity type. The impurity having the first conductivity type may be a group III element. For example, the impurity having the first conductivity type may include a P-type impurity, such as at least one of aluminum (Al), boron (B), indium (In), and / or gallium (Ga). In some example embodiments, the concentration of the impurity may be constant throughout the thickness direction of the semiconductor substrate 110; however, example embodiments are not limited thereto, and the concentration of the impurity may be non-constant (for example, concave, convex, concave-convex, etc.).

[0036] In the semiconductor substrate 110, a photoelectric conversion element PD may be provided for each pixel PX. The photoelectric conversion element PD may be interposed between the first surface 110a and the second surface 110b of the semiconductor substrate 110. The photoelectric conversion element PD may be a doped region including impurities having a second conductivity type opposite to the first conductivity type; for example, the concentration of the impurities of the second conductivity type may be much greater than the concentration of the impurities of the first conductivity type. In some example embodiments, the photoelectric conversion element PD may include a group V element, and the group V element may be an impurity having a second conductivity type. The impurities having the second conductivity type may include N-type impurities, such as one or more of phosphorus, arsenic, bismuth, and / or antimony.

[0037] The photoelectric conversion element PD may be provided within the semiconductor substrate 110 , and may be disposed at a position spaced apart from the second surface 110 b .

[0038] The circuit interconnection layer 120 may be provided on the first surface 110a of the semiconductor substrate 110. The circuit interconnection layer 120 may include a circuit unit 121 including a gate pattern 121a and a gate insulating pattern 121b.

[0039] The gate pattern 121a may be disposed on the first surface 110a of the semiconductor substrate 110. The gate pattern 121a may be used as a gate electrode for one or more of a transfer transistor, a source follower transistor, a reset transistor, or a selection transistor for driving an image sensor. For example, the gate pattern 121a may include or may correspond to one or more of a transfer gate, a source follower gate, a reset gate, or a selection gate. In the accompanying drawings, for ease of description, a single gate pattern 121a is shown as being disposed in each pixel. However, example embodiments are not limited thereto, and a plurality of gate patterns 121a may be disposed in each pixel. The gate pattern 121a may have a buried gate structure, but example embodiments are not limited thereto. Unlike shown in the figure, the gate pattern 121a may have a planar gate structure. The gate pattern 121a may include a metal material, a metal silicide material, polysilicon, or a combination thereof.

[0040] The gate insulating pattern 121b may be interposed between the gate pattern 121a and the semiconductor substrate 110. The gate insulating pattern 121b may include, for example, a silicon-based insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride and / or a high-κ dielectric material such as hafnium oxide and / or aluminum oxide having a dielectric constant greater than that of silicon oxide.

[0041] The circuit interconnection layer 120 may further include a lower insulating layer 123 and an interconnection structure 125. The lower insulating layer 123 may cover the first surface 110a of the semiconductor substrate 110 and may be provided to have a multi-layer structure. The lower insulating layer 123 may include, for example, a silicon-based insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0042] The interconnection structure 125 may be provided within the stacked lower insulating layer 123. The interconnection structure 125 may include an interconnection portion and a via portion. The interconnection portion may be provided in the lower insulating layer 123 and may be electrically connected to one of the impurity doped region and the gate pattern 121a. The interconnection portion may be interposed between two adjacent lower insulating layers. The via portion of the interconnection structure 125 may be connected to the interconnection portion through at least one of the lower insulating layers 123. The interconnection structure 125 may receive a photoelectric signal output from the photoelectric conversion element PD. Although the number of layers of the interconnection structure 125 is shown as five, example embodiments are not limited thereto, and the number of layers of the interconnection structure 125 may be greater than or less than five. Additionally or alternatively, at least one geometric and / or electrical property (such as at least one of thickness, width, spacing, or pitch) of different interconnection structures 125 may be the same or different from other interconnection structures 125.

[0043] The device isolation layer 130 may be provided within the semiconductor substrate 110 and may separate and partition the pixels PX. For example, the device isolation layer 130 may be provided between the pixels PX of the semiconductor substrate 110.

[0044] A device isolation layer 130 may be provided in a trench TCH penetrating the first surface 110 a and the second surface 110 b of the semiconductor substrate 110 to separate the pixels PX.

[0045] The device isolation layer 130 may be provided in the trench TCH, and the trench TCH may be recessed from the first surface 110a of the semiconductor substrate 110. The trench TCH may include a first trench TCH1 extending from the first surface 110a toward the second surface 110b and a second trench TCH2 extending from the second surface 110b toward the first surface 110a. When viewed in a cross section, unlike the first trench TCH1, the second trench TCH2 is recessed only by a depth (e.g., a predetermined depth, or alternatively, a dynamically determined depth) from the second surface 110b of the semiconductor substrate 110 and does not penetrate the semiconductor substrate 110.

[0046] The device isolation layer 130 may include a conductive separation layer 131 extending from the first surface 110a toward the second surface 110b, an insulating pad 133 extending from the first surface 110a toward the second surface 110b and interposed between the conductive separation layer 131 and the semiconductor substrate 110, and a cover separation layer 135 extending from the second surface 110b toward the first surface 110a and contacting the conductive separation layer 131.

[0047] A portion of the device isolation layer 130 (eg, the conductive spacer layer 131) may be or may correspond to a deep trench isolation (DTI) layer. Another portion of the device isolation layer 130 (eg, the cap spacer layer 135) may be or may correspond to a device isolation layer formed to have a smaller depth than the deep device isolation layer.

[0048] In some example embodiments, the conductive separation layer 131 may be formed of a conductive material or may include a conductive material. For example, the conductive separation layer 131 may be formed of a material containing doped polysilicon and / or a metal or may include a material containing doped polysilicon and / or a metal. The dopant of the doped polysilicon may include an impurity having a first conductivity type and / or an impurity having a second conductivity type. In some example embodiments, the impurity concentration of the impurity of the first conductivity type may be much greater than or much less than the impurity concentration of the impurity of the second conductivity type. When the conductive separation layer 131 includes a metal, tungsten, aluminum, etc. may be used. However, example embodiments are not limited thereto, and alternatively or additionally, other materials having conductivity, such as various metals, alloys thereof, or doped inorganic materials may also be used.

[0049] The conductive layer 131 may be configured to receive a negative bias. For example, a negative bias voltage may be applied to the conductive separation layer 131 for stably collecting holes near the interface of the conductive separation layer 131 in a region adjacent to the device isolation layer 130. The interconnect may be connected to the first surface 110a and / or the second surface 110b to apply a negative bias voltage to the conductive separation layer 131.

[0050] The conductive separation layer 131 may fill the first trench TCH1 penetrating the first surface 110a and the second surface 110b of the semiconductor substrate 110. However, in the case of the conductive separation layer 131, light transmittance is low, so that the conductive separation layer 131 is not provided on the light incident surface (e.g., a portion close to the second surface 110b), which may significantly increase the amount of light incident. In some example embodiments, the second trench TCH2 may not be filled with the conductive separation layer 131. A cap separation layer 135 may be provided in the second trench TCH2 formed from a predetermined depth to the second surface 110b.

[0051] In some example embodiments, the length of the conductive separation layer 131 in a direction perpendicular to the first surface 110a may be greater than the length of the cover separation layer 135. For example, the length of the conductive separation layer 131 may be at least twice the length of the cover separation layer 135.

[0052] The insulating liner 133 may extend from the first surface 110a toward the second surface 110b, and may be provided along the periphery of the conductive separation layer 131. The insulating liner 133 may be provided between the semiconductor substrate 110 and the conductive separation layer 131 to electrically insulate the conductive separation layer 131 from the semiconductor substrate 110. For example, the conductive separation layer 131 may be spaced apart from the semiconductor substrate 110 by the insulating liner 133. Therefore, when the image sensor operates, the conductive separation layer 131 may be electrically isolated from the semiconductor substrate 110.

[0053] The insulating liner 133 may include, for example, a silicon-based insulating material (eg, silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 , silicates) and / or silicon carbonitride (SiCN) and / or high-κ dielectric constant metal oxides (e.g., hafnium oxide (HfO x ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 , aluminum oxide), etc.).

[0054] The insulating liner 133 may cover all side surfaces of the first trench TCH1. The insulating liner 133 may be provided to have a height smaller than the semiconductor substrate 110. The insulating liner 133 may be formed to be at least longer than the conductive separation layer 131 and protrude upward from the conductive separation layer 131. For example, the insulating liner 133 may have a protrusion PR protruding upward from a surface formed by the upper surface of the conductive separation layer 131 toward the second surface 110b.

[0055] For example, with respect to the first surface 110a, when the distance from the first surface 110a to the second surface 110b is defined as the first height h1, the length of the conductive separation layer 131 in the direction from the first surface 110a to the second surface 110b is defined as the second height h2, and the length of the insulating liner 133 in the direction from the first surface 110a to the second surface 110b is defined as the third height h3, the second height h2 may be smaller than the first height h1. And the third height h3 may be smaller than the first height h1 and greater than the second height h2.

[0056] The insulating pad 133 may be formed of or may include an insulating material, such as a silicon-based insulating material (eg, silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2, silicates) and / or silicon carbonitride (SiCN)) and / or high-κ dielectric constant metal oxides (e.g., hafnium oxide (HfO x ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 , aluminum oxide), etc.) one or more.

[0057] In some example embodiments, the insulating liner 133 is shown as being formed as a single layer, but example embodiments are not limited thereto. In some example embodiments, the insulating liner 133 may include a plurality of layers, and the plurality of layers may be formed of or include the same and / or different materials.

[0058] The insulating liner 133 may be formed of or may include a material having a lower refractive index than the semiconductor substrate 110. Therefore, the possibility of occurrence and / or the influence of occurrence of crosstalk between pixels PX may be prevented or reduced. The conductive spacer layer 131 may be spaced apart from the semiconductor substrate 110 by the insulating liner 133. Therefore, when the image sensor operates, the conductive spacer layer 131 may be electrically isolated from the semiconductor substrate 110.

[0059] A capping separation layer 135 may be provided on the conductive separation layer 131 .

[0060] The cover spacer layer 135 may include a transparent conductive material or may be formed of a transparent conductive material. For example, the cover spacer layer 135 may include a material having a transmittance of about 70% or more (e.g., 80% or more) and may have both high conductivity and low resistance. For example, the cover spacer layer 135 may have a conductivity greater than 103 S / cm and a resistance less than or equal to 10 -3 The band gap of the material may be larger than that of visible light, so that visible light passes through without being absorbed, and may have a band gap of, for example, 3.5 eV (400 nm) or more.

[0061] Alternatively or additionally, the cover spacer layer 135 may have a refractive index different from that of the semiconductor substrate 110. The cover spacer layer 135 has a refractive index different from that of the semiconductor substrate 110 so that a light path may be refracted at an interface between the cover spacer layer 135 and the semiconductor substrate 110. In some example embodiments, a material of the cover spacer layer 135 may be selected from a material having a refractive index smaller than that of the semiconductor substrate 110 or a material having a refractive index greater than that of the semiconductor substrate 110.

[0062] The material of the cover spacer layer 135 is not limited to a specific material. For example, the cover spacer layer 135 may be formed of a material including at least one of an organic insulating material and an inorganic insulating material, or may include a material including at least one of an organic insulating material and an inorganic insulating material. The cover spacer layer 135 may include at least one of silicon oxide, hafnium oxide, silicon nitride, silicon carbon nitride, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, erbium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, aluminum nitride, hafnium nitride, or aluminum oxynitride. In some example embodiments, the cover spacer layer may include silicon oxide or hafnium oxide.

[0063] The capping spacer 135 may be formed in the second trench TCH2 formed by removing the conductive spacer 131 and a portion of the semiconductor substrate 110 adjacent to the conductive spacer 131. In this case, the length or diameter of the second trench TCH2 provided with the capping spacer 135 may be greater than the length or diameter of the first trench TCH1 provided with the conductive spacer 131. For example, the capping spacer 135 may be provided with a width greater than the width w of the conductive spacer 131 or greater than the sum of the widths of the conductive spacer 131 and the insulating liner 133. For example, when the sum of the widths of the conductive spacer 131 and the insulating liner 133 is referred to as the first width w1 and the width of the capping spacer 135 is referred to as the second width w2, the second width w2 may be greater than the first width w1.

[0064] The lower surface of the cover spacer layer 135 may be in contact or in direct contact with the upper surface of the conductive spacer layer 131. As described above, the width of the cover spacer layer 135 is formed to have a greater width than the conductive spacer layer 131, and the lower surface of the cover spacer layer 135 is provided to be in direct contact with the upper surface of the conductive spacer layer 131, so that the cover spacer layer 135 can completely cover the upper surface of the conductive spacer layer 131.

[0065] The cover separation layer 135 is formed to have a greater width than the conductive separation layer 131 and the insulating liner 133 so that a protrusion PR protruding upward from at least a portion of the insulating liner 133 (eg, relative to the conductive separation layer 131 ) may be provided in the cover separation layer 135 .

[0066] In some example embodiments, the device isolation layer 130 may be formed in various forms and / or in various ways. According to some example embodiments, the device isolation layer 130 may undergo the following process: forming a first trench TCH1 from the first surface 110a to the second surface 110b, conformally forming an insulating liner 133 in the first trench TCH1, filling the first trench TCH1 with the material of the conductive separation layer 131, and, for example, inverting and removing a portion of the semiconductor substrate 110 on one side of the second surface 110b by chemical mechanical polishing (CMP) and / or an etch-back process. In some example embodiments, before inversion, the second surface 110b may be, for example, passivated and may have a film such as a hard mask and / or a photoresist deposited thereon. Then, a second trench TCH2 may be formed by a process such as etching (such as isotropic etching), and the capping separation layer 135 may fill the second trench TCH2. When the second trench TCH2 is formed, an etching process may be performed to remove portions of the conductive separation layer 131 and the semiconductor substrate 110 , and the insulating liner 133 may be etched or remain without being etched.

[0067] In the above process, residues may be generated on the surface of the conductive spacer layer 131 by chemical mechanical polishing and / or blanket etching. When the residues on the surface of the conductive spacer layer 131 exist between the conductive spacer layer 131 and the semiconductor substrate 110, it may be difficult to electrically insulate the conductive spacer layer 131 and the semiconductor substrate 110, and charges may be accumulated by the bias applied to the conductive spacer layer 131, which may cause image degradation. In various example embodiments, the image sensor may use a cover spacer layer 135 to effectively cover the surface of the conductive spacer layer 131 exposed during the manufacturing process to suppress or reduce the possibility of electrons from the conductive spacer layer 131 moving to one side of the semiconductor substrate 110 (e.g., one side of the photoelectric conversion element PD). As a result, image degradation can be significantly reduced. The insulating liner 133 may have a protrusion PR to separate the conductive spacer layer 131 and the semiconductor substrate 110 from each other without contacting each other. As a result, electrical insulation between the conductive spacer layer 131 and the semiconductor substrate 110 can be promoted or improved.

[0068] The color filter CF may be provided on the semiconductor substrate 110 on which the photoelectric conversion element PD and the device isolation layer 130 are formed.

[0069] The color filter CF may be provided on the second surface 110b of the semiconductor substrate 110 for each pixel PX. For example, the color filter CF may be provided at a position corresponding to the photoelectric conversion element PD. Each color filter CF may be selected as one of a plurality of reference colors. A plurality of reference colors may include, for example, red-green-blue (RGB), red-green-blue-white (RGBW), cyan-magenta-yellow (CMY), cyan-magenta-yellow-black (CMYK), red-yellow-blue (RYB) and RGB infrared (RGBIR). For example, the color filter CF may be arranged in a Bayer pattern. However, the color of the color filter CF is not limited thereto, and color filters of other colors may be provided. The color filter CF may constitute a color filter array.

[0070] The fence pattern 150 may be disposed on the device isolation layer 130. For example, the fence pattern 150 may overlap vertically with the device isolation layer 130. The fence pattern 150 may have a planar shape corresponding to the shape of the device isolation layer 130. For example, when viewed in a plan view, the fence pattern 150 may have a grid shape. When viewed in a plan view, the fence pattern 150 may surround the color filter CF. The fence pattern 150 may be interposed between two adjacent color filters CF. A plurality of color filters CF may be physically and optically separated from each other by the fence pattern 150. The fence pattern 150 may include a low refractive index material. The low refractive index material may include a polymer and silicon dioxide nanoparticles in the polymer. The low refractive index material may have insulating properties. Alternatively or additionally, the fence pattern 150 may include a metal and / or a metal nitride. For example, the fence pattern 150 may include titanium and / or titanium nitride.

[0071] The upper insulating layer 140 may be interposed between the semiconductor substrate 110 and the color filter CF and between the device isolation layer 130 and the fence pattern 150. The upper insulating layer 140 may cover the second surface 110b of the semiconductor substrate 110 and the upper surface of the device isolation layer 130. The upper insulating layer 140 may include a plurality of layers. For example, the upper insulating layer 140 may include an anti-reflection layer.

[0072] In some example embodiments, at least a portion of the upper insulating layer 140 may include the same material as the cap spacer layer 135 or at least one material that is the same as the cap spacer layer 135. In this case, the cap spacer layer 135 and at least a portion of the upper insulating layer 140 may be formed using the same material in a single process such as deposition (such as in-situ deposition). In this case, the cap spacer layer 135 may be more easily formed simultaneously in a subsequent process of forming the upper insulating layer 140 without the need to additionally form the cap spacer layer 135. However, the material of the upper insulating layer 140 is not limited thereto, and the upper insulating layer 140 may be separately formed using a material different from that of the cap spacer layer 135 through a different process.

[0073] For example, the upper insulating layer 140 may also include an insulating pattern layer having a high κ dielectric constant greater than the dielectric constant of silicon oxide. The insulating pattern layer may be formed of a material having a dielectric constant substantially the same as or higher than the dielectric constant of the insulating liner 133, or may include a material having a dielectric constant substantially the same as or higher than the dielectric constant of the insulating liner 133. The material used for the insulating pattern layer may include, for example, one or more of silicon nitride, silicon oxide, silicon carbon nitride and / or a high κ dielectric constant metal oxide. The high κ dielectric constant metal oxide may include, for example, one or more of hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, erbium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, aluminum nitride, hafnium nitride or aluminum oxynitride, etc. This high κ dielectric constant can be used to significantly suppress or reduce the generation of abnormal charges on the second surface 110 b of the semiconductor substrate 110 .

[0074] The microlens ML may be disposed on the second surface 110b of the semiconductor substrate 110. For example, the microlens ML may be disposed on the color filter CF and the fence pattern 150. The microlens ML may include a lens pattern and a planarization portion. The planarization portion of the microlens ML may be disposed on the color filter CF. A lens pattern may be provided on the planarization portion. The lens pattern may be formed to be integrated with the planarization portion and may be connected to the planarization portion without an interface. The lens pattern may include the same material as the planarization portion or may be formed of the same material as the planarization portion. As another example, the planarization portion may be omitted and the lens pattern may be directly disposed on the color filter CF. The lens pattern may be hemispherical. The lens pattern may focus incident light. The lens pattern may be provided at a position corresponding to the photoelectric conversion element PD of the semiconductor substrate 110. For example, the lens pattern may be provided on the photoelectric conversion device PD in the pixel (PX) region of the semiconductor substrate 110.

[0075] The microlens ML may be transparent and transmit light. The microlens ML may include an organic material such as a polymer. For example, the microlens ML may include a photoresist material and / or a thermosetting resin.

[0076] In some example embodiments, the color filter CF, the fence pattern 150, and / or the microlens ML have been described as being provided at overlapping positions corresponding to the corresponding pixels PX, but example embodiments are not limited thereto. At least one of the color filter CF, the fence pattern 150, and the microlens ML may have an offset structure that is offset by a predetermined degree from the position corresponding to each pixel PX. Such an offset structure may be caused by a process margin of the color filter CF, the fence pattern 150, and / or the microlens ML, or may be intentionally selected to optimize or improve the light path in consideration of the angle of light traveling from the outside to the pixel PX, etc.

[0077] The image sensor having the above structure can significantly increase the amount of light incident on the photoelectric conversion element PD by removing a portion of the conductive separation layer 131 having relatively high light absorptivity and low light transmittance from the side where light is incident on the photoelectric conversion element PD.

[0078] This will now be described in more detail. The conductive spacer layer 131 may be formed of or may include a conductive material such as doped polysilicon. The conductive spacer layer 131 formed of polysilicon may absorb incident light, and thus may reduce the amount of light entering the photoelectric conversion element PD. In some example embodiments, the conductive spacer layer 131 within a specific depth (e.g., a predetermined depth) may be removed from the second surface 110b onto which light is incident, and a cover spacer layer 135 may be formed instead. The cover spacer layer 135 is formed of a transparent material so that the transparent material does not absorb light, and the loss of light entering the photoelectric conversion element PD may be significantly reduced. Therefore, the amount of light provided to the photoelectric conversion element PD may be increased.

[0079] Alternatively or additionally, the conductive spacer layer 131 may be applied with a negative bias for more stably collecting holes near the interface of the conductive spacer layer 131 in a region adjacent to the device isolation layer 130. Defects such as dark current may be reduced, and the sensitivity of the image sensor may be improved.

[0080] Alternatively or additionally, according to some example embodiments, a focusing effect may be obtained by a device isolation layer. Figure 5 Describe this in detail.

[0081] Figure 5 is a cross-sectional view illustrating only a semiconductor substrate within a single pixel in an image sensor according to some example embodiments.

[0082] refer to Figures 3 to 5, the semiconductor substrate corresponding to each pixel may be patterned into a shape that allows focusing during the formation of the device isolation layer. For example, the semiconductor substrate may be patterned into an upwardly convex shape to refract the path of light incident on the upper surface of the semiconductor substrate so that the light travels in the direction of the photoelectric conversion element.

[0083] In the image sensor according to various example embodiments, the device isolation layer 130 may be formed to be wider near the second surface 110b so that the shape of the semiconductor substrate 110 in each pixel PX may be convex upward. For example, the device isolation layer 130 has a larger width near the second surface 110b than near the first surface 110a, so the semiconductor substrate 110 may have a smaller width near the second surface 110b than near the first surface 110a. Alternatively or additionally, in the actual manufacture of the image sensor, when patterning is performed by a process such as etching, there may be a difference based on a process margin. Therefore, when viewed in a cross section, the semiconductor substrate 110 may have a certain degree of inclination and curvature as shown by the dotted line, rather than a straight line structure as shown in the figure. Therefore, the shape of the upper surface of the semiconductor substrate 110 may be a rectangular shape with at least some rounded corners or beveled corners, rather than a completely angled shape. This shape difference may affect the refraction of light passing between the semiconductor substrate 110 and the device isolation layer 130. For example, when the semiconductor substrate is formed to be convex upward as in various example embodiments, the semiconductor substrate may be used as a convex lens.

[0084] In summary, the width of the semiconductor substrate 110 according to some example embodiments may be controlled so that the refracted light is directed toward the photoelectric conversion element PD as much as possible. To this end, the width of the device isolation layer 130 may be changed. When the semiconductor substrate 110 is manufactured to have a shape substantially similar to that of a convex lens by changing the shape of the device isolation layer 130, the focus of the convex lens may be set to be placed as much as possible within the photoelectric conversion element PD.

[0085] As described above, according to some example embodiments, the upper surface of the semiconductor substrate 110 of each pixel PX separated by the device isolation layer 130 has a convex lens shape having an upper surface convex upward, so that the amount of light incident on the photoelectric conversion element PD can be significantly increased. As a result, the sensitivity of the image sensor can be improved.

[0086] According to some example embodiments, the device isolation layer can be modified in various ways within the inventive concept of the present disclosure. The example embodiments to be described later are some of the various modifications within the inventive concept of the present disclosure, and can be combined with each other within the limits of compatibility. In the following example embodiments, for ease of description, the differences from the above-mentioned embodiments will be mainly described.

[0087] Fig. 6A is a cross-sectional view illustrating an image sensor according to some example embodiments, Figure 6B yes Fig. 6A is an enlarged view of part P2, and Figure 6C Only shows Fig. 6A A cross-sectional view of a semiconductor substrate within a single pixel in an image sensor is shown.

[0088] refer to FIG. 6A to FIG. 6C , the cover separation layer 135 may have a stepped shape in which the width gradually increases in a direction toward the second surface 110 b when viewed in a cross section.

[0089] The capping spacer 135 may be formed by etching the second trench TCH2 on the semiconductor substrate 110 to have a shape having a plurality of steps and then filling the second trench TCH2 with a material of the capping spacer 135 .

[0090] In some example embodiments, the second trench TCH2 may have three steps as shown. In some example embodiments, the second trench TCH2 may have more than three steps. In the second trench TCH2, the distance between the facing steps ST may increase in an upward direction (e.g., in a direction toward the second surface 110b). As a result, the capping spacer 135 may also have a width that increases in an upward direction (e.g., in a direction toward the second surface 110b).

[0091] In some example embodiments, similar to the above example embodiments, the device isolation layer 130 has a larger width in a portion close to the second surface 110b than in a portion close to the first surface 110a, so that the semiconductor substrate 110 may have a smaller width in a portion close to the second surface 110b than in a portion close to the first surface 110a. Alternatively or additionally, in the actual manufacture of the image sensor, when patterning is performed by a process such as etching, there is a difference based on the process margin. Therefore, when viewed in a cross section, the semiconductor substrate 110 may have a certain degree of inclination and curvature as shown by the dotted line, rather than a straight line structure as shown in the figure. As a result, in some example embodiments, the semiconductor substrate 110 may have a lens shape that convexes upward for each pixel PX. Due to this shape, light passing between the semiconductor substrate 110 and the device isolation layer 130 can travel to one side of the photoelectric conversion element PD.

[0092] In some example embodiments, the heights and / or widths of the steps ST may be the same as or different from each other.The heights and / or widths of the steps ST may be changed in various ways so that the refracted light is guided toward the photoelectric conversion element PD as much as possible.

[0093] Fig. 7A is a cross-sectional view illustrating an image sensor according to some example embodiments, Figure 7B yes Fig. 7A An enlarged view of part P3, and Figure 7C Only shows Fig. 7A A cross-sectional view of a semiconductor substrate within a single pixel in an image sensor is shown.

[0094] refer to 7A to 7C , the cover spacer layer 135 may have an inclined portion having a width that increases in a direction toward the second surface 110 b when viewed in a cross section.

[0095] The capping spacer 135 may be formed by etching the second trench TCH2 to have an inclined portion when forming the second trench TCH2 on the semiconductor substrate 110 and then filling the second trench TCH2 with a material of the capping spacer 135 .

[0096] In some example embodiments, the second trench TCH2 may have an inclined surface having a predetermined angle θ with respect to the second surface 110b. In some example embodiments, the second trench TCH2 may have a plurality of inclined surfaces sequentially having different angles with respect to the second surface 110b.

[0097] In the second trench TCH2 filled with the capping spacer layer 135, the distance between the facing steps ST may increase in an upward direction (eg, a direction toward the second surface 110b). As a result, the capping spacer layer 135 may also have a width increasing in an upward direction (eg, a direction toward the second surface 110b).

[0098] Due to the inclined surface, the semiconductor substrate 110 corresponding to each pixel PX may have a lens shape that is convex upward. In this case, the number of inclined surfaces, the angle at which the inclined surface intersects the second surface 110b, and the size of the inclined surface may be changed in various ways so that the refracted light is guided toward the photoelectric conversion element PD as much as possible.

[0099] In some example embodiments, the semiconductor substrate 110 may have a lens shape that is convex upward for each pixel PX. Due to this shape, light passing between the semiconductor substrate 110 and the device isolation layer 130 may travel to one side of the photoelectric conversion element PD.

[0100] In some example embodiments, the device isolation layer 130 may be provided in a form different from that of the above-described embodiments.

[0101] Figure 8 is a cross-sectional view illustrating an image sensor according to some example embodiments.

[0102] refer to Figure 8 , the insulating liner 133 may be formed to have the same length as the conductive separation layer 131. For example, the heights of the insulating liner 133 and the conductive separation layer 131 in the direction from the first surface 110a to the second surface 110b may be the same, and the protrusion PR of the insulating liner 133 protruding into the cover separation layer 135 may not be provided in the present embodiment.

[0103] Relative to the first surface 110a, when the distance from the first surface 110a to the second surface 110b is defined as a first height h1, the length of the conductive separation layer 131 in the direction from the first surface 110a to the second surface 110b is defined as a second height h2, and the length of the insulating pad 133 in the direction from the first surface 110a to the second surface 110b is defined as a third height h3, the second height h2 can be less than the first height h1, and the third height h3 can be the same as the second height h2.

[0104] In some example embodiments, the conductive separation layer 131 may be provided in the first trench TCH1, and the cap separation layer 135 may be provided in the second trench TCH2 having a greater width than the first trench TCH1. Therefore, similar to the above example embodiments, the semiconductor substrate 110 of each pixel PX may have a lens convex upward. As a result, even in this embodiment, a focusing effect based on the shape of the semiconductor substrate 110 may be obtained.

[0105] refer to Figure 8 , the cover spacer layer 135 does not include a step. However, in some example embodiments, the cover spacer layer 135 may include a layer similar to Fig. 6A and Figure 6B In addition, Figure 8 In the example embodiment shown, the cover spacer layer 135 does not include an inclined surface. However, in some example embodiments, the cover spacer layer 135 may alternatively or additionally include a Fig. 7A and Figure 7B The inclined surface in the form of.

[0106] Since the capping spacer layer 135 has a shape having a greater width than the conductive spacer layer 131, the semiconductor substrate 110 corresponding to each pixel PX may have an upwardly convex lens shape. As a result, light refracted and incident on the semiconductor substrate 110 may be guided toward the photoelectric conversion element PD as much as possible.

[0107] An image sensor according to some example embodiments may further include a member for preventing or reducing defects that may occur due to an etching process performed during the formation of the cap spacer layer.

[0108] Fig. 9 and Fig.10 are cross-sectional views each illustrating an image sensor according to various example embodiments.

[0109] refer to Fig. 9 and Fig.10 , the semiconductor substrate 110 may include an impurity-doped region DPA spaced apart from the photoelectric conversion element PD and extending from the second surface 110 b to a predetermined depth.

[0110] The impurity-doped region DPA may correspond to a region doped with impurities of a conductivity type opposite to the conductivity type of the impurities in the photoelectric conversion element PD. In some examples, the impurity-doped region DPA may also include impurities of the same conductivity type as the conductivity type of the photoelectric conversion element PD, but at a much lower impurity concentration. For example, when the photoelectric conversion element PD is doped with impurities of a second conductivity type, the impurity-doped region DPA may be doped with impurities of a first conductivity type opposite to the second conductivity type.

[0111] When the photoelectric conversion element PD is a second conductivity type region (e.g., an N-type impurity-doped region), the impurity-doped region DPA may be a first conductivity type region (e.g., a P-type impurity-doped region). Conversely, when the photoelectric conversion element PD is a first conductivity type region (e.g., a P-type impurity-doped region), the impurity-doped region (DPA) may be a second conductivity type region (e.g., an N-type impurity-doped region).

[0112] The impurity-doped region DPA may be formed from the second surface 110b to a depth greater than the depth at which the cover spacer layer 135 is formed, and to a depth less than the depth at which the photoelectric conversion element PD is formed. For example, when the cover spacer layer 135 is formed to a depth d1 from the second surface 110b and the impurity-doped region DPA is formed to a depth d2 from the second surface 110b, d2 may be greater than d1. In some cases, when the photoelectric conversion element PD is disposed at a distance d3 from the second surface 110b, d2 may be less than d3. For example, the impurity-doped region DPA may be formed to a depth less than the depth at which the photoelectric conversion element PD is formed.

[0113] According to some example embodiments, the impurity-doped region DPA may reduce or prevent pixel defects. According to some example embodiments, in order to form a cap spacer 135 covering the upper surface of the conductive spacer layer 131 and having a greater width than the conductive spacer layer 131, the semiconductor substrate 110 may undergo an etching process of removing a portion of the semiconductor substrate 110 to form a second trench TCH2. After the etching process, a transparent insulating material may fill the second trench TCH2 to form the cap spacer 135. When such a process is performed, an interface defect may occur between the semiconductor substrate 110 and the cap spacer 135 or the upper insulating layer 140, and an etching residue may be generated on the interface between the cap spacer 135 and the semiconductor substrate 110 within the second trench TCH2. Charges may accumulate in the interface defects or residues, and the accumulated charges may cause pixel defects in the image device. For example, the conductive spacer layer 131 may be negatively biased. When the conductive spacer layer 131 is not sufficiently covered by the cap spacer layer 135, defects caused by pixel defects may occur more frequently in a portion adjacent to the photoelectric conversion element PD. However, in some example embodiments, the impurity-doped region DPA may be doped with impurities of a conductivity type opposite to that of the photoelectric conversion element PD to prevent or reduce charges (electrons) accumulated on the interface between the semiconductor substrate 110 and the capping spacer layer 135 or charges (electrons) moved from the conductive spacer layer 131 from moving to the photoelectric conversion element PD. As a result, the image sensor according to some example embodiments may reduce or prevent pixel defects.

[0114] The above-described image sensor may be implemented in various forms. Hereinafter, detailed examples of pixels in an image sensor according to some example embodiments will be described.

[0115] Fig.11 is a circuit diagram of a pixel in an image sensor according to some example embodiments.

[0116] refer to Fig.11 , the pixel array may include a plurality of pixels, and the pixels may be arranged in a matrix form such as a rectangular (e.g., square) form. Each pixel may include a transfer transistor TX and logic transistors RX, SX, and DX. The logic transistor may include a reset transistor RX, a select transistor SX, and a source follower transistor DX. The transfer transistor TX may have a transfer gate TG. Each pixel may also include a photoelectric conversion element PD and a floating diffusion region FD. The geometry and / or electrical properties of each of the transfer transistor TX and the logic transistors RX, SX, and DX may be the same as or may be different from each other.

[0117] The photoelectric conversion element PD may generate and accumulate photocharges in proportion to the amount of external incident light. The photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX may transfer the charge generated by the photoelectric conversion element PD to the floating diffusion region FD. The floating diffusion region FD may receive the charge generated by the photoelectric conversion element (PD) and may cumulatively store the received charge.

[0118] The source follower transistor DX may be controlled according to the amount of photo charges accumulated in the floating diffusion region FD.

[0119] The reset transistor RX may periodically reset the charge accumulated in the floating diffusion region FD. The reset transistor RX may include a drain electrode connected to the floating diffusion region FD and a supply voltage V DD When the reset transistor RX is turned on, the power supply voltage V connected to the source electrode of the reset transistor RX DD may be applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD may be released to reset the floating diffusion region FD.

[0120] The source follower transistor DX can be used as a source follower buffer amplifier. The source follower transistor DX can amplify the potential change in the floating diffusion region FD and output the amplified potential change to the output line V OUT .

[0121] The selection transistor SX can select the pixels to be read in units of rows. When the selection transistor SX is turned on, the power supply voltage V DD can be applied to the drain electrode of the source follower transistor DX.

[0122] The above circuit diagram is an example and can be changed according to the pixel structure and the driving method. For example, two or more photoelectric conversion elements can be provided for each pixel. Therefore, the driving method can also be appropriately changed.

[0123] Fig.12 is a plan view illustrating an image sensor according to some example embodiments, and FIG. 13A to FIG. 13E It is shown Fig.12 A conceptual plan view of a pixel array in a pixel array area of ​​.

[0124] refer to Fig.12 and FIG. 13A to FIG. 13E, when viewed in a plan view, the image sensor may include a pixel array area PA, an optical black area OB, and a pad area PDA. When viewed in a plan view, the pixel array area PA may be disposed in a central portion of the image sensor. The pixel array area PA may be provided with a pixel array in which a plurality of pixels PX are arranged in a matrix.

[0125] The pixel PX may output a photoelectric signal from incident light. The pixels may be arranged two-dimensionally, forming rows and columns at the same time. The rows may be parallel to the first direction D1, and the columns may be consistent with the second direction D2. The number of rows may be the same as or different from the number of columns.

[0126] The pad area PDA may be an edge area of ​​the image sensor. When viewed in a plan view, the pad area PDA may surround the pixel array area PA. A bonding pad BP may be provided on the pad area PDA. The bonding pad BP may output an electrical signal generated from the pixel PX to the outside. Alternatively, an external electrical signal and / or voltage may be transmitted to the pixel PX through the bonding pad BP. Since the pad area PDA is an edge area of ​​the semiconductor substrate 110, the bonding pad BP may be easily connected to the outside. The optical black area OB and the pad area PDA may be provided outside the pixel array area PA.

[0127] The optical black area OB may be interposed between the pixel array area PA and the pad area PDA. Similar to the pixel array (APS) area, the optical black area OB may include both a portion having the photosensitive element PD and a portion not having the photosensitive element PD.

[0128] In the above-mentioned pixel array area, the image sensor according to some example embodiments may be applied to various structures according to a pixel array, a combination of color filters, etc. For example, the image sensor may be applied to various structures such as a so-called tetracell, 2PD, and Q-cell, and FIG. 13A to FIG. 13E A portion of such an example is shown.

[0129] refer to Fig.13A , the pixel array area PA may be provided with a pixel array including a plurality of pixels PX. Two or more pixels PX may constitute a pixel group PXG. In this case, the pixel array may include a plurality of pixel groups PXG.

[0130] In some example embodiments, as an example, a single pixel group PXG may include four pixels PX. For example, a single pixel group PXG may include first to fourth pixels PX1, PX2, PX3, and PX4 arranged in a 2×2 matrix. The single pixel group PXG may be arranged in a matrix along a first direction D1 and a second direction D2 that intersect each other. In the accompanying drawings, a direction perpendicular to the first direction D1 and the second direction D2 may be a third direction D3. The row direction may be the first direction D1, and the column direction may be the second direction D2. The first pixel PX1 and the second pixel PX2 and the third pixel PX3 and the fourth pixel PX4 are arranged sequentially in the first direction D1. In this case, the first pixel PX1 and the second pixel PX2 constitute a first row, and the third pixel PX3 and the fourth pixel PX4 constitute a second row.

[0131] One of a plurality of reference colors may be assigned to each of the first to fourth pixels PX1, PX2, PX3, and PX4. The plurality of reference colors may include, for example, red-green-blue (RGB), red-green-blue-white (RGBW), cyan-magenta-yellow (CMY), cyan-magenta-yellow-black (CMYK), red-yellow-blue (RYB), and RGB infrared (RGBIR). In some example embodiments, the first to third colors may be, for example, blue (B), green (G), and red (R), respectively, but are not limited thereto.

[0132] The colors of the first to fourth pixels PX1, PX2, PX3, and PX4 may be implemented by a color filter CF corresponding to each pixel PX. When an array including a color filter CF corresponding to each pixel PX is referred to as a color filter array, the color filter array may include first to third color filters CF1, CF2, and CF3 corresponding to each pixel PX. According to some example embodiments, the first to third color filters CF1, CF2, and CF3 may represent blue, green, and red, respectively. Alternatively or additionally, the first pixel PX1 may correspond to the first color filter CF1, the second pixel PX2 may correspond to the second color filter CF2, the third pixel PX3 may correspond to the second color filter CF2, and the fourth pixel PX4 may correspond to the third color filter CF3. However, it should be noted that the arrangement of the color filters is not limited thereto, and does not limit the repeated array structure and pattern of other color filter arrays.

[0133] refer to Fig. 13B , each pixel group PXG may include first to fourth pixels PX1 , PX2 , PX3 , and PX4 arranged in a 2×2 matrix.

[0134] One of the plurality of reference colors may be assigned to each pixel group PXG, and each pixel group PXG may have one of the assigned reference colors. For example, green may be assigned to a single pixel group PXG. In this case, the first to fourth pixels PX1, PX2, PX3, and PX4 may all have a green color filter.

[0135] Each pixel group PXG may have a single color. When a plurality of pixel groups PXG are arranged, they may be formed as a Bayer pattern as a whole. For example, when four pixel groups PXG are arranged to have a 2×2 matrix shape, the two pixel groups PXG in the first row may have blue and green, respectively, and the two pixel groups PXG in the second row may have green and red, respectively.

[0136] However, it should be noted that the arrangement of the color filters is not limited thereto, and the repeated array structure and pattern of other color filter arrays are not limited thereto.

[0137] As described herein, a single pixel group PXG including first to fourth pixels PX1, PX2, PX3, and PX4 may be provided with a single microlens. For example, the first to fourth pixels PX1, PX2, PX3, and PX4 within a single pixel group PXG may share a single microlens ML.

[0138] As described herein, a single pixel group PXG may include first to fourth pixels PX1, PX2, PX3, and PX4 that are different from each other, and a photoelectric conversion signal of a photoconductive conversion element included in each pixel PX may be read independently. A phase difference may be detected based on an arrangement relationship between different photoelectric conversion elements included in each pixel PX to perform autofocus. Detection of a phase difference may be performed for each direction in which the photoelectric conversion elements within the first to fourth pixels PX1, PX2, PX3, and PX4 are arranged. In the present embodiment, the first to fourth pixels PX1, PX2, PX3, and PX4 are arranged in a first direction D1 and a second direction D2, so that a phase difference may be detected in both horizontal and vertical directions.

[0139] Although not described otherwise, in some example embodiments, the pixel array may include a plurality of pixel groups PXG, and each pixel group PXG may include first to ninth pixels arranged in a 3×3 matrix.

[0140] refer to Fig. 13C , each pixel group PXG may include first to fourth pixels PX1 , PX2 , PX3 , and PX4 arranged in a 2×2 matrix.

[0141] As described herein, each of the first to fourth pixels PX1, PX2, PX3, and PX4 may include a first sub-pixel SPX1 and a second sub-pixel SPX2. The first sub-pixel SPX1 and the second sub-pixel SPX2 may be sequentially arranged in the first direction D1.

[0142] One of the plurality of reference colors may be assigned to each of the first to fourth pixels PX1, PX2, PX3, and PX4. According to some example embodiments, the first to third color filters CF1, CF2, and CF3 may represent blue, green, and red, respectively. In addition, the first pixel PX1 may correspond to the first color filter CF1, the second pixel PX2 may correspond to the second color filter CF2, the third pixel PX3 may correspond to the second color filter CF2, and the fourth pixel PX4 may correspond to the third color filter CF3. However, it should be noted that the arrangement of the color filters is not limited thereto, and does not limit the repeated array structure and pattern of other color filter arrays.

[0143] refer to Fig.13D , the pixel array area PA may be provided with a plurality of pixel groups having the same shape, and the pixel groups may be arranged in different forms.

[0144] like Fig.13D As shown, the pixel groups may include a first pixel group PXG1 arranged in a 1×2 matrix and a second pixel group PXG2 arranged in a 2×2 matrix. As shown, some pixels included in the first pixel group PXG1 and the second pixel group PXG2 may be shared with each other.

[0145] One of the plurality of reference colors may be assigned to each of the pixel groups PXG1 and PXG2. For example, the first pixel PX1 and the second pixel PX2 in the first pixel group PXG1 may have one of the assigned reference colors. The first to fourth pixels PX1, PX2, PX3, and PX4 in the second pixel group may also have one of the assigned reference colors. For example, green may be assigned to a single first pixel group PXG1. In this case, the first pixel PX1 and the second pixel PX2 may each have a green color filter. Blue may be assigned to a single second pixel group PXG2. In this case, blue may be assigned to all of the first to fourth pixels PX1, PX2, PX3, and PX4. However, when a single pixel in the first pixel group PXG1 (e.g., the second pixel PX2) and an adjacent single pixel in the second pixel group PXG2 (e.g., the first pixel PX1) are shared with each other, the shared pixel may have the same color as the remaining pixels in the first pixel group PXG1 (e.g., the first pixel PX1).

[0146] As described herein, the first pixel PX1 and the second pixel PX2 in each first pixel group PXG1 may share a microlens ML, while the first to fourth pixels PX1 , PX2 , PX3 , and PX4 in each second pixel group PXG2 may not share a microlens ML and may each have a microlens ML.

[0147] As described above, the pixel array may include a pixel group including two pixels PX1 and PX2 sharing a microlens ML, and all pixels may be two pixels PX1 and PX2 sharing a microlens ML, or some pixels may be two pixels PX1 and PX2 sharing a microlens ML. In the above embodiment, in order to perform autofocus, a single pixel group may include a first pixel PX1 and a second pixel PX2 different from each other, and independently read a photoelectric conversion signal of a photoelectric conversion element PD included in each pixel PX. Autofocus may be performed by detecting a phase difference using an arrangement relationship between different photoelectric conversion elements PD included in each pixel PX.

[0148] refer to Fig.13E , the pixel array may include a plurality of pixel groups PXG. The plurality of pixel groups PXG may include a first pixel group PXG1 and a second pixel group PXG2. Each of the first pixel groups PXG1 may include first to fourth pixels PX1, PX2, PX3, and PX4 having different colors, and a microlens ML may be provided separately for each of the first to fourth pixels PX1, PX2, PX3, and PX4. Each of the second pixel groups PXG2 may include first to fourth pixels PX1, PX2, PX3, and PX4 having the same color, and a single microlens ML may be provided for the first to fourth pixels PX1, PX2, PX3, and PX4. Colors other than the first to third colors, such as white, may be assigned to the second pixel group PXG2.

[0149] The second pixel group PXG2 of the pixel array may be provided with white pixels PX, thereby significantly increasing the amount of light incident on the photoelectric conversion element PD to improve the sensitivity of the image sensor. Meanwhile, the first pixel group PXG1 may be provided to achieve not only image sensing but also auto focusing.

[0150] As described above, according to various example embodiments, a portion of the device isolation layer close to the light incident surface may be used as a transparent insulating material to significantly reduce optical loss. Alternatively or additionally, the semiconductor substrate corresponding to each pixel may be provided to have a convex shape, thereby improving the focusing efficiency of light traveling to the photoelectric conversion element. Alternatively or additionally, the upper surface of the conductive spacer layer included in the device isolation layer may be covered with a transparent insulating material to reduce pixel defects.

[0151] Therefore, the sensitivity of the image sensor can be improved and the photoelectric conversion efficiency can be improved. As a result, a high-quality image sensor can be provided.

[0152] Any of the elements and / or functional blocks disclosed above may include or be implemented in a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include an electrical component such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include an electrical component such as a logic gate, which includes at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0153] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

[0154] For example, in some example embodiments, an image sensor having a microlens is provided. However, the example embodiments may also be applied to an image sensor based on a super microlens (MML) having a nanostructure instead of a microlens. Alternatively or additionally, the example embodiments are not necessarily mutually exclusive of each other. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.

[0155] This application claims the priority of Korean Patent Application No. 10-2023-0136264 filed on October 12, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensor, comprising: A semiconductor substrate comprising a first surface, a second surface opposite to the first surface, and a plurality of pixels, wherein the semiconductor substrate has a first height; a device isolation layer in a trench that penetrates the first surface and the second surface of the semiconductor substrate and separates the pixels from each other; as well as a microlens provided on the second surface, in The device isolation layer comprises: a conductive spacer layer having a second height less than the first height; a cover spacer layer on the conductive spacer layer to cover the upper surface of the conductive spacer layer; and An insulating spacer extends in a direction from the first surface to the second surface, contacts the conductive separation layer, and has a height that is less than the first height and greater than or equal to the second height. 2 . The image sensor of claim 1 , wherein the cover spacer layer has a width greater than a width of the conductive spacer layer. 3 . The image sensor of claim 2 , wherein the insulating spacer has a height that is smaller than the first height and larger than the second height. 4 . The image sensor of claim 3 , wherein the insulating pad comprises a protrusion protruding from an upper surface of the conductive separation layer.

5. The image sensor according to claim 1, wherein Each of the pixels includes a photoelectric conversion element in the semiconductor substrate, and The upper surface of the semiconductor substrate of each pixel separated by the device isolation layer has a lens shape convex on one side, the lens shape being configured to refract a path of light incident on the upper surface of the semiconductor substrate so that the light travels to the photoelectric conversion element. 6 . The image sensor according to claim 5 , wherein the device isolation layer surrounds each pixel, and the upper surface of the semiconductor substrate of each pixel separated by the device isolation layer has an upwardly convex shape. 7 . The image sensor according to claim 5 , wherein the cover spacer layer has a stepped shape having a width increasing in a direction toward the second surface when viewed in a cross section. 8 . The image sensor according to claim 5 , wherein the cover spacer layer includes an inclined portion having a width that increases in a direction toward the second surface when viewed in a cross section.

9. The image sensor according to claim 1, wherein Each pixel includes a photoelectric conversion element in the semiconductor substrate, and The photoelectric conversion element includes impurities of a first conductivity type.

10. The image sensor according to claim 9, wherein The semiconductor substrate includes an impurity-doped region from the second surface to a first depth, and the impurity-doped region includes impurities of a second conductivity type opposite to the first conductivity type. 11 . The image sensor according to claim 10 , wherein the impurity doped region has a depth greater than a depth of the capping spacer layer. 12 . The image sensor according to claim 1 , wherein the device isolation layer comprises polysilicon containing impurities.

13. The image sensor of claim 12, wherein the conductive spacer layer is configured to receive a negative bias. 14 . The image sensor of claim 1 , wherein the cap spacer layer has a refractive index different from a refractive index of the semiconductor substrate.

15. The image sensor of claim 14, wherein the cover spacer layer comprises a transparent material. 16 . The image sensor according to claim 15 , wherein the cover spacer layer comprises an organic insulating layer or an inorganic insulating layer or both an organic insulating layer and an inorganic insulating layer.

17. The image sensor of claim 16, wherein the cover spacer layer comprises at least one of silicon oxide, hafnium oxide, silicon nitride, silicon carbon nitride, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, erbium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, aluminum nitride, hafnium nitride, or aluminum oxynitride.

18. An image sensor, comprising: A semiconductor substrate comprising a plurality of pixels, a first surface and a second surface opposite to the first surface; a device isolation layer in a trench that penetrates the first surface and the second surface of the semiconductor substrate and separates the pixels from each other; as well as a microlens provided on the second surface, in Each pixel includes a photoelectric conversion element in the semiconductor substrate, and The upper surface of the semiconductor substrate of each pixel separated by the device isolation layer has a lens shape convex on one side, the lens shape being configured to refract a path of light incident on the upper surface of the semiconductor substrate so that the light travels to the photoelectric conversion element.

19. The image sensor according to claim 18, wherein The device isolation layer comprises: a conductive spacer layer in a portion of the trench; a cover separation layer, on the conductive separation layer to cover the upper surface of the conductive separation layer; as well as An insulating liner is between the conductive separation layer and the semiconductor substrate and includes a protrusion protruding from an upper surface of the conductive separation layer.

20. An image sensor, comprising: A semiconductor substrate including a plurality of pixels, each pixel having a photoelectric conversion element, the semiconductor substrate including a first surface and a second surface opposite to the first surface; a device isolation layer in a trench that penetrates the first surface and the second surface of the semiconductor substrate and separates the pixels from each other; as well as microlenses on the second surface, in The groove defines a first groove having a first width and a second groove having a second width greater than the first width, The device isolation layer comprises: a conductive spacer layer within said first trench; a cap spacer layer on the conductive spacer layer to cover an upper surface of the conductive spacer layer and within the second groove; and an insulating liner extending in a direction from the first surface to the second surface and between the semiconductor substrate and the conductive spacer layer, wherein The upper surface of the semiconductor substrate of each pixel separated by the device isolation layer has a lens shape convex on one side, the lens shape being configured to refract a path of light incident on the upper surface of the semiconductor substrate so that the light travels to the photoelectric conversion element.

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