Micro-LED device self-alignment groove filling and passivation method

Abstract

The invention discloses a Micro-LED (Light Emitting Diode) device self-alignment groove filling and passivating method, which comprises the following steps that a Micro-LED device is provided, and the Micro-LED device comprises array units and grooves between the array units; preparing a dielectric layer on the Micro-LED device, wherein the dielectric layer fills the groove and covers all the array units; curing the dielectric layer; and thinning the whole surface of the dielectric layer by using a mask-free dry etching back etching method until the upper surfaces of all the array units are exposed, and forming a patterned passivation layer at the groove. The whole surface of the dielectric layer is thinned by using a mask-free dry etching back etching method, mask preparation and photoetching are not needed, the height of the dielectric layer can be accurately regulated and controlled through an etching process, and the process is simple; meanwhile, due to the fact that the register step and the developing solution corrosion step are avoided, the technological method can eliminate the problems of interface gaps and table top residues caused by register errors, the graphical passivation layer which is tightly connected can be formed without being restrained by the shape and the size, the etching resistance of the passivation structure is improved, and the device manufacturing yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a method for self-aligning slot filling and passivation of a Micro-LED device. Background Art

[0002] In the semiconductor device manufacturing process, especially after the development of miniaturized Micro-LED, the array units inside the chip are getting smaller and smaller, and have gradually developed in the direction of high density and small pitch. In this preparation process, due to the short circuit problem easily caused by small pitch, it is often necessary to form a passivation layer in the grooves between the Micro-LED array units to play the role of insulation isolation, groove filling and sidewall passivation.

[0003] To achieve this goal, in conventional semiconductor technology, a photoresist coating containing a photoinitiator is usually formed on the target array, and then the unnecessary part of the photoresist is removed by exposure and development, thereby forming a target passivation layer covering the side walls of each array unit. Conventional pattern transfer / groove filling method: usually requires a photolithography process, either direct photolithography of photosensitive polymers, or dielectric etching with mask lithography. The photolithography process generally includes dielectric spin coating, pre-baking, plate exposure, post-baking (negative photoresist), development, hardening, and other steps.

[0004] However, with the complexity of device structures, the size of these tiny units continues to decrease. To achieve smaller-sized graphic transfer and control high-precision unit spacing, high-precision lithography machines and strict process control methods are required. The equipment is expensive and the process control is difficult. Especially for high-aspect ratio trench filling passivation, poor surface flatness will lead to different focusing depths at different heights during lithography, resulting in different exposure levels, which will cause different shapes of photoresists after exposure, resulting in key dimension deviations and shape distortions after etching, resulting in low device manufacturing yield. Summary of the invention

[0005] In view of the above problems, an embodiment of the present invention provides a method for self-aligned slot filling and passivation of a Micro-LED device, which is used to improve the problems existing in preparing a patterned passivation layer by a conventional exposure process.

[0006] In order to achieve the above object, the present invention provides the following technical solutions: The present invention provides a method for self-aligning slot filling and passivation of a Micro-LED device, comprising the following steps: Step S1, providing a Micro-LED device, wherein the Micro-LED device includes array units and grooves between the array units; Step S2, preparing a dielectric layer on the Micro-LED device, wherein the dielectric layer fills the grooves and covers all array units; Step S3, curing the dielectric layer; Step S4, using a maskless dry etching back method to thin the entire surface of the dielectric layer until the upper surfaces of all array units are exposed, and a patterned passivation layer is formed at the grooves.

[0007] Optionally, the array unit is a semiconductor light emitting unit, a chip to be bonded unit, a substrate to be bonded unit, or a unit after the chip and substrate are bonded.

[0008] Optionally, the semiconductor light-emitting unit only includes a semiconductor epitaxial light-emitting layer; the chip unit to be bonded includes, from bottom to top, a semiconductor epitaxial light-emitting layer, an electrode layer and a chip bonding metal layer; the substrate unit to be bonded includes, from bottom to top, a CMOS circuit and a substrate bonding metal layer; after the chip is bonded to the substrate, the unit includes, from bottom to top, a CMOS circuit, a substrate bonding metal layer, a chip bonding metal layer and a semiconductor epitaxial light-emitting layer.

[0009] Optionally, the method for preparing the dielectric layer is to spin-coat the dielectric material on the entire surface of the Micro-LED device; the dielectric material is a photosensitive electrically insulating dielectric material or a non-photosensitive electrically insulating dielectric material that can be spin-coated and cured, and the dielectric material is cured by thermal curing or photocuring; the upper surface of the dielectric layer is flat.

[0010] Optionally, the photosensitive electrical insulating dielectric material or the non-photosensitive electrical insulating dielectric material that can be spin-coated and cured can be photoresist, spin-on glass, PDMS, or PMMA.

[0011] Optionally, the longitudinal height of the array unit is H0, the thickness of the dielectric layer prepared in step S2 is H1, 200nm≤H1-H0≤2000nm; the thickness of the patterned passivation layer in step S4 is H2, H0 / 2≤H2≤H0.

[0012] Optionally, in step S4, the etching rate of the dielectric layer by the etching gas used in the maskless dry etching back method is much greater than the etching rate of the array unit.

[0013] Optionally, the etching gas is one or more combinations of O2, CF4, CHF3, C4F8, and SF6.

[0014] Optionally, the method further includes cleaning the surface of the Micro-LED device after step S4 is completed, wherein the cleaning method is dry cleaning and / or wet cleaning.

[0015] Optionally, the expanded application areas of the maskless dry etching back method include local planarization, sidewall passivation and CMOS substrate protection in addition to the known trench filling.

[0016] Compared with the prior art, the method for self-aligned slot filling and passivation of Micro-LED devices provided by the present invention has the following advantages: (1) The maskless dry etching back etching method can achieve the thinning of the entire dielectric layer without the need for mask preparation and photolithography. The height of the dielectric layer can be precisely controlled through the etching process, and the process is simple. At the same time, since the plate alignment step and developer corrosion step are avoided, this process method can eliminate the interface gap and table residue problems caused by plate alignment errors, and can form a densely bonded patterned passivation layer at each stage of Micro-LED device manufacturing without being constrained by shape and size, thereby increasing the etching resistance of the passivation structure and improving the device manufacturing yield.

[0017] (2) A flat dielectric layer is formed by spin coating, and stable cross-linking of the dielectric layer can be achieved by thermal curing or photocuring, and the dielectric layer to be etched is simple to prepare; compared with the exposure method that can only use photosensitive dielectric liquids, the dielectric material in this application can be any dielectric material that can be spin-coated and cured, without distinguishing between photosensitive and non-photosensitive types, which increases the diversity of material selection.

[0018] (3) The slot filling method of thinning the entire surface of the dielectric layer can improve the surface flatness of the high aspect ratio steps and reduce the distortion of the lithography pattern caused by the flatness problem. In addition, the passivation is not affected by the uniformity and missing of the array units, and the missing parts are covered by the insulating dielectric layer, which can avoid the occurrence of short circuits to a certain extent.

[0019] In addition to the technical problems solved by the embodiments of the present invention described above, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions, other technical problems that can be solved by the method for self-aligned groove filling and passivation of Micro-LED devices provided by the embodiments of the present invention, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 Schematic diagram of the planar structure of the target Micro-LED device array in an embodiment of the present invention.

[0022] Figure 2 Schematic cross-sectional view of the target Micro-LED device array in an embodiment of the present invention.

[0023] Figure 3 Schematic diagram of the cross section of the dielectric layer prepared in the embodiment of the present invention.

[0024] Figure 4 It is a schematic diagram of performing back etching on the dielectric layer to reduce the thickness of the dielectric layer in an embodiment of the present invention.

[0025] Figure 5 It is a cross-sectional schematic diagram after the dielectric layer is thinned by the back etching method in an embodiment of the present invention.

[0026] Figure 6 This is a scanning electron microscope morphology image of the patterned passivation layer of the 2.5um size Micro-LED array unit prepared in Example 2 of the present invention.

[0027] In the figure: 1-substrate; 2-buffer layer; 3-array unit; 4-groove; 5-dielectric layer; 6-passivation layer.

[0028] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] It should be noted that the words expressing position and direction described in the present invention are all described with reference to the accompanying drawings as examples, but can also be changed as needed, and all such changes are included in the protection scope of the present invention. The terms "upper surface", "top view", "up", "above", "from bottom to top" and similar expressions used herein are for illustrative purposes only.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0032] In order to solve the problem that when the photoresist exposure process is used in the prior art to passivate the Micro-LED array during the semiconductor chip manufacturing process, a gap is easily generated at the interface between the photoresist and the array to be passivated due to the plate error and the corrosion of the developer, and there is a residual table surface, the present invention provides a method for self-aligned slot filling and passivation of Micro-LED devices, which mainly prepares a dielectric layer to cover the target array, and uses a dry etching back method to thin the dielectric layer on the entire surface to expose the surface of the array unit, thereby forming a graphic target passivation layer. This method is not limited by the shape and size of the Micro-LED array unit, can achieve self-aligned graphic transfer, and effectively improves the lack of precision and interface gap problems in preparing small-size graphic passivation layers by exposure method. In addition to the known groove filling, the application field of this process method also involves local flattening, sidewall passivation, and CMOS substrate protection.

[0033] See also Figure 1-5 The present embodiment provides a method for self-aligned slot filling and passivation of a Micro-LED device, comprising the following steps: Step S1 , providing a Micro-LED device, wherein the Micro-LED device comprises array units 3 and grooves 4 between the array units.

[0034] In some embodiments of the present application, the array unit 3 may be a semiconductor light emitting unit, a chip unit to be bonded, a substrate unit to be bonded, or a unit after the chip and substrate are bonded.

[0035] In some embodiments of the present application, the semiconductor light-emitting unit only includes a semiconductor epitaxial light-emitting layer; the chip unit to be bonded includes, from bottom to top, a semiconductor epitaxial light-emitting layer, an electrode layer and a chip bonding metal layer; the substrate unit to be bonded includes, from bottom to top, a CMOS circuit and a substrate bonding metal layer; after the chip is bonded to the substrate, the unit includes, from bottom to top, a CMOS circuit, a substrate bonding metal layer, a chip bonding metal layer and a semiconductor epitaxial light-emitting layer.

[0036] Step S2 , preparing a dielectric layer 5 on the Micro-LED device, wherein the dielectric layer 5 fills the grooves 4 and covers all array units 3 .

[0037] In some embodiments of the present application, the method for preparing the dielectric layer 5 is to spin-coat the dielectric material on the entire surface of the Micro-LED device; the dielectric material is a photosensitive electrically insulating dielectric material or a non-photosensitive electrically insulating dielectric material that can be spin-coated and cured, and the curing method of the dielectric material is thermal curing or photocuring; the upper surface of the dielectric layer is flat.

[0038] It should be noted that thermal curing refers to the polymerization and cross-linking reaction that occurs under temperature induction, and the thermal curing temperature is the cross-linking temperature of the medium or solvent; photocuring refers to the curing process of monomers, oligomers or polymer matrices under light induction, which is generally used in the film-forming process, and the most commonly used is ultraviolet (UV) curing.

[0039] In some embodiments of the present application, the spin-coated and curable photosensitive electrical insulating dielectric material or non-photosensitive electrical insulating dielectric material may be photoresist, spin-coated glass, PDMS, PMMA. The photoresist may be SU-8 negative photoresist, PSPI, BCB, etc.

[0040] In some embodiments of the present application, the longitudinal height of the array unit 3 is H0, the thickness of the dielectric layer 5 is H1, and 200nm≤H1-H0≤2000nm.

[0041] Step S3, curing the dielectric layer 5.

[0042] Step S4 , using a maskless dry etching back method to thin the entire surface of the dielectric layer 5 until the upper surfaces of all array units 3 are exposed, and forming a patterned passivation layer 6 at the grooves 4 .

[0043] In some embodiments of the present application, the etching rate of the etching gas used in the maskless dry etching back method for the dielectric layer 5 is much higher than that for the array unit 3. Specifically, the etching rate of the etching gas for the dielectric material is much higher than that for the semiconductor material and the metal material.

[0044] In some embodiments of the present application, the etching gas is one or more combinations of O2, CF4, CHF3, C4F8, and SF6.

[0045] It should be noted that the dry etching equipment may be one or more of an ICP etcher, a RIE etcher, an IBE etcher and the like.

[0046] In some embodiments of the present application, the thickness of the patterned passivation layer 6 is H2, and H0 / 2≤H2≤H0.

[0047] In some embodiments of the present application, the surface of the Micro-LED device is cleaned after step S4 is completed, and the cleaning method is dry cleaning and / or wet cleaning. The purpose of cleaning is to remove surface contamination or etching byproducts and clean the surface.

[0048] In some embodiments of the present application, the expanded application fields of the maskless dry etching back method include local planarization, sidewall passivation, and CMOS substrate protection in addition to the known trench filling. Example 1

[0049] In this embodiment, the method for self-aligning slot filling and passivation of a Micro-LED device includes the following steps: Step S1, providing a target Micro-LED device array to be passivated, the plan view and cross-sectional view of which are as follows: Figure 1 and Figure 2 shown.

[0050] Specifically, the part to be passivated of the target Mciro-LED device array is a regularly arranged array unit 3, which is formed on a substrate 1 and a buffer layer 2. The buffer layer 2 is used to buffer the stress between the substrate 1 and the array unit 3, and each array unit 3 is electrically independent of each other. The array unit 3 is a chip unit to be bonded, which includes a semiconductor epitaxial light-emitting layer, an electrode layer, and a chip bonding metal layer from bottom to top. There are isolation grooves 4 between the array units 3, and the longitudinal height H0 of the array unit 3 is 1.5um.

[0051] Step S2, preparing a dielectric layer 5, the dielectric layer 5 fills the groove 4 and covers all array units 3, such as Figure 3 shown.

[0052] Specifically, a thick dielectric material is spin-coated on the target Micro-LED device array. During the spin-coating process, a specific rotation speed and spin-coating time need to be set to control the thickness of the film layer so that the thickness of the flat dielectric layer 5 after curing is greater than the longitudinal height of the array unit 3. The formed dielectric layer 5 is a flat surface that completely covers the array unit 3.

[0053] In this embodiment, the dielectric material is SU-8 negative photoresist, and the thickness H1 of the dielectric layer 5 is 2 um.

[0054] Step S3, curing the dielectric layer 5.

[0055] Specifically, the curing form of the dielectric layer 5 is thermal curing, and the curing conditions are hard baking on a hot plate at 230° C. for 30 minutes. The cured dielectric layer 5 has a certain mechanical strength and good chemical stability to prevent the target passivation layer from deformation, denaturation and other problems in the key steps of the chip manufacturing process.

[0056] Step S4 , thinning the dielectric layer 5 entirely by maskless dry etching until the upper surface of each array unit 3 is exposed, and forming a patterned passivation layer 6 at the groove 4 .

[0057] The maskless dry etching back method is as follows Figure 4 As shown, the etching equipment is an ICP etcher, and the etching gas is a combination of O2 and CF4. After etching, the upper surface of the array unit 3 is completely exposed, and no dielectric layer remains on the surface of the array unit 3. Figure 5 As shown, the thickness H2 of the patterned passivation layer 6 produced after etching is 1.3 um.

[0058] Step S5, cleaning the etched surface. In this embodiment, the etching byproduct is a fluorocarbon polymer, which is cleaned with a mixed solution of ammonia and hydrogen peroxide for 5 minutes.

[0059] In this embodiment, the patterned passivation layer 6 on the chip unit to be bonded manufactured by steps S1-S5 forms a seamless and tight connection at the interface between the array unit 3 and the dielectric layer 5, which protects the side wall of the semiconductor epitaxial light-emitting layer on the one hand, and isolates the metal electrode layer and the chip bonding metal layer on the other hand, thereby reducing the Micro-LED leakage channel and improving the yield of the Micro-LED device. Example 2

[0060] In this embodiment, the array unit 3 to be passivated of the Micro-LED device provided in step S1 is a unit after the chip and the substrate are bonded, and the unit structure includes a CMOS circuit, a substrate bonding metal layer, a chip bonding metal layer and a semiconductor epitaxial light-emitting layer from bottom to top. There are isolation grooves 4 between the array units 3, and the size of the array unit 3 is 2.5um×2.5um, and the vertical height H0 is 5um. The isolation grooves 4 between the array units 3 form deep groove steps with a high aspect ratio.

[0061] Step S2, preparing a dielectric layer 5, the dielectric layer 5 fills the groove 4 and covers all array units 3, such as Figure 3 shown.

[0062] Specifically, a thick dielectric material is spin-coated on the target Micro-LED device array so that the thickness of the flat dielectric layer 5 after curing is greater than the longitudinal height of the array unit 3, and the formed dielectric layer 5 is a flat surface that completely covers the array unit 3. In particular, for deep grooves with a depth H0 ≥ 5um, if the thickness of the dielectric layer cannot cover the array unit 3 after one spin coating, a method of multiple spin coatings can be used.

[0063] In this embodiment, the dielectric material is spin-on glass SOG, and thermal curing is used to form the dielectric layer 5, and the thickness H1 of the dielectric layer 5 is 5.5 um. Specifically, the curing conditions are hot plate 150° C.*5 min+180° C.*1 h.

[0064] Step S4, the dielectric layer 5 is thinned by a maskless dry etching back method until the upper surface of each array unit 3 is exposed, and a patterned passivation layer 6 is formed at the groove 4. Specifically, the etching equipment uses an ICP etcher, and the etching gas uses a combination of CF4 and CHF3. The thickness H2 of the patterned passivation layer 6 formed on the surface of the exposed array unit 3 after etching is 4.8um.

[0065] Step S5, using a mixed solution of ammonia water and hydrogen peroxide to clean the etched surface.

[0066] In this embodiment, the patterned passivation layer 6 on the unit after the manufactured chip is bonded to the substrate effectively protects the CMOS circuit, the substrate bonding metal layer, the chip bonding metal layer and the semiconductor epitaxial light-emitting layer, and at the same time significantly reduces the aspect ratio of the groove, has a local flattening effect, and is beneficial to metal wiring and electrode lithography. In particular, when there is a defect in the array unit, the self-aligned slot filling and passivation method provided by the present invention is not affected by the defect, such as Figure 6 As shown, the missing area of ​​the array unit is also covered by the insulating dielectric layer, which also avoids the occurrence of short circuit to a certain extent.

[0067] In summary, the method for self-aligned slot filling and passivation of the Micro-LED device in the present invention forms a flat dielectric layer covering the Micro-LED array unit by spin-coating a dielectric layer colloid on the Micro-LED device, and controls the thickness of the dielectric layer by back-etching to expose the upper surface of the array unit, which can realize mask-free, shape- and size-free graphic transfer, while avoiding the photolithography alignment and developer corrosion steps, which can greatly reduce the precision error and form a close-knit dielectric filling, with a simple process and easy implementation. Therefore, the present invention solves the deviation problem and interface gap problem existing in small-size, high-precision photolithography in existing graphic transfer technology, and provides a technical reference for application fields such as local flattening of chip surface, sidewall passivation, and CMOS substrate protection in the manufacturing process of Micro-LED devices.

[0068] In the description of this specification, the description of "some embodiments" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0069] The above embodiments are only used to illustrate the design ideas and features of the method of the present invention, and their purpose is to enable those skilled in the art to understand the content of the method of the present invention and implement it accordingly. The protection scope of the method of the present invention is not limited to the above embodiments. Therefore, any equivalent changes or modifications made based on the principles and design ideas disclosed by the present invention are within the protection scope of the present invention.

Claims

1. A method for self-aligned slot filling and passivation of a Micro-LED device, characterized in that: The following steps are involved: Step S1, providing a Micro-LED device, wherein the Micro-LED device comprises array units and grooves between the array units; Step S2, preparing a dielectric layer on the Micro-LED device, wherein the dielectric layer fills the grooves and covers all array units; Step S3, curing the dielectric layer; Step S4, using a maskless dry etching back method to thin the entire surface of the dielectric layer until the upper surfaces of all array units are exposed, and a patterned passivation layer is formed at the grooves.

2. The method for self-aligned slot filling and passivation of a Micro-LED device according to claim 1, characterized in that: The array unit is a semiconductor light emitting unit, a chip unit to be bonded, a substrate unit to be bonded, or a unit after the chip and substrate are bonded.

3. The method for self-aligned slot filling and passivation of a Micro-LED device according to claim 2, characterized in that: The semiconductor light-emitting unit only includes a semiconductor epitaxial light-emitting layer; the chip unit to be bonded includes, from bottom to top, a semiconductor epitaxial light-emitting layer, an electrode layer and a chip bonding metal layer; the substrate unit to be bonded includes, from bottom to top, a CMOS circuit and a substrate bonding metal layer; after the chip is bonded to the substrate, the unit includes, from bottom to top, a CMOS circuit, a substrate bonding metal layer, a chip bonding metal layer and a semiconductor epitaxial light-emitting layer.

4. The method for self-aligned slot filling and passivation of a Micro-LED device according to claim 1, characterized in that: The method for preparing the dielectric layer is to spin-coat the dielectric material on the entire surface of the Micro-LED device; the dielectric material is a photosensitive electrical insulating dielectric material or a non-photosensitive electrical insulating dielectric material that can be spin-coated and cured, and the dielectric material is cured by thermal curing or photocuring; the upper surface of the dielectric layer is flat.

5. The method for self-aligned slot filling and passivation of a Micro-LED device according to claim 4, characterized in that: The photosensitive electrical insulating dielectric material or non-photosensitive electrical insulating dielectric material that can be spin-coated and cured is photoresist, spin-coated glass, PDMS, or PMMA.

6. The method for self-aligned slot filling and passivation of a Micro-LED device according to claim 1, characterized in that: The longitudinal height of the array unit is H0, the thickness of the dielectric layer prepared in step S2 is H1, 200nm≤H1-H0≤2000nm; the thickness of the patterned passivation layer in step S4 is H2, H0 / 2≤H2≤H0.

7. The method for self-aligned slot filling and passivation of a Micro-LED device according to claim 1, characterized in that: In step S4, the etching rate of the dielectric layer by the etching gas used in the maskless dry etching back method is much greater than the etching rate of the array unit.

8. The method for self-aligned slot filling and passivation of a Micro-LED device according to claim 7, characterized in that: The etching gas is one or more combinations of O2, CF4, CHF3, C4F8, and SF6.

9. The method for self-aligned slot filling and passivation of a Micro-LED device according to claim 1, characterized in that: The method also includes cleaning the surface of the Micro-LED device after step S4 is completed, wherein the cleaning method is dry cleaning and / or wet cleaning.

10. The method for self-aligned slot filling and passivation of a Micro-LED device according to claim 6, characterized in that: The application fields of the maskless dry etching back method also include local planarization, sidewall passivation and CMOS substrate protection.

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