Semiconductor package

Abstract

A semiconductor package according to an embodiment includes: a substrate; a protective layer disposed on the substrate; a first adhesive member provided on the protective layer and having an open loop shape in a peripheral direction of an upper surface of the protective layer; and a cover member disposed on the first adhesive member, in which a lower surface of the cover member includes: a first lower surface in contact with the first adhesive member, and a second lower surface not in contact with the first adhesive member, and the protective layer includes a first opening, the first opening vertically overlaps the second lower surface of the cover member and does not vertically overlap the first adhesive member.

Description

Technical Field

[0001] Embodiments relate to semiconductor packaging. Background Art

[0002] As the performance of electrical / electronic products increases, technologies for attaching a large number of packages to a substrate of limited size are being proposed and studied. However, since typical packages are based on mounting a single semiconductor chip, there are limitations in obtaining the desired performance.

[0003] A typical package substrate has a form in which a processor package in which a processor chip is disposed and a memory package in which a memory chip is disposed are connected as one body. The package substrate is manufactured by combining the processor chip and the memory chip into a single integrated package, thereby reducing the mounting area of ​​the chip and enabling high-speed signal transmission through a short path.

[0004] Due to these advantages, package substrates are widely used in mobile devices and the like.

[0005] At the same time, the area of ​​packages continues to expand due to the high specifications of electronic devices such as mobile devices and the adoption of HBM (High Bandwidth Memory).

[0006] In addition, as the area of ​​the semiconductor package increases, there is a problem that the semiconductor package is more warped. In addition, as the area of ​​the semiconductor package increases, heat generation becomes more serious, and therefore, there is a problem that the heat dissipation characteristics must be further improved.

[0007] Therefore, conventional semiconductor packages employ a cover member (or cover) to improve bending characteristics and heat dissipation characteristics. The cover member includes a metal material having excellent thermal conductivity.

[0008] The cover member is attached to the adhesive member applied to the package substrate. At this time, the adhesive member in the conventional semiconductor package is applied to the peripheral area of ​​the upper surface of the package substrate in a closed loop shape. In addition, when the adhesive member is applied to the substrate in a closed loop shape, a physical reliability problem occurs, that is, the gas is not discharged during the heat treatment performed after the cover member is attached, or the gas expands due to the heat generated during the operation of the product, and the semiconductor device mounted on the semiconductor package is separated from the package substrate, or the cover member is separated from the package substrate.

[0009] Meanwhile, in order to solve the above-mentioned problem, the adhesive member is not applied to some areas of the peripheral area of ​​the upper surface of the package substrate. That is, according to the prior art, the adhesive member is applied to the package substrate in an open loop shape. In addition, some areas where the adhesive member is not applied are used as exhaust holes for exhausting gas.

[0010] However, when the width of some areas on the package substrate to which the adhesive member is not applied increases, there is a problem that the adhesive force between the package substrate and the cover member is deteriorated due to the adhesive member.

[0011] In addition, when the width of some regions on the package substrate to which the adhesive member is not applied is reduced, the area of ​​the exhaust hole may not be sufficiently ensured, and thus, a physical reliability problem may occur because the gas is not easily exhausted.

[0012] (Patent Document 1) KR 10-2017-0107596 A Summary of the invention

[0013] Technical issues

[0014] The embodiment provides a semiconductor package having a novel structure.

[0015] In addition, embodiments provide a semiconductor package having improved heat dissipation characteristics.

[0016] In addition, the embodiment provides a semiconductor package having improved adhesion between a package substrate and a cover member.

[0017] In addition, the embodiment provides a semiconductor package having improved gas exhaust characteristics in a heat treatment after a bonding member applying process.

[0018] In addition, the embodiment provides a semiconductor package capable of increasing the area of ​​a vent hole while increasing the application area of ​​an adhesive member.

[0019] In addition, the embodiment provides a semiconductor package that can be thinned and miniaturized.

[0020] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood from the following description by those skilled in the art to which the proposed embodiments belong.

[0021] Technical Solution

[0022] According to an embodiment, a semiconductor package includes: a substrate; a protective layer arranged on the substrate; a first adhesive member arranged on the protective layer and having an open loop shape along the peripheral direction of the upper surface of the protective layer; and a cover member arranged on the first adhesive member, wherein the lower surface of the cover member includes: a first lower surface in contact with the first adhesive member, and a second lower surface not in contact with the first adhesive member, and the protective layer includes a first opening, the first opening vertically overlaps with the second lower surface of the cover member and does not vertically overlap with the first adhesive member.

[0023] In addition, at least a portion of the second lower surface of the cover member does not vertically overlap the first opening.

[0024] In addition, the upper surface of the protective layer includes a peripheral region adjacent to a periphery of the upper surface of the protective layer, and the first adhesive member is partially disposed in the peripheral region along a peripheral direction.

[0025] In addition, the first opening vertically overlaps an area in the peripheral region where the first adhesive member is not disposed.

[0026] In addition, the width of the region where the first adhesive member is not provided in the peripheral direction is greater than the width of the first opening in the peripheral direction.

[0027] In addition, a plurality of first openings are disposed spaced apart from each other in a peripheral direction, and the first adhesive member includes a plurality of first adhesive patterns disposed between the plurality of first openings in the peripheral direction.

[0028] In addition, the first opening is connected to the outer side surface of the protection layer.

[0029] In addition, the protective layer includes a groove that is recessed from the upper surface of the protective layer toward the lower surface of the protective layer and vertically overlaps with the first adhesive member, and the first adhesive member is disposed in the groove.

[0030] In addition, the groove is spaced apart from the outer side surface of the protection layer and connected to the first opening.

[0031] In addition, the substrate includes an insulating layer and a first electrode layer disposed on the insulating layer, and the protective layer includes a second opening that passes through an upper surface and a lower surface of the protective layer and vertically overlaps with the first electrode layer.

[0032] In addition, the first opening does not vertically overlap with the first electrode layer.

[0033] In addition, the semiconductor package further includes a first connection portion disposed on the first electrode layer vertically overlapping the second opening, and a semiconductor device disposed on the first connection portion.

[0034] Furthermore, the cover member includes a side plate portion spaced apart from the semiconductor device and covering a side region of the semiconductor device, and an upper plate portion extending from the side plate portion and covering an upper region of the semiconductor device, and a lower surface of the cover member is a lower surface of the side plate portion.

[0035] In addition, the semiconductor package further includes a second adhesive member disposed between the upper surface of the semiconductor device and the lower surface of the upper plate portion.

[0036] In addition, the semiconductor package further includes a third adhesive member disposed on the upper surface of the upper plate portion, and a heat sink disposed on the third adhesive member.

[0037] In addition, the semiconductor package further includes a molding member which is disposed on the substrate and molds the first connection portion and a side surface of the semiconductor device.

[0038] Furthermore, the protective layer includes a solder resist.

[0039] Beneficial Effects

[0040] The semiconductor package of the embodiment includes a substrate and a protective layer disposed on the substrate. In addition, the protective layer includes a first opening disposed in a peripheral area of ​​an upper surface of the protective layer and passing through the upper surface and the lower surface of the protective layer. In addition, the semiconductor package includes a first adhesive member disposed in a peripheral area of ​​an upper surface of the protective layer and a cover member disposed on the first adhesive member.

[0041] At this time, the first adhesive member may be partially disposed in the peripheral region of the protective layer. Specifically, the first adhesive member may have an open loop shape along the peripheral direction of the upper surface of the protective layer.

[0042] Therefore, the peripheral area includes a disposition area where the first adhesive member is disposed and a non-disposition area where the first adhesive member is not disposed, and at this time, the non-disposition area vertically overlaps with the first opening.

[0043] In other words, the lower surface of the cover member includes a first lower surface in contact with the first adhesive member and a second lower surface not in contact with the first adhesive member. In addition, the first opening vertically overlaps with the second lower surface of the cover member but does not vertically overlap with the first adhesive member.

[0044] Therefore, the embodiment can not only utilize the non-setting area of ​​the first adhesive member, but also utilize the first opening of the protective layer connected to the non-setting area as a vent. Therefore, the embodiment can easily discharge the gas existing in the cavity space defined by the internal space of the cover member to the outside. Therefore, the embodiment can solve the physical reliability problem and the electrical reliability problem caused by the presence of gas in the cavity space. Therefore, the embodiment can further improve the product reliability of the semiconductor package.

[0045] At the same time, the protective layer of the embodiment includes a groove, which is arranged in the area where the first bonding member is to be arranged and is connected to the first opening. In addition, the first bonding member can be arranged in the groove. In this way, the embodiment can reduce the height of the semiconductor package by the depth of the groove. Therefore, the embodiment can miniaturize the semiconductor package.

[0046] In addition, the embodiment allows the width of the non-setting area of ​​the first bonding member to be greater than the width of the first opening. At this time, the width of the first opening and the width of the non-setting area each represent the width in the peripheral direction of the upper surface of the protective layer. Therefore, the embodiment can prevent the first bonding member from overflowing into the first opening. Therefore, the embodiment can further improve the product reliability of the semiconductor package. In addition, the embodiment is provided with a step between the non-setting area and the first opening, so that the gas generated in the cavity space can flow in the direction of the first opening. Therefore, the embodiment can further improve the exhaust characteristics of the gas. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0048] Figure 2 is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0049] Figure 3 is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0050] Figure 4 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0051] Figure 5 is a plan view showing the first protective layer of the first embodiment.

[0052] Figure 6 is a plan view showing a first protective layer of the second embodiment.

[0053] Figure 7 is a plan view showing a first protective layer of the third embodiment.

[0054] Figure 8 is a plan view showing a first protective layer of a fourth embodiment.

[0055] Fig. 9 is a diagram showing a state in which a first bonding member is provided on a first protective layer of the first embodiment.

[0056] FIG. 10 is a diagram showing a state in which a first bonding member is provided on a first protective layer of a second embodiment.

[0057] FIG. 11 is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0058] FIG. 12 is a plan view showing a first protective layer of the semiconductor package of FIG. 11 .

[0059] FIG. 13 is a diagram illustrating a state in which a first adhesive member is provided on the first protective layer of FIG. 12 .

[0060] Figure 14 to Fig.23 are cross-sectional views explaining a method of manufacturing a semiconductor package according to an embodiment in order of processes. DETAILED DESCRIPTION

[0061] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0062] However, the spirit and scope of the present invention are not limited to a part of the described embodiments, but may be implemented in various other forms, and one or more elements of the embodiments may be selectively combined and rearranged within the spirit and scope of the present invention.

[0063] In addition, unless otherwise clearly defined and described, the terms (including technical terms and scientific terms) used in the embodiments of the present invention may be interpreted as the same meaning as that generally understood by ordinary technicians in the field to which the invention belongs, and those terms such as those defined in commonly used dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant field. In addition, the terms used in the embodiments of the present invention are used to describe the embodiments and are not intended to limit the present invention.

[0064] In the present specification, a singular form may also include a plural form, and unless otherwise specifically stated in a phrase, when described as "at least one (or more) of A (and), B, and C", at least one of all combinations of A, B, and C may be included. In addition, when describing elements of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used.

[0065] These terms are only used to distinguish an element from other elements, and these terms do not limit the nature, order or sequence of the elements. In addition, when an element is described as being "connected" or "coupled" to another element, it may include not only that the element is directly "connected" or "coupled" to another element, but also that the element is "connected" or "coupled" through other elements between the element and another element.

[0066] Furthermore, when described as being formed or disposed “on (above)” or “under (below)” each element, “on (above)” or “under (below)” may include not only two elements being directly connected to each other but also one or more other elements being formed or disposed between the two elements. Furthermore, when expressed as “on (above)” or “under (below)”, not only an upper direction based on one element but also a lower direction may be included.

[0067] Electronic devices

[0068] Before describing the embodiment, an electronic device including a semiconductor package of the embodiment will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. In addition, various semiconductor devices can be installed in the semiconductor package.

[0069] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor devices in the form of integrated circuits (ICs), in which hundreds to millions of devices are integrated into one chip. Semiconductor devices may be logic chips, memory chips, and the like. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), and the like. For example, a logic chip may be an AP including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), and the like, or a chipset including a specific combination of the above.

[0070] The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, or the like.

[0071] Meanwhile, the product group of the semiconductor package to which the embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip - chip scale package), FC-BGA (flip chip ball grid array), POP (stacked package) and SIP (system in package), but is not limited thereto.

[0072] In addition, the electronic device may be a smart phone, a personal digital assistant, a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, a car, etc. However, the embodiment is not limited thereto and may be any other electronic device that processes data.

[0073] Semiconductor packaging

[0074] Hereinafter, a semiconductor package according to an embodiment will be described.

[0075] Figure 1 is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0076] refer to Figure 1 , the semiconductor package includes a substrate 100 .

[0077] In one embodiment, the substrate 100 may be a packaging substrate. For example, the substrate 100 may be a substrate disposed between a semiconductor device and a mainboard of an electronic device. For example, the substrate 100 may be a substrate disposed between an interposer on which a semiconductor device is mounted and a mainboard. In this case, the interposer may be an active interposer that also performs the function of a semiconductor device, or may be a passive interposer that only performs an electrical connection function.

[0078] In another embodiment, the substrate 100 may be an interposer, for example, the substrate 100 may be a substrate disposed between a package substrate 600 connected to a mainboard of an electronic device and a semiconductor device. Figure 2 is shown and will be referred to Figure 2 Give a description.

[0079] The substrate 100 includes an insulating layer 110 , an electrode layer 120 , and through electrodes 130 .

[0080] The insulating layer 110 of the substrate 100 may have a layer structure of at least one layer or more layers. Preferably, the insulating layer 110 of the substrate 100 may have a multi-layer structure. In this way, the substrate 100 of the embodiment can effectively electrically connect the mainboard and the semiconductor device of the electronic device. At this time, Figure 1 The insulating layer 110 of the substrate 100 in FIG. 1 is shown to have a three-layer structure, but is not limited thereto. For example, the insulating layer 110 of the substrate 100 may have two layers or less, or may have four layers or more.

[0081] When the insulating layer 110 of the substrate 100 has a multi-layer structure, the plurality of insulating layers of the substrate 100 may include the same insulating material, but is not limited thereto. For example, at least one of the plurality of insulating layers of the substrate 100 may include an insulating material different from another insulating layer.

[0082] The insulating layer 110 of the substrate 100 may be rigid or flexible. For example, the insulating layer 110 of the substrate 100 may include glass or plastic. For example, the insulating layer 110 of the substrate 100 may include chemically strengthened / semi-strengthened glass, such as soda-lime glass or aluminosilicate glass. For example, the insulating layer 110 of the substrate 100 may include reinforced or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 110 of the substrate 100 may include sapphire. For example, the insulating layer 110 of the substrate 100 may include an optically isotropic film. For example, the insulating layer 110 of the substrate 100 may include COC (cyclic olefin copolymer), COP (cyclic olefin polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 110 of the substrate 100 may be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 110 of the substrate 100 may have a structure in which an inorganic filler of silicon dioxide or aluminum oxide is provided in a thermosetting resin or a thermoplastic resin.

[0083] Specifically, in one embodiment, the insulating layer 100 of the substrate 100 may include a first insulating layer having reinforcing fibers, and a second insulating layer disposed on the top and bottom of the first insulating layer and having no reinforcing fibers. Therefore, the substrate 100 may be a core substrate.

[0084] In addition, in another embodiment, the insulating layer 100 of the substrate 100 may consist of only an insulating layer without reinforcing fibers. Therefore, the substrate 100 may be a coreless substrate.

[0085] In one embodiment, the insulating layer 110 of the substrate 100 may include an organic material that does not include a reinforcement having excellent processability, excellent rigidity, enabling thinning of the substrate 100, and enabling miniaturization of the electrode layer 120 of the substrate 100. The reinforcement may also be referred to as reinforcement fiber or glass fiber.

[0086] For example, the insulating layer 110 of the substrate 100 may be made of ABF (Ajinomoto deposited film), FR-4, BT (bismaleimide triazine), PID (photo imaging dielectric resin), BT, or the like.

[0087] At this time, if the insulating layer 110 of the substrate 100 is formed of ABF (Ajinomoto deposited film), the bending characteristics of the substrate 100 may be deteriorated.

[0088] Therefore, in another embodiment, the insulating layer 110 of the substrate 100 is composed of ABF (Ajinomoto deposited film), and at least one ABF among the plurality of insulating layers of the substrate 100 may include a reinforcing material capable of improving bending characteristics.

[0089] For example, the insulating layer 110 of the substrate 100 includes a layer composed of a first ABF including a resin and a filler. In addition, the insulating layer 110 of the substrate 100 includes a layer composed of a second ABF containing more reinforcing material in the first ABF. At this time, the reinforcing material included in the second ABF may be glass fiber and may include a GCP (glass core primer) material, but is not limited thereto.

[0090] The thickness of each layer of the insulating layer 110 of the substrate 100 may be in the range of 10 μm to 40 μm. Preferably, the thickness of each layer of the insulating layer 110 of the substrate 100 may be in the range of 15 μm to 35 μm. More preferably, the thickness of each layer of the insulating layer 110 of the substrate 100 may be in the range of 18 μm to 32 μm. If the thickness of each layer of the insulating layer 110 of the substrate 100 is less than 10 μm, the bending characteristics of the substrate 100 may be deteriorated. In addition, if the thickness of each layer of the insulating layer 110 of the substrate 100 is less than 10 μm, the electrode layer 120 of the substrate 100 may not be stably protected, and thus the electrical reliability may be deteriorated. In addition, if the thickness of each layer of the insulating layer 110 of the substrate 100 exceeds 40 μm, the overall thickness of the substrate 100 will increase, and therefore, the thickness of the semiconductor package may increase. In addition, if the thickness of each layer of the insulating layer 110 of the substrate 100 exceeds 40 μm, it is difficult to miniaturize the electrode layer 120 of the substrate 100 .

[0091] The thickness of each layer of the insulating layer 110 of the substrate 100 may correspond to the distance between the electrode layers provided in different layers in the vertical direction of the substrate. That is, the thickness may represent the length from the upper surface to the lower surface, or from the lower surface to the upper surface of the substrate 100, and may represent the length in the vertical direction of the substrate. Here, the upper surface may represent the highest position in the vertical direction of each component, and the lower surface may represent the lowest position in the vertical direction of each component. In addition, the position may also be referred to in reverse.

[0092] Meanwhile, the semiconductor package of the embodiment includes a first protective layer 140 disposed on the upper surface of the substrate 100. In addition, the semiconductor package includes a second protective layer 150 disposed on the lower surface of the substrate 100.

[0093] The insulating layer 110 of the substrate 100 may have a multi-layer structure. In addition, the upper surface of the insulating layer 110 described below may mean the upper surface of the uppermost layer among the insulating layers provided with a plurality of layers. In addition, the lower surface of the insulating layer 110 described below may mean the lower surface of the lowermost layer among the insulating layers 110 provided with a plurality of layers. At this time, when the first protective layer 140 is provided on the upper surface of the insulating layer 110, and the first protective layer 140 is a protective layer provided with a material different from the material constituting the insulating layer 110, the upper surface of the insulating layer 110 and the lower surface of the first protective layer 140 may be distinguished. In addition, when the second protective layer 150 is provided on the lower surface of the insulating layer 110, and the second protective layer 150 is a protective layer provided with a material different from the material constituting the insulating layer 110, the lower surface of the insulating layer 110 and the upper surface of the second protective layer 150 may be distinguished.

[0094] The substrate 100 includes an electrode layer 120. The electrode layer 120 may be disposed on a surface of the insulating layer 110 of the substrate 100. For example, when the insulating layer 110 of the substrate 100 has a three-layer structure, the electrode layer 120 may be disposed on surfaces of the three insulating layers, respectively.

[0095] At this time, one of the electrode layers 120 of the substrate 100 may have an ETS (embedded trace substrate) structure. For example, the electrode layer disposed on the upper surface of the insulating layer 110 of the substrate 100 may have an ETS structure. Therefore, at least a portion of the electrode layer disposed on the uppermost side of the substrate 100 may be disposed in a groove (not shown) formed on the upper surface of the insulating layer 110. Therefore, the ETS structure may also be referred to as a buried layer structure. Compared with an electrode layer having a general protruding structure, the ETS structure is conducive to miniaturization. Therefore, the embodiment enables miniaturization of the electrode layer disposed on the upper surface of the insulating layer 110 of the substrate 100 by having an ETS structure. That is, the electrode layer disposed on the upper surface of the insulating layer 110 includes an electrode connected to a semiconductor device or an external substrate. Therefore, the embodiment is capable of forming an electrode corresponding to the size and pitch of a terminal disposed in a semiconductor device. In this way, the embodiment is capable of improving circuit integration. In addition, the embodiment is capable of minimizing the transmission distance of a signal transmitted through a semiconductor device, thereby minimizing signal transmission loss.

[0096] At this time, the first electrode pattern 120a-1 of the electrode layer 120 may include a protrusion that protrudes further toward the semiconductor device 220 than the upper surface of the first protective layer 140. The protrusion may be called a bump. The protrusion may also be called a pillar. The protrusion may also be called a pillar. That is, as the pitch of the terminal 225 of the semiconductor device 220 becomes finer, the problem of short circuit of the conductive adhesive disposed on the plurality of terminals 225 may occur. Therefore, in order to reduce the volume of the conductive adhesive disposed on each of the plurality of terminals 225, the first electrode pattern 120a-1 may include a protrusion. In addition, when TC (thermocompression) bonding is used to apply heat and pressure to the conductive adhesive disposed between the first electrode pattern 120a-1 and the terminal 225 of the semiconductor device 220 to bond them, the protrusion may also play a role in improving the alignment between the first electrode pattern 120a-1 and the terminal 225 of the semiconductor device 220 and preventing the conductive adhesive from spreading.

[0097] The electrode layer 120 of the substrate 100 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the electrode layer 120 of the substrate 100 may be formed of a paste or solder paste including at least one metal material having excellent bonding strength selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the electrode layer 120 of the substrate 100 may be formed of copper (Cu) having high electrical conductivity and relatively low price.

[0098] The thickness of the electrode layer 120 of the substrate 100 may be in the range of 7 μm to 20 μm. For example, the thickness of the electrode layer 120 of the substrate 100 may be in the range of 9 μm to 17 μm. The thickness of the electrode layer 120 of the substrate 100 may be in the range of 10 μm to 13 μm. If the thickness of the electrode layer 120 of the substrate 100 is less than 7 μm, the resistance of the electrode layer 120 may increase, and the allowable current of the transmittable signal may decrease. In addition, if the thickness of the electrode layer 120 of the substrate 100 exceeds 20 μm, it may be difficult to miniaturize the electrode layer 120.

[0099] The electrode layer 120 of the substrate 100 may include a through pad connected to the through electrode 130 of the substrate 100 and at least one electrode pattern connected to an external substrate or semiconductor device. In addition, the electrode layer 120 of the substrate 100 may include a trace of a signal transmission line connected to the through pad or the electrode pattern.

[0100] The width of the through pad or electrode pattern of the electrode layer 120 of the substrate 100 may be in the range of 15 μm to 90 μm. The width of the through pad or electrode pattern of the electrode layer 120 of the substrate 100 may be in the range of 20 μm to 85 μm. The width of the through pad or electrode pattern of the electrode layer 120 of the substrate 100 may be in the range of 25 μm to 80 μm.

[0101] At this time, the through pads or electrode patterns of the electrode layer 120 of the substrate 100 may have different widths within the above range according to the functions. In addition, the electrodes of the electrode layer 120 of the substrate 100 may have different widths corresponding to the size of the terminals of the connected semiconductor device or the size of the pads of the external substrate.

[0102] For example, the electrode layer 120 of the substrate 100 may include a plurality of electrode patterns. For example, the electrode layer 120 of the substrate 100 may include a first electrode layer 120a disposed on the upper surface of the insulating layer 110. In addition, the first electrode layer 120a may include a plurality of electrode patterns. For example, the first electrode layer 120a may include a first electrode pattern 120a-1 vertically overlapping the semiconductor device 220. The first electrode pattern 120a-1 may represent a pattern directly connected to the terminal 225 of the semiconductor device 220. In addition, the first electrode layer 120a may include a second electrode pattern 120a-2 that does not vertically overlap the semiconductor device 220.

[0103] The first electrode pattern 120a-1 is directly connected to the terminal 225 of the semiconductor device 220. The terminal 225 of the semiconductor device 220 is provided in plurality, and therefore, the first electrode pattern 120a-1 may also be provided in plurality. At this time, the shape, size, and pitch of at least one electrode pattern among the plurality of first electrode patterns 120a-1 may be different from the shape, size, and pitch of at least one other electrode pattern.

[0104] If the first electrode pattern 120a-1 includes a protrusion, the width of the protrusion may be in the range of 4 μm to 70 μm. If the width of the protrusion is less than 40 μm, the width of the protrusion may be too small, resulting in a collapse problem during TC bonding. In addition, if the width of the protrusion is greater than 70 μm, it may be difficult to correspond to the fine pitch of the terminal 225 of the semiconductor device 220.

[0105] The substrate 100 may include a through electrode 130. The through electrode 130 of the substrate 100 may pass through the insulating layer 110 of the substrate 100. The through electrode 130 of the substrate 100 may be connected between electrode layers provided in different insulating layers of the substrate 100. The through electrode 130 may represent an electrode connecting the electrode layer 120 and the first electrode pattern 120a-1 or the electrode layer 120 and the second electrode pattern 120-2. The width of the through electrode 130 may be smaller than the width of the first electrode pattern 120a-1 and / or the second electrode pattern 120-2. In addition, the vertical thickness of the through electrode 130 may be greater than the vertical thickness of the first electrode pattern 120a-1 and / or the second electrode pattern 120-2. When the electrode layer is embedded in the insulating layer, the through electrode 130 may pass between the electrode layers provided in the insulating layer. In addition, when the electrode layer protrudes from the upper and lower surfaces of the insulating layer, the through electrode 130 may completely pass through the insulating layer.

[0106] The through-electrode 130 of the substrate 100 may be formed by filling the inside of a through-hole penetrating the insulating layer 110 of the substrate 100 with a conductive material.

[0107] The through hole can be formed by any one of mechanical, laser, and chemical processing methods. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. In addition, when the through hole is formed by laser processing, a UV or CO2 laser method can be used. In addition, when the through hole is formed by chemical processing, a chemical agent including aminosilane, ketones, etc. can be used.

[0108] When forming the through hole, the inside of the through hole may be filled with a conductive material to form the through electrode 130 of the substrate 100. The metal material forming the through electrode may be any one selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni) and palladium (Pd). In addition, the conductive material filling may be any one of chemical plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet and dispensing, or a combination thereof.

[0109] The semiconductor package of the first embodiment may include a first protective layer 140 disposed on a substrate 100. In addition, the semiconductor package may include a second protective layer 150 disposed below the substrate 100. At this time, the upper surface of the package substrate may represent the upper surface of the first protective layer 140, and the lower surface of the package substrate may represent the lower surface of the second protective layer 150. However, when the package substrate does not include the first protective layer 140 and the second protective layer 150, the upper surface and the lower surface of the package substrate may represent the upper surface and the lower surface of the substrate 100.

[0110] The first protective layer 140 and the second protective layer 150 may have a function of protecting the substrate 100. For example, the first protective layer 140 and the second protective layer 150 may have a function of protecting the surface of the insulating layer 110 or the surface of the electrode layer 120 of the substrate 100. Therefore, the first protective layer 140 and the second protective layer 150 may also be functionally expressed as "protective layers".

[0111] For example, the first protective layer 140 and the second protective layer 150 may be a resist layer. Preferably, the first protective layer 140 and the second protective layer 150 may be a solder resist layer including an organic polymer material. For example, the first protective layer 140 and the second protective layer 150 may include an epoxy acrylate series resin. Specifically, the first protective layer 140 and the second protective layer 150 may include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, etc. However, the embodiment is not limited thereto, and the first protective layer 140 and the second protective layer 150 may of course be any one of a photo solder resist layer, a cover layer (cover-lay), and a polymer material.

[0112] The thickness of each of the first protective layer 140 and the second protective layer 150 may be 1 μm to 20 μm. The thickness of each of the first protective layer 140 and the second protective layer 150 may be 1 μm to 15 μm. For example, the thickness of each of the first protective layer 140 and the second protective layer 150 may be 5 μm to 20 μm. If the thickness of each of the first protective layer 140 and the second protective layer 150 exceeds 20 μm, the thickness of the semiconductor package may increase, or stress may be applied to the substrate 100. If the thickness of each of the first protective layer 140 and the second protective layer 150 is less than 1 μm, the electrode layer 120 included in the substrate 100 is not stably protected, and therefore, electrical reliability or physical reliability may be deteriorated.

[0113] The first protective layer 140 may be divided into a plurality of regions in the horizontal direction. For example, the first protective layer 140 may include a peripheral region 140a or an outer region or an edge region adjacent to the periphery 140c on the upper surface of the first protective layer 140. In addition, the first protective layer 140 may include an inner region 140b other than the peripheral region 140a.

[0114] In addition, the first protective layer 140 may include a plurality of opening regions. For example, the first protective layer 140 includes an upper surface and a lower surface opposite to the upper surface.

[0115] In addition, the first protection layer 140 may include a plurality of opening regions penetrating the upper surface and the lower surface. The opening regions may also be referred to as “openings”.

[0116] For example, the first protective layer 140 may include a first opening 141 disposed in a peripheral region 140a adjacent to a periphery 140c of an upper surface of the first protective layer 140. In addition, the first protective layer 140 may include a second opening 142 disposed in an inner region 140b.

[0117] At this time, the planar shape of the first opening 141 of the first protective layer 140 may be different from the planar shape of the second opening 142 , but is not limited thereto.

[0118] The diameter of the first opening 141 of the first protective layer 140 may be different from the diameter of the second opening 142. Preferably, the diameter of the first opening 141 of the first protective layer 140 may be greater than the diameter of the second opening 142. That is, the area of ​​the first protective layer 140 opened by one first opening 141 may be greater than the area of ​​the first protective layer 140 opened by one second opening 142.

[0119] The first opening 141 and the second opening 142 may have different functions.

[0120] The first opening 141 may be used as an exhaust hole. Therefore, the first opening 141 may be disposed adjacent to the outer surface of the first protective layer 140. In addition, the first opening 141 may have a larger diameter than the second opening 142 to improve exhaust performance.

[0121] The second opening 142 may vertically overlap the first electrode pattern 120a-1 of the first electrode layer 120a. Therefore, the second opening 142 may have a diameter corresponding to the width of the first electrode pattern 120a-1 of the first electrode layer 120a. The second opening 142 may have a function of exposing the first electrode pattern 120a-1 in the first electrode layer 120a, which is electrically connected to the terminal 225 of the semiconductor device 220, from the first protective layer 140. Therefore, the second opening 142 may have a smaller diameter than the first opening 141. Meanwhile, the diameter may represent the width in the first horizontal direction or the width in the second horizontal direction, but is not limited thereto.

[0122] The diameter of the first opening 141 may be determined according to the total area of ​​the substrate 100 and the amount of the applied adhesive member 240. For example, the diameter of the first opening 141 may increase in proportion to the area of ​​the substrate 100 or the amount of the applied adhesive member 240.

[0123] Meanwhile, the diameter of the second opening 142 may be determined by the width of the first electrode pattern 120a-1 of the first electrode layer 120a. At this time, due to the miniaturization of the terminal 225 of the semiconductor device 220, the width of the first electrode pattern 120a-1 also becomes smaller. Therefore, the diameter of the second opening 142 may be smaller than the diameter of the first opening 141.

[0124] In one embodiment, the first opening 141 may not vertically overlap with the first electrode layer 120a. For example, the first opening 141 may not vertically overlap with the first electrode pattern 120a-1 and the second electrode pattern 120a-2 of the first electrode layer 120a. Therefore, the first opening 141 may expose the upper surface of the insulating layer 110 of the substrate 100 instead of the upper surface of the first electrode layer 120a.

[0125] In another embodiment, the first opening 141 may overlap vertically with at least one electrode pattern of the first electrode layer 120a. For example, the first electrode layer 120a may include an electrode pattern corresponding to a grounding electrode having a grounding function, or an electrode pattern corresponding to a heat dissipation electrode having a heat dissipation function. In addition, the first opening 141 may overlap vertically with a grounding electrode pattern or a heat dissipation electrode pattern of the first electrode layer 120a. Therefore, the embodiment allows the heat transferred through the grounding electrode pattern or the heat dissipation electrode pattern to be dissipated to the outside, while exhausting gas through the first opening 141.

[0126] Different from this, the second opening 142 may be provided to expose the first electrode pattern 120a-1 of the first electrode layer 120a coupled to the terminal 225 of the semiconductor device 220. For example, the second opening 142 may be provided in the bonding region between the terminal 225 of the semiconductor device 220 and the first electrode pattern 120a-1 of the first electrode layer 120a. At this time, the bonding between the terminal 225 of the semiconductor device 220 and the first electrode pattern 120a-1 of the first electrode layer 120a may represent wire bonding, solder bonding, direct metal bonding, etc. Wire bonding may represent the use of a conductor such as gold (Au) to electrically connect the terminal 225 of the semiconductor device 220 to the first electrode pattern 120a-1. In addition, solder bonding may represent the use of a material including at least one of Sn, Ag, and Cu to electrically connect the terminal 225 of the semiconductor device 220 to the first electrode pattern 120a-1. In addition, direct metal bonding may mean that heat and pressure are applied to the first electrode pattern 120a-1 and the terminal 225 of the semiconductor device 220 to recrystallize without solder, wires, conductive adhesives, etc., thereby directly connecting the first electrode pattern 120a-1 and the terminal 225 of the semiconductor device 220.

[0127] Meanwhile, the first opening 141 may be connected to the outer side surface of the first protective layer 140. That is, the first opening 141 may refer to a through hole that is recessed inward from the outer side surface of the first protective layer 140 and passes through the upper and lower surfaces of the first protective layer 140.

[0128] In contrast, the second opening 142 may be spaced apart from the first opening 141 , and also spaced apart from the outer side surface of the first protective layer 140 .

[0129] Meanwhile, the second protective layer 150 may also include an opening, and the opening of the second protective layer 150 may vertically overlap with the electrode pattern disposed on the lower surface of the insulating layer 110 of the substrate 100 .

[0130] The semiconductor package of the embodiment includes a first connection portion 210. The first connection portion 210 is disposed on the substrate 100. For example, the first connection portion 210 is disposed on the first electrode pattern 120a-1 of the first electrode layer 120a of the substrate 100. At this time, if the first electrode pattern 120a-1 is bonded to the terminal 225 of the semiconductor device 220 by direct metal bonding, the first connection portion 210 may be omitted. Alternatively, if the first electrode pattern 120a-1 is bonded to the terminal 225 of the semiconductor device 220 by direct metal bonding, the first connection portion 210 may represent a metal layer recrystallized by direct bonding.

[0131] The first connection portion 210 may have a hexahedral shape. The cross section of the first connection portion 210 may include a square shape. The cross section of the first connection portion 210 may include a rectangular or square shape. For example, the first connection portion 210 may include a spherical shape. For example, the cross section of the first connection portion 210 may include a circular shape or a semicircular shape. For example, the cross section of the first connection portion 210 may include a partially circular shape or a fully circular shape. The cross-sectional shape of the first connection portion 210 may be flat on one side and curved on the other side. The first connection portion 210 may be a solder ball, but is not limited thereto.

[0132] The semiconductor package of the embodiment includes a component disposed on the first connection portion 210. The component disposed on the first connection portion 210 may be a semiconductor device, or alternatively, may be an interposer.

[0133] The semiconductor device 220 may be a logic chip, but is not limited thereto. For example, the semiconductor device 220 may be a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or an application processor (AP) chip in a microcontroller. The semiconductor device 220 includes a terminal 225 disposed on the lower surface of the semiconductor device 220. In addition, the terminal 225 of the semiconductor device 220 may be electrically connected to the first electrode pattern 120a-1 of the electrode layer 120 of the substrate 100 through the first connection portion 210.

[0134] In addition, the semiconductor package may include a molding 230. The molding 230 may mold a portion of the configuration coupled to the substrate 100. The molding 230 may refer to an underfill molding one side of the semiconductor device 220. In addition, the molding 230 may refer to a molding layer molding one side of the semiconductor device 220. In addition, the molding 230 may include both the underfill and the molding layer.

[0135] The molding member 230 may mold the first connection portion 210. In addition, the molding member 230 may mold the terminal 225 of the semiconductor device 220. In addition, the molding member 230 may mold at least a portion of one side of the semiconductor device 220. The molding member 230 may open the upper surface of the semiconductor device 220.

[0136] The molding 230 may be EMC (epoxy molding compound), but the embodiment is not limited thereto. The molding 230 may have a low dielectric constant. For example, the dielectric constant (Dk) of the molding 230 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding 230 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding 230 may be 0.8 to 5. Therefore, in the embodiment, the molding 230 has a low dielectric constant, so that the heat generated by the semiconductor device 220 can be effectively dissipated to the outside.

[0137] The semiconductor package includes a second connection portion 260 .

[0138] The second connection portion 260 may be provided on the lower surface of the substrate 100. For example, the second connection portion 260 may be provided on the lower surface of the electrode pattern of the electrode layer 120 provided on the lower surface of the substrate 100. For example, the second connection portion 260 may be provided in the opening of the second protective layer 150. The second connection portion 260 may be a solder for connecting the semiconductor package of the embodiment to a separate external substrate (for example, a main board of an electronic device), but is not limited thereto.

[0139] The semiconductor package includes an adhesive member 240 .

[0140] The adhesive member 240 may be disposed on the upper surface of the first protective layer 140. Preferably, the adhesive member 240 may include a material having an adhesive property. The adhesive member 240 may be an epoxy resin, but is not limited thereto. For example, the adhesive member 240 may be any one of a thermosetting adhesive, an ultraviolet curing adhesive, and an adhesive film.

[0141] The adhesive member 240 may be disposed on the upper surface of the first protective layer 140 along a peripheral direction of the upper surface of the first protective layer 140. The peripheral direction may refer to an edge direction disposed along an edge of the upper surface of the first protective layer 140.

[0142] For example, the adhesive member 240 may be disposed in the peripheral region 140a of the upper surface of the first protective layer 140 along the peripheral direction of the upper surface of the first protective layer 140. That is, the peripheral region 140a is disposed along the peripheral direction of the upper surface of the first protective layer 140 while being adjacent to the periphery 140c of the upper surface of the first protective layer 140. In addition, the adhesive member 240 may be disposed in the peripheral region 140a of the first protective layer 140.

[0143] At this time, the adhesive member 240 may be provided in an open loop shape along the peripheral direction of the upper surface of the first protective layer 140. For example, the adhesive member 240 may not be completely provided in the peripheral region 140a of the first protective layer 140, but may be partially provided in the peripheral region 140a of the first protective layer 140. For example, the peripheral region 140a of the first protective layer 140 may include an adhesive member provided region where the adhesive member 240 is provided and an adhesive member non-provided region where the adhesive member 240 is not provided. The adhesive member non-provided region may refer to a separation region between one end and the other end of the adhesive member 240 having an open loop shape.

[0144] In this way, the embodiment allows the adhesive member 240 to have an open loop shape, and therefore, the adhesive member 240 is not disposed in at least a portion of the peripheral region 140a of the first protective layer 140. In addition, the area in the peripheral region 140a where the adhesive member 240 is not disposed can be used as a vent. For example, when the adhesive member 240 has a closed loop shape, the gas present in the cavity space defined by the internal space of the cover member 300 may not be discharged to the outside of the cavity space. That is, the embodiment may perform a heat treatment that combines the adhesive member 240 and the cover member 300. In addition, during the heat treatment, gas may be generated in the internal space. At this time, when the adhesive member 240 has a closed loop shape, the gas generated in the cavity space may not be discharged to the outside. Therefore, in an embodiment, the adhesive member 240 is set to have an open loop shape, and in this way, the gas present in the cavity space can be discharged to the outside of the cavity space through the separation area between one end and the other end of the adhesive member 240.

[0145] However, the separation area between one end and the other end of the bonding member 240 alone may not be enough to discharge the gas present in the cavity space to the outside. That is, due to the high specifications of the semiconductor package, the area of ​​the semiconductor package is increasing. Therefore, the amount of the applied bonding member 240 is increasing. Therefore, if the gas is discharged only through the separation area between one end and the other end of the bonding member 240, the gas in the cavity space cannot be fully discharged to the outside, so physical reliability problems may occur. At this time, the area of ​​the separation area where the bonding member 240 is not provided can be increased to ensure that the space where the gas can be discharged. However, as the area of ​​the semiconductor package increases, the size of the cover member 300 also increases. In addition, if the area of ​​the separation area increases, the bonding force between the cover member 300 and the substrate 100 cannot be fully ensured, which may cause a physical reliability problem of the separation of the cover member 300 from the substrate 100. In other words, if the area of ​​the separation area is reduced, the problem of not being able to fully discharge the gas will occur, and if the area of ​​the separation area is increased, the problem of not being able to ensure the bonding force between the cover member 300 and the substrate 100 will occur.

[0146] Therefore, the embodiment uses the first opening 141 provided in the first protective layer 140 to allow the gas present in the cavity space to be discharged to the outside of the cavity space.

[0147] To this end, the first opening 141 of the first protective layer 140 may vertically overlap with the separation region of the adhesive member 240. In other words, the first opening 141 of the first protective layer 140 may be connected to the separation region of the adhesive member 240. Therefore, the embodiment may exhaust the gas existing in the cavity space not only through the separation region but also through the first opening 141 of the first protective layer 140 connected to the separation region.

[0148] In other words, the peripheral region 140a of the first protective layer 140 includes a setting region where the adhesive member 240 is set and a non-setting region where the adhesive member 240 is not set. In addition, the first opening 141 of the first protective layer 140 vertically overlaps with the non-setting region of the peripheral region 140a. Therefore, the separation distance in the vertical direction between the lower surface of the cover member 300 and the substrate 100 can increase the depth of the first opening 141. In this way, the embodiment can fully discharge the gas generated in the cavity space to the outside. Therefore, the embodiment can further improve the physical reliability and electrical reliability of the semiconductor package.

[0149] The semiconductor package includes a cover member 300 .

[0150] The cover member 300 is disposed on the adhesive member 240. The cover member 300 may include an inner receiving space defining a cavity space.

[0151] The cover member 300 may have a shape in which a lower side is opened while including a receiving space inside.

[0152] The cover member 300 includes a side plate portion 310 disposed on the substrate 100 and covering one side of the semiconductor device 220. In addition, the side plate portion 310 may include a first portion in contact with the adhesive member 240 and a second portion extending from the first portion in a direction away from the substrate. For example, the side plate portion 310 may have a stepped shape, but is not limited thereto.

[0153] The cover member 300 includes an upper plate portion 320 extending from an upper end of the side plate portion 310 and covering an upper portion of the semiconductor device 220. In addition, the cover member 300 may form a cavity space accommodating the semiconductor device 220 inside through the side plate portion 310 and the upper plate portion 320.

[0154] The lower surface of the cover member 300 may contact the adhesive member 240. Specifically, the lower surface of the side plate part 310 of the cover member 300 may contact the adhesive member 240.

[0155] At this time, the lower surface of the side plate portion 310 of the cover member 300 may include a first lower surface that vertically overlaps with the adhesive member 240 and contacts with the adhesive member 240. In addition, the lower surface of the side plate portion 310 of the cover member 300 may include a second lower surface that does not vertically overlap with the adhesive member 240 and does not contact the adhesive member 240. For example, the second lower surface of the side plate portion 310 of the cover member 300 may be a portion that vertically overlaps with the separation area of ​​the adhesive member 240. At this time, the second lower surface of the side plate portion 310 of the cover member 300 may vertically overlap with the first opening 141 of the first protective layer 140. Therefore, at least a portion of the second lower surface of the side plate portion 310 of the cover member 300 may be positioned to directly face the upper surface of the substrate 100 through the separation area and the first opening 141.

[0156] The cover member 300 may overlap vertically with the electrode layer 120. The upper plate portion 320 of the cover member 300 may overlap vertically with the semiconductor device 220 and / or the electrode layer 120. In addition, the side plate portion 310 of the cover member 300 may overlap vertically with the electrode layer 120. The side plate portion 310 may include a first region vertically overlapping with the first opening 141 and a second region vertically overlapping with the first adhesive member 240. In addition, when the first region does not overlap vertically with the first protective layer 140, the first region may not overlap vertically with the electrode layer 120 to prevent the electrode layer 120 from being oxidized or degraded by the gas flowing through the first opening 141. However, since the electrode layer 120 is protected by the first protective layer 140 and / or the first adhesive member 240 in the second region and is not affected by the flowing gas, the routing of the electrode layer 120 can be freely designed so that the second region can overlap vertically with the electrode layer 120.

[0157] The cover member 300 covers the periphery of the cavity space, and thus may have a function of protecting the semiconductor device 220 accommodated in the cavity space. In addition, the cover member 300 may have a heat dissipation function of dissipating heat generated by the semiconductor device 220 to the outside. To this end, the cover member 300 may include a metal material having excellent heat transfer characteristics, but is not limited thereto.

[0158] Meanwhile, the semiconductor package of the embodiment includes a second adhesive member 410. The second adhesive member 410 may be disposed on the upper surface of the semiconductor device 220. In addition, the second adhesive member 410 may be disposed on the lower surface of the upper plate portion 320 of the cover member 300. Specifically, the second adhesive member 410 may be disposed between the semiconductor device 220 and the cover member 300. The second adhesive member 410 allows the cover member 300 to be coupled to the semiconductor device 220. In addition, the second adhesive member 410 may transfer the heat generated by the semiconductor device 220 to the cover member 300. To this end, the second adhesive member 410 may include a material having excellent heat transfer characteristics. For example, the second adhesive member 410 may be a TIM (thermal interface material) capable of heat transfer. Preferably, the second adhesive member 410 may be a TIM slurry. The TIM slurry may be composed of a mixture of alumina, wax, solvent, etc., but is not limited thereto.

[0159] In addition, the semiconductor package includes a third adhesive member 420. The third adhesive member 420 is disposed on the cover member 300. Preferably, the third adhesive member 420 is disposed on the upper surface of the upper plate portion 320 of the cover member 300. The third adhesive member 420 may be disposed between the heat dissipation plate 430 and the cover member 300. The third adhesive member 420 may allow the heat dissipation plate 430 to be coupled to the cover member 300. The third adhesive member 420 may transfer heat transferred from the cover member 300 to the heat dissipation plate 430. To this end, the third adhesive member 420 may include a material having excellent heat transfer properties. For example, the third adhesive member 420 may be a TIM paste, but is not limited thereto.

[0160] The semiconductor package includes a heat dissipation plate 430 coupled to the third adhesive member 420. The heat dissipation plate 430 may be a heat sink. The heat dissipation plate 430 may release heat transferred from the cover member 300 to the outside. The heat dissipation plate 430 may have a structure including a plurality of heat dissipation fins spaced apart from each other, but is not limited thereto.

[0161] Figure 2 is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0162] See also Figure 2 The semiconductor package of the second embodiment is different from the semiconductor package of the first embodiment in the structure of the substrate 100. Therefore, only the structure of the substrate 100 will be described below.

[0163] The semiconductor package of the first embodiment has a structure in which one semiconductor device 220 is mounted on a substrate 100. Unlike this, the semiconductor package of the second embodiment may have a plurality of semiconductor devices mounted on a substrate 100 spaced apart from each other in a horizontal direction.

[0164] In addition, the substrate 100 of the first embodiment is a package substrate. That is, the substrate 100 of the first embodiment is a package substrate provided between a semiconductor device and a main board.

[0165] Different from this, the substrate 100 of the second embodiment is an interposer. That is, the substrate 100 of the second embodiment may represent an interposer provided between the semiconductor device and the package substrate 600.

[0166] In addition, the first electrode patterns 120 a - 1 of the first electrode layer 120 a may be divided into a first group of first electrode patterns and a second group of first electrode patterns.

[0167] In addition, the semiconductor package of the second embodiment may include a first semiconductor device 220 a disposed on the first electrode pattern of the first group. The terminal 225 a of the first semiconductor device 220 a may be electrically connected to the first electrode pattern of the first group through the first connection portion 210 .

[0168] In addition, the semiconductor package of the second embodiment may include a second semiconductor device 220 b disposed on the first electrode pattern of the second group. The terminal 225 b of the second semiconductor device 220 b may be electrically connected to the first electrode pattern of the second group through the first connection portion 210 .

[0169] The first semiconductor device 220 a and the second semiconductor device 220 b may be logic chips of the same type or logic chips of different types.

[0170] Meanwhile, the molding member 230 of the semiconductor package of the second embodiment may mold the first semiconductor device 220 a and the second semiconductor device 220 b at the same time.

[0171] In addition, the second adhesive member 410 of the semiconductor package of the second embodiment may be disposed on the first semiconductor device 220a and the second semiconductor device 220b. At this time, the second adhesive member 410 may also be disposed in a separation region between the first semiconductor device 220a and the second semiconductor device 220b, but is not limited thereto.

[0172] Figure 3 is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0173] refer to Figure 3 The semiconductor package of the third embodiment is different from the semiconductor package of the first embodiment in the structure of the substrate 100. Therefore, only the structure of the substrate 100 will be described below.

[0174] Figure 1 The semiconductor package of the first embodiment may be a coreless substrate. In addition, Figure 3 The semiconductor package of the third embodiment may be a core substrate.

[0175] refer to Figure 3 , the substrate 100 includes an insulating layer 110. In addition, the insulating layer 110 may have a multilayer structure. The insulating layer 110 may include a core layer 111. The core layer 111 may include a prepreg. The prepreg may be formed by impregnating a fiber layer in the form of a fabric sheet (e.g., a glass fabric woven with glass fiber yarn) with an epoxy resin or the like and then performing thermal compression. The core layer 111 may include a resin and reinforcing fibers disposed in the resin. The resin may be an epoxy resin, but is not limited thereto.

[0176] The insulating layer 110 of the substrate 100 may further include an additional insulating layer 112 disposed on the core layer 111. The additional insulating layer 112 may be ABF that does not include the reinforcement material included in the substrate 100 of the first embodiment.

[0177] At this time, the electrode of the electrode layer 120 of the substrate 100 of the second embodiment may have a structure protruding on the upper surface of the insulating layer 110 of the substrate 100 .

[0178] Figure 4 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0179] refer to Figure 4 The semiconductor package of the fourth embodiment is different from the semiconductor package of the first embodiment in the components of the semiconductor device disposed on the substrate 100. Therefore, only the components of the semiconductor device disposed on the substrate 100 will be described below.

[0180] The semiconductor package of the fourth embodiment may include a first component 220 disposed on a first connection portion 210 of a substrate 100. The first component 220 may be a semiconductor device, or alternatively, may be an interposer. In addition, when the first component 220 is an interposer, it may be an active interposer, or alternatively, may be a passive interposer.

[0181] In addition, the semiconductor package of the fourth embodiment may include a fifth connection portion 510 disposed on the first component 220. The fifth connection portion 510 may be electrically connected to the first component 220. For example, when the first component 220 is a semiconductor device, the fifth connection portion 510 may be disposed on a terminal of the semiconductor device. For example, when the first component 220 is an interposer, the fifth connection portion 510 may be disposed on an electrode of the interposer.

[0182] In addition, the semiconductor package of the fourth embodiment may include a second component 520 disposed on the fifth connection portion 510. The second component 520 may be a semiconductor device. For example, the second component 520 may be a CPU or a GPU, but is not limited thereto. The second component 520 includes a terminal 525. In addition, the terminal 525 of the second component 520 may be electrically connected to the first component 220 through the fifth connection portion 510. In this way, the second component 520 may be electrically connected to the substrate 100.

[0183] For example, the semiconductor package of the fourth embodiment may have a plurality of semiconductor devices 220 and 520 disposed in a stacked structure on a substrate 100. In addition, the semiconductor package of the fourth embodiment may electrically connect the substrate 100 and the semiconductor device 520 through an active or passive interposer 220.

[0184] Furthermore, the molded part 230 of the fourth embodiment may mold the first component 220 and the second component 520 .

[0185] In addition, the cover member 300 of the fourth embodiment may cover the side and upper regions of the first component 220 and the second component 520. For example, the first component 220 and the second component 520 may be disposed in a cavity space defining a receiving space of the cover member 300.

[0186] In addition, the second adhesive member 410 of the fourth embodiment may be provided on the upper surface of the second part 520 .

[0187] The structure of the opening area of ​​the first protective layer 140 , the arrangement structure of the first adhesive member 240 , and the arrangement structure of the cover member 300 will be described in more detail below.

[0188] Figure 5 is a plan view showing a first protective layer of the first embodiment, Figure 6 is a plan view showing a first protective layer of a second embodiment, Figure 7 is a plan view showing a first protective layer of a third embodiment, Figure 8 is a plan view showing a first protective layer of a fourth embodiment, Fig. 9 is a diagram showing a state in which a first bonding member is provided on a first protective layer of a first embodiment, Fig.10 is a diagram showing a state in which a first bonding member is provided on a first protective layer of a second embodiment.

[0189] refer to Figure 5 , the first protective layer 140 is disposed on the substrate 100. The first protective layer 140 may include an opening region.

[0190] At this time, the first protective layer 140 may be divided into a plurality of regions. For example, the first protective layer 140 may include a peripheral region 140a adjacent to a peripheral region 140c of the upper surface of the first protective layer 140. In addition, the first protective layer 140 may include an inner region 140b excluding the peripheral region 140c.

[0191] At this time, the periphery 140c may also be referred to as an edge of the upper surface of the first protective layer 140. In addition, the periphery 140c may also be referred to as a corner where the upper surface of the first protective layer 140 and the outer surface of the first protective layer 140 are connected.

[0192] The opening region of the first protection layer 140 includes a first opening 141 and a second opening 142 .

[0193] At this time, in the first embodiment, one first opening 141 may be provided.

[0194] The first opening 141 may be provided in the peripheral region 140a of the first protective layer 140. The first opening 141 may be a through hole penetrating the upper and lower surfaces of the peripheral region 140a of the first protective layer 140. At this time, the first opening 141 may be connected to the outer surface of the first protective layer 140. Therefore, the first opening 141 may be a groove recessed inwardly on the outer surface of the first protective layer 140, or may be a through hole penetrating the upper and lower surfaces of the first protective layer 140.

[0195] The second opening 142 may be provided in plurality. The number of the second openings 142 may correspond to the number of the terminals 225 of the semiconductor device 220 provided on the substrate 100 or the number of the first electrode patterns 120a-1, but is not limited thereto. For example, the number of the second openings 142 may be less than the number of the first electrode patterns 120a-1. In this case, at least one of the plurality of second openings may open a plurality of first electrode patterns 120a-1 at the same time.

[0196] In the first embodiment, the first opening 141 may be provided in a region spaced apart from the corner region in the peripheral region 140 a of the first protective layer 140 .

[0197] refer to Figure 6 In the second embodiment, a plurality of first openings 141 may be provided.

[0198] For example, the first protection layer 140 of the second embodiment may include a plurality of first openings 141 disposed in the peripheral region 140 a and spaced apart from each other.

[0199] For example, the plurality of first openings 141 may include 1-1st to 1-4th openings 141-1, 141-2, 141-3, 141-4 spaced apart from each other in the peripheral region 140a. The 1-1st to 1-4th openings 141-1, 141-2, 141-3, 141-4 may be spaced apart from each other along the peripheral direction of the upper surface of the first protective layer 140. In addition, each of the 1-1st to 1-4th openings 141-1, 141-2, 141-3, 141-4 may be connected to the outer side surface of the first protective layer 140.

[0200] refer to Figure 7 The first protective layer 140 of the third embodiment may have one first opening 141 a. At this time, the first opening 141 of the first protective layer 140 is disposed at a position spaced apart from a corner region of the upper surface of the first protective layer 140 .

[0201] On the contrary, the first opening 141a of the first protective layer 140 of the third embodiment may be disposed in a corner region. Therefore, the periphery of the outer side surface of the first protective layer 140 constituting the first opening 141a may include a curved portion. For example, the planar shape of the first opening 141a of the third embodiment may be an "L" shape having a curved portion, but is not limited thereto.

[0202] refer to Figure 8 , the first opening 141a of the fourth embodiment may be composed of multiple parts.

[0203] For example, the first protection layer 140 of the fourth embodiment may include a plurality of first openings 141 a disposed in the peripheral region 140 a and spaced apart from each other.

[0204] For example, the plurality of first openings 141a may include 1-1st to 1-4th openings 141-1a, 141-2a, 141-3a, 141-4a spaced apart from each other in the peripheral region 140a. The 1-1st to 1-4th openings 141-1a, 141-2a, 141-3a, 141-4a may be spaced apart from each other along the peripheral direction of the upper surface of the first protective layer 140. In addition, each of the 1-1st to 1-4th openings 141-1a, 141-2a, 141-3a, and 141-4a may be connected to the outer side surface of the first protective layer 140. The 1-1st to 1-4th openings 141-1a, 141-2a, 141-3a, 141-4a may be disposed at different corner regions of the peripheral region 140a of the upper surface of the first protective layer 140.

[0205] Meanwhile, the first opening of the first protection layer 140 of the embodiment may also be configured as a combination of structures of the first openings of at least two embodiments from the first embodiment to the fourth embodiment.

[0206] At the same time, reference Fig. 9 , the first adhesive member 240 is disposed in the peripheral region 140 a of the first protective layer 140 . In addition, the first connection portion 210 may be disposed in the second opening 142 of the first protective layer 140 .

[0207] The first adhesive member 240 may be disposed in the peripheral region 140a of the first protective layer 140 along the peripheral direction of the upper surface of the first protective layer 140. At this time, the first adhesive member 240 may have an open loop shape. For example, the first adhesive member 240 may be partially disposed in the peripheral region 140a. For example, the peripheral region 140a may include a non-disposed region in which the first adhesive member 240 is not disposed along the peripheral direction. The non-disposed region may represent a separation region between one end 241e1 and the other end 241e2 of the first adhesive member 240 having an open loop shape. For example, the non-disposed region may represent an area vertically overlapping with the second lower surface of the side plate portion 310 of the cover member 300. The second lower surface of the side plate portion 310 of the cover member 300 may represent a portion of the lower surface of the side plate portion 310 that does not vertically overlap with the adhesive member 240 and does not contact the first adhesive member 240.

[0208] In addition, the first opening 141 of the first protective layer 140 may vertically overlap with the non-disposition region. At this time, the non-disposition region may partially vertically overlap with the first opening 141 of the first protective layer 140.

[0209] Specifically, a portion of the non-disposition region may be provided with the first opening 141 , and a portion of the remaining region may not be provided with the first opening 141 .

[0210] Specifically, the first opening 141 of the embodiment may have a first width W1. At this time, the first width W1 may represent the width in the circumferential direction of the upper surface of the first protection layer 140. For example, the first width W1 may represent the length of the first opening 141 in the horizontal direction.

[0211] In addition, the non-setting area or separation area of ​​the embodiment may have a second width W2 greater than the first width W1. The second width W2 may represent the width in the peripheral direction of the upper surface of the first protective layer 140. For example, the second width W2 may represent the separation distance of the separation area. For example, the second width W2 may represent the separation distance between one end 240e1 and the other end 240e2 of the first adhesive member 240.

[0212] In an embodiment, the first width W1 is greater than the second width W2. In this way, the embodiment can guide the exhaust path of the gas present in the cavity space to the first opening 141. In this way, the embodiment can further improve the exhaust characteristics of the gas.

[0213] In addition, in the embodiment, the first width W1 is greater than the second width W2, and in this way, the first adhesive member 240 disposed on the first protective layer 140 can be prevented from overflowing to the first opening 141. Therefore, the embodiment can further improve the gas exhaust characteristics without affecting the gas exhaust characteristics.

[0214] At the same time, reference Fig.10 , the first opening 141 can be provided in plurality.

[0215] For example, the first openings 141 may include 1-1 to 1-4 openings 141 - 1 , 141 - 2 , 141 - 3 , and 141 - 4 spaced apart from each other in the peripheral region 140 a and disposed along a peripheral direction of the upper surface of the first protective layer 140 .

[0216] Therefore, the first adhesive member 240 may include a plurality of adhesive patterns disposed between the 1-1 to 1-4 openings 141 - 1 , 141 - 2 , 141 - 3 , and 141 - 4 in the circumferential direction.

[0217] For example, the first adhesive member 240 may include a first adhesive pattern 241 - 1 disposed between the 1-1th opening 141 - 1 and the 1-2th opening 141 - 2 in the circumferential direction.

[0218] For example, the first adhesive member 240 may include a second adhesive pattern 241 - 2 disposed between the 1 - 2 opening 141 - 2 and the 1 - 3 opening 141 - 3 in the circumferential direction.

[0219] For example, the first adhesive member 240 may include a third adhesive pattern 241 - 3 disposed between the 1 - 3 opening 141 - 3 and the 1 - 4 opening 141 - 4 in the circumferential direction.

[0220] For example, the first adhesive member 240 may include a fourth adhesive pattern 241 - 4 disposed between the 1-1th opening 141 - 1 and the 1-4th opening 141 - 4 in the circumferential direction.

[0221] Fig.11 is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Fig.12 It is shown Fig.11 A plan view of a first protective layer of a semiconductor package, Fig.13 The first bonding member is shown to be arranged on Fig.12 Diagram of the state on the first protection layer.

[0222] refer to Figures 11 to 13 The semiconductor package of the present invention is different from the semiconductor package of the first embodiment in that a groove 143 is provided in the first protection layer 140 of the substrate 100. Therefore, only the structure of the groove 143 of the first protection layer 140 will be described below.

[0223] The first protective layer 140 may include a groove 143 disposed in the peripheral region 140a. The groove 143 may have a shape recessed from the upper surface to the lower surface of the first protective layer 140. The groove 143 may be spaced apart from the periphery 140c of the upper plate portion 320 of the first protective layer 140.

[0224] In addition, the groove 143 may be connected to the first opening 141 of the first protective layer 140. In this way, the embodiment allows the first adhesive member 240 to be disposed in the groove 143 while allowing gas to be exhausted through the first opening 141.

[0225] In addition, the embodiment can reduce the thickness of the semiconductor package by the depth of the above-mentioned groove 143. Therefore, the embodiment can miniaturize the semiconductor package.

[0226] The semiconductor package of the embodiment includes a substrate and a protective layer disposed on the substrate. In addition, the protective layer includes a first opening disposed in a peripheral region of an upper surface of the protective layer and passing through the upper surface and the lower surface of the protective layer. In addition, the semiconductor package includes a first adhesive member disposed in a peripheral region of an upper surface of the protective layer and a cover member disposed on the first adhesive member.

[0227] At this time, the first adhesive member may be partially disposed in the peripheral region of the protective layer. Specifically, the first adhesive member may have an open loop shape along the peripheral direction of the upper surface of the protective layer.

[0228] Therefore, the peripheral area includes a setting area where the first adhesive member is set and a non-setting area where the first adhesive member is not set. At this time, the non-setting area vertically overlaps with the first opening.

[0229] In other words, the lower surface of the cover member includes a first lower surface in contact with the first adhesive member and a second lower surface not in contact with the first adhesive member. In addition, the first opening vertically overlaps with the second lower surface of the cover member but does not vertically overlap with the first adhesive member.

[0230] Therefore, the embodiment can not only utilize the non-setting area of ​​the first adhesive member, but also utilize the first opening of the protective layer connected to the non-setting area as a vent. Therefore, the embodiment can easily discharge the gas existing in the cavity space for defining the internal space of the cover member to the outside. Therefore, the embodiment can solve the physical reliability problem and the electrical reliability problem caused by the presence of gas in the cavity space. Therefore, the embodiment can further improve the product reliability of the semiconductor package.

[0231] At the same time, the protective layer of the embodiment includes a groove, which is arranged in the area where the first bonding member is to be arranged and is connected to the first opening. In addition, the first bonding member can be arranged in the groove. In this way, the embodiment can reduce the height of the semiconductor package by the depth of the groove. Therefore, the embodiment can miniaturize the semiconductor package.

[0232] In addition, the embodiment allows the width of the non-setting area of ​​the first bonding member to be greater than the width of the first opening. At this time, each of the width of the first opening and the width of the non-setting area each represents the width in the peripheral direction of the upper surface of the protective layer. Therefore, the embodiment can prevent the first bonding member from overflowing into the first opening. Therefore, the embodiment can further improve the product reliability of the semiconductor package. In addition, the embodiment sets a step between the non-setting area and the first opening so that the gas generated in the cavity space can flow in the direction of the first opening. Therefore, the embodiment can further improve the exhaust characteristics of the gas.

[0233] Figures 14 to 23 are cross-sectional views explaining a method of manufacturing a semiconductor package according to an embodiment in order of processes.

[0234] Below, we will refer to Figures 14 to 23 Describe the process sequence for manufacturing Figure 1 Meanwhile, the semiconductor packages of the second to fifth embodiments can also be manufactured based on the following manufacturing process.

[0235] refer to Fig.14 , the embodiment prepares a material as a basis for manufacturing the substrate 100. For example, the embodiment prepares a carrier for manufacturing the substrate 100 of the ETS structure. The carrier includes a carrier insulating layer CB1 and a carrier metal layer CB2 disposed on at least one surface of the carrier insulating layer CB1. Fig.14 It is shown that the carrier metal layer CB2 is only disposed on the lower surface of the carrier insulating layer CB1, but the embodiment is not limited thereto. For example, the carrier metal layer CB2 may also be disposed on the upper surface of the carrier insulating layer CB1. Therefore, the embodiment may simultaneously perform a process of manufacturing a plurality of substrates 100 using the carrier metal layers CB2 disposed on both sides of the carrier insulating layer CB1.

[0236] Next, refer to Fig.15 , the embodiment uses the carrier metal layer CB2 disposed on at least one surface of the carrier insulating layer CB1 as a seed layer, and forms a portion of the electrode layer 120 of the substrate 100 on the lower surface of the carrier metal layer CB2. For example, the embodiment performs a process of forming the first electrode layer 120a on the lower surface of the carrier metal layer CB2, and the first electrode layer 120a is an electrode layer disposed on the uppermost side of the substrate 100. At this time, the first electrode layer 120a may include a first electrode pattern 120a-1 and a second electrode pattern 120a-2.

[0237] Next, refer to Fig.16 In an embodiment, when forming the first electrode layer 120 a , a process of laminating the insulating layer 110 , a process of forming a through hole, a process of forming a through electrode, and a process of forming an electrode layer are performed at least once to form the substrate 100 .

[0238] Next, refer to Fig.17 , the embodiment may perform a process of removing the carrier. For example, the embodiment may perform a process of separating the carrier insulating layer CB1 and the carrier metal layer CB2. Next, the embodiment may perform a process of removing the carrier metal layer CB2 disposed on the substrate 100 by etching.

[0239] Next, refer to Fig.18 , embodiments may perform a process of forming a first protective layer 140 on the substrate 100 .

[0240] To this end, the embodiment may apply an insulating material covering the entire upper portion of the substrate 100 and remove the applied insulating material by exposure and development to perform a process of forming the first opening 141 and the second opening 142 of the first protective layer 140. The first opening 141 may be formed in the peripheral region 140a of the first protective layer 140, and the second opening 142 may be formed in the inner region 140b of the first protective layer 140.

[0241] In this regard, embodiments may perform a process of forming the second protection layer 150 at a lower portion of the substrate 100 .

[0242] Next, refer to Fig.19 , embodiments may perform a process of disposing the first connection portion 210 on the first electrode pattern 120 a - 1 exposed through the second opening 142 of the first protective layer 140 .

[0243] Next, refer to Fig. 20, the embodiment may perform a process of mounting the semiconductor device 220 on the first connection portion 210. The terminal 225 of the semiconductor device 220 may be electrically connected to the first electrode pattern 120a-1 through the first connection portion 210. Thereafter, the embodiment may perform a process of forming a molding member 230 molding the semiconductor device 220 and the first connection portion 210.

[0244] Next, refer to Fig.21 , the embodiment may perform a process of applying the first adhesive member 240 in the peripheral area of ​​the upper surface of the first protective layer 140. At this time, the first adhesive member 240 is arranged in an open loop shape along the peripheral direction of the upper surface of the first protective layer 140. For example, the peripheral area 140a of the first protective layer 140 includes a non-set area where the first adhesive member 240 is not set. The non-set area may be a separation area where one end of the first adhesive member 240 is separated from the other end. In addition, the non-set area may overlap vertically with the first opening 141 provided in the first protective layer 140. Next, the embodiment may perform a process of applying the second adhesive member 410 on the upper surface of the semiconductor device 220.

[0245] Next, refer to Fig. 22 , the embodiment may perform a process of attaching the cover member 300 to the substrate 100 using the first adhesive member 240 and the second adhesive member 410. Then, after attaching the cover member 300, a heating process of curing the first adhesive member 240 may be performed. At this time, gas may be generated during the heating process, and the generated gas may be discharged to the outside of the cover member 300 through the non-disposition area of ​​the first adhesive member 240 and the first opening 141 of the first protective layer 140.

[0246] Next, refer to Fig.23 , the embodiment may perform a process of applying the third adhesive member 420 to the upper surface of the upper plate part 320 of the cover member 300. Thereafter, the embodiment may perform a process of attaching the heat dissipation plate 430 on the third adhesive member 420.

[0247] On the other hand, when the circuit board having the above-mentioned features of the present invention is used for IT equipment or household appliances such as smart phones, server computers, televisions, etc., functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or contaminants, or alternatively, it can solve the problems of leakage current, electrical short circuit between terminals, and electrical open circuit of terminals provided to semiconductor chips. In addition, when the function of signal transmission is dominant, the noise problem can be solved. In this way, the circuit board having the above-mentioned features of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and the circuit board applying the present invention can achieve functional unification or technical interlocking with each other.

[0248] When the circuit board having the characteristics of the present invention described above is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or alternatively, the safety of the transportation device can be further improved by safely protecting the semiconductor chip controlling the transportation device from external interference and solving the problem of leakage current or electrical short circuit between terminals or electrical open circuit of terminals provided to the semiconductor chip. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional integrity or technical interlocking with each other.

[0249] The features, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, a person skilled in the art to which the embodiments belong may even combine or modify the features, structures and effects shown in each embodiment relative to other embodiments. It should therefore be understood that the contents related to such combinations and such modifications are included within the scope of the embodiments.

[0250] The above description focuses on the embodiments, but it is only illustrative and does not limit the embodiments. It will be appreciated by those skilled in the art that various modifications and applications not described above may be made without departing from the basic features of the embodiments. For example, each component specifically represented in the embodiments may be modified and implemented. In addition, it should be understood that the differences associated with these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A semiconductor package, comprising: substrate; a protective layer disposed on the substrate; a first adhesive member disposed on the protective layer, the first adhesive member having an open loop shape along a peripheral direction of an upper surface of the protective layer; as well as a cover member disposed on the first bonding member, The lower surface of the cover member comprises: a first lower surface in contact with the first bonding member, and a second lower surface not in contact with the first bonding member, The protection layer includes a first opening, the first opening vertically overlaps with the second lower surface of the cover member and does not vertically overlap with the first adhesive member. 2 . The semiconductor package according to claim 1 , wherein at least a portion of the second lower surface of the cover member does not vertically overlap with the first opening.

3. The semiconductor package according to claim 1 , wherein the upper surface of the protection layer includes a peripheral area adjacent to a periphery of the upper surface of the protection layer, The first bonding member is partially disposed in the peripheral region along the peripheral direction. 4 . The semiconductor package according to claim 3 , wherein the first opening vertically overlaps a region of the peripheral region where the first adhesive member is not disposed. 5 . The semiconductor package according to claim 4 , wherein a width of a region where the first adhesive member is not provided in the peripheral direction is larger than a width of the first opening in the peripheral direction.

6. The semiconductor package according to any one of claims 3 to 5, wherein a plurality of first openings are provided spaced apart from each other along the peripheral direction, The first bonding member includes a plurality of first bonding patterns arranged between the plurality of first openings along the peripheral direction. 7 . The semiconductor package according to claim 3 , wherein the first opening is connected to an outer side surface of the protection layer.

8. The semiconductor package according to claim 7, wherein the protective layer comprises a groove that is recessed from an upper surface of the protective layer toward a lower surface of the protective layer and vertically overlaps with the first adhesive member, The first bonding member is disposed in the groove. 9 . The semiconductor package according to claim 8 , wherein the groove is spaced apart from an outer side surface of the protection layer and connected to the first opening.

10. The semiconductor package according to any one of claims 3 to 5, wherein the substrate comprises: Insulation layer; as well as A first electrode layer is provided on the insulating layer, The protection layer includes a second opening that passes through the upper surface and the lower surface of the protection layer and vertically overlaps with the first electrode layer.

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