Diode in nanosheet technology

Abstract

The nanosheet diode includes a bookend structure and a center structure. The bookend includes a first semiconductor doped as one of an anode and a cathode of a diode, and includes a left block, a right block, and a first stack of spaced apart nanosheets horizontally connecting the left block and the right block. The central structure includes a second semiconductor doped as the other of the anode and cathode of the diode, and includes a front block, a rear block, and a second stack of nanosheets interdigitally interleaved into a space between the spaced apart first stack of nanosheets and horizontally connecting the front block and the rear block. The bookend structure directly contacts a top surface, a bottom surface, and an end surface of the second stack of nanosheets of the central structure.

Description

Background Art

[0001] The present invention relates to the electrical, electronic and computer fields, and more particularly to the fabrication of nanosheet semiconductor devices.

[0002] Previously, diodes have been fabricated together with transistors in nanosheet technology by depositing a stack of alternating layers of two materials on a substrate and defining a field effect transistor (FET) and a diode region and depositing a mask. The mask covers only the FET region, leaving the diode region uncovered. The prior art process also includes doping the material in the diode region with a dopant, implanting the epitaxial material with another dopant to form a PN junction, and stripping the mask from the structure. The prior art process also includes forming a metal gate conductor on the FET region, and depositing metal on the structure to produce a terminal. In the diode region, according to the prior art process, a dielectric spacer remains embedded between the p-doped semiconductor structure and the n-doped semiconductor structure. Summary of the invention

[0003] The principles of the present invention provide techniques for forming diodes in nanosheet technology.

[0004] According to one aspect of the present invention, an exemplary semiconductor structure includes a nanosheet diode having an anode and a cathode. The nanosheet diode includes: a bookend structure, which is doped as one of the anode and cathode of the diode and includes a left block, a right block, and a first stack of spaced nanosheets horizontally connecting the left block and the right block; and a central structure, which is doped as the other of the anode and cathode of the diode and includes a front block, a rear block, and a second stack of nanosheets, the second stack of nanosheets being staggered into the space between the first stack of spaced nanosheets and horizontally connecting the front block and the rear block. The bookend structure directly contacts the top surface, the bottom surface, and the end surface of the second stack of nanosheets of the central structure.

[0005] According to another aspect, an exemplary method for forming a nanosheet diode includes: forming a bookend structure including a first semiconductor doped as one of an anode and a cathode of a diode, and including a left block, a right block, and a first stack of spaced-apart nanosheets horizontally connecting the left block and the right block; and forming a central structure including a second semiconductor doped as the other of an anode and a cathode of a diode, and including a front block, a rear block, and a second stack of nanosheets, the second stack of nanosheets being cross-staggered into the space between the first stack of spaced-apart nanosheets and horizontally connecting the front block and the rear block. The bookend structure directly contacts the top surface, the bottom surface, and the end surface of the second stack of nanosheets of the central structure.

[0006] In view of the foregoing, the technology of the present invention can provide substantially beneficial technical effects. For example, one or more embodiments provide a diode formed with nanosheet technology that has enhanced conductivity relative to previous diodes of similar scale and technology. Some embodiments may not have this / these potential advantages, and this / these potential advantages are not necessarily required for all embodiments. These and other features and advantages of the present invention will become apparent from the detailed description of illustrative embodiments of the present invention read below in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 4 A nanosheet semiconductor structure including a diode according to an exemplary embodiment is schematically depicted.

[0008] Figure 5 The flowchart depicts the process for manufacturing Figure 1 Steps in an exemplary method of illustrating a semiconductor structure.

[0009] Figures 6 to 9 The schematic diagram depicts Figure 5 Preliminary structure in the exemplary method shown.

[0010] Figure 10 to Figure 45 The schematic diagram shows the Figure 5 The exemplary method steps shown result in intermediate structures. DETAILED DESCRIPTION

[0011] Figures 1 to 4 A nanosheet semiconductor structure 100 including a diode 102 and a transistor 104 is schematically depicted. Figure 2 , Figure 3 and Figure 4 Along Figure 1 2, 3 and 4 in FIG. The diode 102 includes a bookend structure 106 and a center structure 108. Either the bookend structure 106 or the center structure 108 can be doped as an anode of the diode 102, while the other of the two structures can be doped as a cathode. In one or more non-limiting exemplary embodiments, the bookend structure 106 and the center structure 108 both include silicon; in some cases, they both consist essentially of silicon. In one or more non-limiting exemplary embodiments, the anode is doped with a p-dopant, and in some cases, the p-dopant is selected from a list consisting of boron, aluminum, gallium, and indium. In one or more non-limiting exemplary embodiments, the cathode is doped with an n-type dopant, and in some cases, the n-type dopant is selected from a list consisting of antimony, arsenic, and phosphorus.

[0012] The bookend structure 106 includes a left block 110 and a right block 112, wherein a nanosheet 114 extends horizontally between and connects the left block 110 and the right block 112. In the present disclosure, terms such as "left", "right", "front", "rear", "horizontal", and "vertical" are relative to the drawings of the present disclosure, and do not require that the actual product must be oriented or configured such that a particular component must be on the "left" or "right", etc. In one or more embodiments, a bottom dielectric isolation 116 is provided below the left block 110 and the right block 112 to electrically separate them from the substrate 118. In one or more embodiments, the substrate 118 also includes silicon; in some cases, it is substantially composed of silicon.

[0013] Top contacts 120 electrically connect left and right blocks 110 and 112 to back end of line (BEOL) layers of semiconductor device 100. BEOL layers are not shown to avoid clutter; BEOL layers and electrical connections to forward or reverse biased diodes are within the knowledge of those skilled in the art.

[0014] The central structure 108 includes a front block 122, a rear block 124, and a horizontal nanosheet 126 extending horizontally between and connecting the front block and the rear block. The nanosheet 126 is interlaced with the nanosheet 114 in a generally cross-shaped manner. The central structure 108 also includes a top block 128. The top contact 130 electrically connects the top block to the BEOL layer (not shown) of the semiconductor device 100.

[0015] The interlayer dielectric 132 , the gate cut 134 , and the shallow trench isolation 136 electrically separate the diode 102 from the gate stack 138 of an adjacent transistor (not shown in detail).

[0016] Transistor 104 includes substrate 118, source / drain structure 714, gate stack 4302, and source / drain contacts 4304. Transistor 104 itself is conventional and is only described further as it relates to fabrication processes that affect both diode 102 and transistor 104. Elements 702, 706, 708 are discussed below.

[0017] Figure 5 The flowchart shows the process for manufacturing Figure 1 Steps in an exemplary method 500 of the semiconductor structure 100 shown. Semiconductor device manufacturing includes various steps of device patterning process. For example, the manufacture of semiconductor chips can start with multiple CAD (computer-aided design) generated device patterns, which will be replicated on a substrate. The replication process can involve the use of various exposure techniques and various subtractive (etching) and / or additive (deposition) material processing procedures.

[0018] In step 502 of method 500, a preliminary structure 600 is obtained, such as Figures 6 to 9 shown. Figure 7 , Figure 8 and Fig. 9 Along Figure 6 7, 8 and 9 in FIG. 6. Structure 600 includes left block 110 and right block 112, bottom dielectric isolation 116, substrate 118, template nanosheet 702, sacrificial nanosheet 704, inner spacer 706, gate spacer 708, dummy gate 710 and interlayer dielectric (ILD) 712. Structure 600 is shown after epitaxial growth of source / drain structure 714 in transistor 104, formation of dummy gate 710, deposition of ILD 712 and chemical mechanical planarization.

[0019] At 504 (reference Figures 10 to 13 , respectively along Fig.10 Sight lines 11, 12 and 13 are captured Fig.11 , Fig.12 and Fig.13 ), depositing a liner 1102 (e.g., silicon carbide) and forming a gate cut 134 to form an intermediate structure 1000. Those skilled in the art use many techniques to remove material at various stages of creating a semiconductor structure (such as step 504 of making a gate cut). As used herein, these processes are generally referred to as "etching". For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, which are all known techniques for removing selective materials when forming semiconductor structures. Standard Clean 1 (SC1) contains a strong base (typically ammonium hydroxide) and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. Those skilled in the art understand the techniques and applications of etching well, and therefore, a more detailed description of these processes is not given herein.

[0020] As an exemplary subtractive process, in a photolithography process, a layer of photoresist material may first be applied on top of a substrate and then selectively exposed according to a predetermined one or more device patterns. Portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beams, X-rays, etc.) may undergo some changes in its solubility to certain solutions. The photoresist may then be developed in a developer solution to remove un-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer to produce a photoresist pattern or photomask. The photoresist pattern or photomask may then be copied or transferred to the substrate below the photoresist pattern.

[0021] At 506 (see Figures 14 to 17 ; Fig.15 , Fig.16 and Fig.17 Along Fig.14 15 , 16 and 17 in FIG), the gate cut 134 is filled with a dielectric 1702 and chemical mechanical planarization (CMP) is performed to form an intermediate structure 1400 .

[0022] In 508 (reference Figures 18 to 21 , Fig.19 , Fig. 20 and Fig.21 Along Fig.18 19 , 20 , and 21 in the drawings), depositing and patterning a mask layer, such as an organic planarization layer (OPL) 1902 exposing a region 2004 where the diode 100 will be formed, thereby forming an intermediate structure 1800 .

[0023] At 510 (see Figure 22 to Figure 25 , Fig.23 , Fig.24 and Fig.25 Along Fig. 22 23, 24 and 25 in FIG), the dummy gate 710 is removed from the diode precursor region 2004, and the sacrificial nanosheet 704 is released from the diode precursor region 2004, thereby forming an intermediate structure 2200 having a gap 2502.

[0024] At 512 (see Figure 26 to Figure 29 , Fig. 27 , Fig.28 and Fig.29 Along Fig.26 27, 28 and 29 in FIG), the inner spacer 706 and the gate spacer 708 are removed from the diode precursor region 2004, thereby forming the intermediate structure 2600. In one or more embodiments, if the liner 1102 is a different material than the inner spacer and gate spacer materials, the removal of the spacers can be more easily achieved. For example, if the spacers 706, 708 are nitride-based, the spacers can be selectively wet etched relative to the liner 1102 if the liner 1102 is carbide-based (e.g., SiC or SiOC), and vice versa.

[0025] At 514 (see Figure 30 to Figure 33 ; Fig.31 , Fig.32 and Fig.33 Along Fig.30 31, 32 and 33 in FIG), the template nanosheet 702 is trimmed only within the diode precursor region 2004, thereby forming an intermediate structure 3000 including a trimmed nanosheet 3202. Trimming can be accomplished by various etching processes; in one or more embodiments, an isotropic process is used, such as wet etching using chemicals such as a bath of acetic acid (CH3COOH), hydrogen peroxide (H2O2) and hydrofluoric acid (HF).

[0026] At 516 (reference Figure 34 to Figure 37 , Fig.35 , Fig.36 and Fig.37 Along Fig.34 35, 36 and 37 in FIG), epitaxially grow (thicken) trimmed nanosheet 3202 to form intermediate structure 3400, which includes bookend structure 106 with nanosheet 114, which will become part of diode 102. Nanosheet 114 can be doped in situ or doped by diffusion. At 517, after doping nanosheet 114, central structure 108 including nanosheet 126 is epitaxially grown and doped.

[0027] Various structures described herein, such as bookend structures and center structures including left, right, front and back blocks and nanosheet stacks, can be grown epitaxially. As used herein, "epitaxy" or "epitaxially growth" refers to the process of forming a single crystal or large-grained polycrystalline material layer on an existing material with similar crystalline properties. One feature of epitaxy is that the process causes the crystal structure of the existing substrate or seed layer (including any defects therein) to reproduce in the epitaxially grown material. Epitaxial growth can include heteroepitaxiality (i.e., growing a material with a different component from its underlying layer) or homoepitaxiality (i.e., growing a material including the same component as its underlying layer). Heteroepitaxy can introduce strain in the epitaxially grown material because its crystal structure may be distorted to match the crystal structure of the underlying layer. In some applications, such strains may be desired. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material can have the same crystalline properties as the deposition surface on which it may be formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface may exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process may be selective for formation on semiconductor surfaces and may not deposit the material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0028] Many different precursors can be used for epitaxial deposition of in-situ doped semiconductor materials. In some embodiments, the gas source for depositing the epitaxially formed in-situ doped semiconductor material can include silicon (Si) deposited from silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, disilane, and combinations thereof. In other examples, when the in-situ doped semiconductor material includes germanium, the germanium gas source can be selected from germanium, digermane, halogenated germanes, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Examples of other epitaxial growth processes that can be used to grow the semiconductor layers described herein include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE).

[0029] "In situ" refers to the introduction of dopants that determine the conductivity type of the doped layer during a process step (e.g., epitaxial deposition) that forms the doped layer. The terms "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), wherein the grown semiconductor material (crystalline overlying layer) has substantially the same crystalline properties as the semiconductor material (seed material) of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled, and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface so that the deposited atoms orient themselves to the crystalline arrangement of the atoms of the deposition surface. Thus, the epitaxially grown semiconductor material has substantially the same crystalline properties as the deposition surface of the material on which the epitaxial growth is formed.

[0030] As used herein, the term "conductivity type" refers to a p-type or n-type dopant region. As further used herein, "p-type" refers to the addition of impurities to an intrinsic semiconductor that creates a deficiency in valence electrons. In a silicon-containing substrate, examples of p-type dopants (i.e., impurities) include, but are not limited to: boron, aluminum, gallium, and indium. As used herein, "n-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. Examples of n-type dopants (i.e., impurities in a silicon-containing substrate) include, but are not limited to, antimony, arsenic, and phosphorus.

[0031] In one or more embodiments, the nanosheet 114 is doped in unison with the left block 110 and the right block 112 (as well as the source / drain structure 714 of the transistor 104), while the center structure 108 is doped inversely. Thus, in such embodiments, if the transistor 104 is an nFET, the bookend structure 106 will be doped as a cathode and the center structure 108 will be doped as an anode; on the other hand, if the transistor 104 is a pFET, the bookend structure 106 will be doped as an anode and the center structure 108 will be doped as a cathode. Note that the doping of the diode 102 need not be linked to the doping of the transistor 104, and in one or more embodiments, there may be a pFET transistor 104 with a bookend structure 106 doped as a cathode or an nFET transistor 104 with a bookend structure 106 doped as an anode.

[0032] At 518 (ref. Figures 38 to 41 ; Fig.39 , Fig.40 and Fig.41 Along Fig.38 39, 40 and 41 in the figure), filled with an interlayer dielectric 132 to form an intermediate structure 3800.

[0033] At 520 (see Figure 42 to Figure 45 ; Fig.43 , Fig.44 and Fig.45 Along Fig.42 43, 44 and 45 in the figure), replacing the gate stack 4302 of the sacrificial nanosheet 704 and the dummy gate 710 in the transistor 104, and depositing a self-aligned gate dielectric cap 4304 to form the intermediate structure 4200. The gate stack in both the nFET and pFET structures (in embodiments with two types of regions) includes a work function material (WFM) layer. Non-limiting examples of suitable work function (gate) metals include p-type work function materials and n-type work function materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel and conductive metal nitrides (e.g., TiN, WN) or any combination thereof. N-type work function materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide and aluminum carbide), aluminides or any combination thereof.

[0034] The work function material can be deposited by a suitable deposition process, such as ALD, CVD, PECVD, PVD, electroplating, and thermal or electron beam evaporation. The pinching off of the work function material between the semiconductor fins is substantially avoided during deposition. The WFM layer is removed from one of the nFET and pFET regions in the structure including two types of regions while protecting the other region. SC1 etching, SC2 etching or other suitable etching processes can be used to remove the selected portion of the originally deposited WFM layer. A new WFM layer suitable for the region is then deposited. The device formed in the nFET region will accordingly include a WFM layer (gate electrode) having a first component, while the device in the pFET region will include a WFM layer having a second component. For example, the WFM used in the nFET region can be a Ti, Al, TiAl, TiAlC or TiAlC layer or a metal stack, such as TiN / TiAl / TiN, TiN / TiAlC / TiN, TiN / TaAlC / TiN or any combination of aluminum alloys and TiN layers. The WFM layer used in the pFET region can be, for example, a TiN, TiC, TaN or tungsten (W) layer. The threshold voltage (Vt) of nFET devices is sensitive to the thickness of the work function material such as titanium nitride (TiN).

[0035] At 522, the contacts 120, 130 are etched and formed to complete the semiconductor structure 100 (refer to Figures 1 to 4 ). The contact material may, for example, alternatively include tantalum (Ta), aluminum (Al), platinum (Pt), gold (Au), titanium (Ti), palladium (Pd), or any combination thereof. The contact material may be deposited by, for example, CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering. A planarization process such as CMP is performed to remove any conductive material (capping layer) from the top surface of the structure.

[0036] In view of the discussion thus far, and with reference to the accompanying drawings, it should be understood that, in general, an exemplary semiconductor structure 100 according to one aspect of the present invention includes a nanosheet diode 102 having an anode and a cathode. The nanosheet diode includes: a bookend structure 106, which is doped as one of the anode or cathode of the diode, and includes a left block 110, a right block 112, and a first stack of spaced-apart nanosheets 114 horizontally connecting the left and right blocks. The nanosheet diode also includes a central structure 108, which is doped as the other of the anode or cathode of the diode, and includes a front block 122, a rear block 124, and a second stack of nanosheets 126, which is cross-staggered into the space between the first stack of spaced-apart nanosheets and horizontally connects the front block and the rear block. The bookend structure directly contacts the top surface, the bottom surface, and the end surface of the second stack of nanosheets of the central structure.

[0037] In one or more embodiments, the semiconductor structure further includes a transistor adjacent to the nanosheet diode, and an interlayer dielectric isolating the front block, the rear block, the left block, and the right block from the adjacent transistor.

[0038] In one or more embodiments, the semiconductor structure further includes a top contact 130 electrically connected to the central structure of the nanosheet diode. In one or more embodiments, the semiconductor structure further includes a side contact 120 electrically connected to the bookend structure of the nanosheet diode. In one or more embodiments, the semiconductor structure further includes a bottom dielectric insulator 116 located below at least one of the left block and the right block of the bookend structure. In one or more embodiments, the semiconductor structure further includes a substrate 118 electrically connected to the bookend structure via a second stack of nanosheets. In one or more embodiments, the semiconductor structure further includes a gate cut 134 separating the front block and the rear block from the adjacent gate stack.

[0039] In one or more embodiments, the bookend structures and the center structure are both composed essentially of silicon. In one or more embodiments, the anode is doped with a p-dopant selected from the list consisting of boron, aluminum, gallium, and indium. In one or more embodiments, the cathode is doped with an n-type dopant selected from the list consisting of antimony, arsenic, and phosphorus. In one or more embodiments, the second semiconductor is the same as the first semiconductor.

[0040] According to another aspect, an exemplary method for forming a nanosheet diode includes: forming a bookend structure including a first semiconductor doped as one of an anode or cathode of a diode, and including a left block, a right block, and a first stack of spaced-apart nanosheets horizontally connecting the left block and the right block; and forming a central structure including a second semiconductor doped as the other of an anode or cathode of a diode, and including a front block, a rear block, and a second stack of nanosheets, the second stack of nanosheets being cross-staggered into the space between the first stack of spaced-apart nanosheets and horizontally connecting the front block and the rear block. The bookend structure directly contacts the top surface, the bottom surface, and the end surface of the second stack of nanosheets of the central structure.

[0041] In one or more embodiments, forming the bookend structure includes, at 514, trimming an undoped template nanosheet that horizontally connects the left block and the right block; at 516, epitaxially regrowing a first stack of nanosheets from the trimmed template nanosheet; and doping the first stack of nanosheets to match the doping of the left block and the right block.

[0042] In one or more embodiments, the method further includes, at 512 , releasing the inner spacer from a location adjacent to the left block and the right block of the bookend structure before trimming the template nanosheet.

[0043] In one or more embodiments, doping the first stack of nanosheets includes in-situ doping. In one or more embodiments, doping the first stack of nanosheets includes diffusion doping.

[0044] In one or more embodiments, forming the central structure includes epitaxially growing the front block, the rear block, and the top block and the second stack of nanosheets from the bookend structure as a seed at 517. In one or more embodiments, forming the central structure includes in-situ doping the central structure opposite the bookend structure. In one or more embodiments, forming the central structure includes diffusion doping the central structure opposite the bookend structure.

[0045] In one or more embodiments, the second semiconductor is the same as the first semiconductor.

[0046] Although the entire manufacturing method and the structure formed thereby are novel, certain individual processing steps required to implement the method can utilize conventional semiconductor manufacturing techniques and conventional semiconductor manufacturing tools. In view of the teachings herein, these techniques and tools will be familiar to those of ordinary skill in the relevant art. In addition, one or more processing steps and tool processing for manufacturing semiconductor devices are also described in many readily available publications, including, for example: James D. Plummer et al., Silicon VLSI Technology: Foundations, Practice and Modeling, 1st edition, Princeton Press (Prentice Hall), 2001; PH Holloway et al., Compound Semiconductor Handbook: Growth, Processing, Characterization and Devices, 1st edition, Cambridge University Press, 2008; all of which are incorporated herein by reference. It is emphasized that although some individual processing steps are described herein, those steps are merely illustrative, and those skilled in the art may be familiar with several equally suitable alternatives that will apply.

[0047] It should be understood that the various layers and / or regions shown in the drawings may not be drawn to scale. In addition, for ease of explanation, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. This does not mean that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit device.

[0048] The description of various embodiments of the present invention has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising a nanosheet diode having an anode and a cathode, wherein the nanosheet diode comprises: a bookend structure including a first semiconductor doped as one of an anode and a cathode of a diode, and including a left block, a right block, and a first stack of spaced-apart nanosheets horizontally connecting the left block and the right block; and a central structure including a second semiconductor doped as the other of an anode and a cathode of a diode and including a front block, a rear block, and a second stack of nanosheets cross-staggered into spaces between the first stacks of spaced-apart nanosheets and horizontally connecting the front block and the rear block; wherein the bookend structures directly contact top, bottom and end surfaces of the second stack of nanosheets of the central structure.

2. The semiconductor structure according to claim 1, further comprising: a transistor adjacent to the nanosheet diode; and An interlayer dielectric isolating the front block, the rear block, the left block, and the right block from adjacent transistors.

3. The semiconductor structure according to any one of claims 1 or 2, further comprising: A top contact is electrically connected to the central structure of the nanosheet diode.

4. The semiconductor structure according to any one of claims 1 to 3, further comprising: A side contact is electrically connected to the bookend structure of the nanosheet diode.

5. The semiconductor structure according to any one of claims 1 to 4, further comprising: A bottom dielectric insulator is positioned below at least one of the left block and the right block of the bookend structure.

6. The semiconductor structure according to any one of claims 1 to 5, further comprising: A substrate is electrically connected to the bookend structure via the second stack of nanosheets.

7. The semiconductor structure according to any one of claims 1 to 6, further comprising: A gate cut separates the front block and the back block from an adjacent gate stack.

8. The semiconductor structure according to any one of claims 1 to 7, wherein: The bookend structures and the central structure are both composed essentially of silicon.

9. The semiconductor structure of claim 8, wherein the anode is doped with a p-type dopant selected from the list consisting of boron, aluminum, gallium, and indium.

10. The semiconductor structure according to any one of claims 8 or 9, wherein: The cathode is doped with an n-type dopant selected from the list consisting of antimony, arsenic, and phosphorus.

11. The semiconductor structure according to any one of claims 1 to 10, wherein: The second semiconductor is the same as the first semiconductor.

12. A method for manufacturing a nanosheet diode, the method comprising: forming a bookend structure comprising a first semiconductor doped as one of an anode and a cathode of the diode, and the bookend structure comprising a left block, a right block, and a first stack of spaced-apart nanosheets horizontally connecting the left block and the right block; and forming a central structure including a second semiconductor doped as the other of an anode and a cathode of a diode and including a front block, a rear block, and a second stack of nanosheets cross-staggered into spaces between the first stacks of spaced-apart nanosheets and horizontally connecting the front block and the rear block; wherein the bookend structures directly contact top, bottom and end surfaces of the second stack of nanosheets of the central structure.

13. The method according to claim 12, wherein: Forming the bookend structure includes: trimming an undoped template nanosheet horizontally connecting the left block and the right block; epitaxially regrow a first stack of said nanosheets from the trimmed template nanosheet; and The first stack of nanosheets is doped to match the doping of the left and right blocks.

14. The method according to claim 13, further comprising: Before trimming the template nanosheet, internal spacers are released from locations adjacent to the left and right blocks of the bookend structure.

15. The method of any one of claims 12 to 14, wherein doping the first stack of nanosheets comprises in-situ doping.

16. The method of any one of claims 12 to 15, wherein doping the first stack of nanosheets comprises diffusion doping.

17. The method according to any one of claims 12 to 16, wherein: Forming the central structure includes: The front, rear and top blocks and the second stack of nanosheets are epitaxially grown from the bookend structures as seeds.

18. The method according to claim 17, wherein: Forming the central structure includes: The central structure opposite the bookend structures is doped in situ.

19. The method according to any one of claims 17 or 18, wherein: Forming the central structure includes: The central structure opposite the bookend structures is diffusely doped.

20. The method of any one of claims 12-19, wherein the second semiconductor is the same as the first semiconductor.

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