Time division multiplexing triaxial accelerometer reading circuit

Abstract

The invention discloses a time division multiplexing three-axis accelerometer reading circuit, which relates to the field of reading circuits, and comprises a signal conditioning module and an electrostatic force feedback module, and in the Nth working period of the reading circuit, an X-axis acceleration sensor, a Y-axis acceleration sensor and a Z-axis acceleration sensor in a three-axis accelerometer are respectively used as detection axis acceleration sensors to be connected with the signal conditioning module. For any shaft acceleration sensor, when the acceleration sensor is a detection shaft acceleration sensor of the Nth work period, the electrostatic force feedback module provides feedback voltage for the acceleration sensor and samples the feedback voltage; when the acceleration sensor is converted into a non-detection-axis acceleration sensor from the detection-axis acceleration sensor in the Nth work period, the electrostatic force feedback module provides feedback voltage sampled in the Nth work period for the acceleration sensor until the acceleration sensor is the detection-axis acceleration sensor in the (N + 1) th work period, the accelerometer reading circuit has the characteristics of high precision, low power consumption and small circuit area.

Description

Technical Field

[0001] The invention relates to the field of accelerometer readout circuits, in particular to a time-division multiplexed three-axis accelerometer readout circuit. Background Art

[0002] An accelerometer generally consists of two parts, namely the acceleration sensor and its corresponding readout circuit. A high-performance accelerometer is inseparable from a high-performance accelerometer readout circuit. The principle of the acceleration sensor is to convert the acceleration signal into an electrical physical signal, and the readout circuit converts the physical signal representing the acceleration given by the sensor into an analog or digital signal that can be processed by the hardware. Depending on the application scenario, accelerometers can be classified by principle, detection method, and feedback method.

[0003] From the perspective of detection principle, accelerometers can be divided into capacitive, piezoresistive, piezoelectric and resonant types. Among them, the principle of capacitive accelerometer is that the change of acceleration causes the change of capacitance, and the change of acceleration is obtained by detecting the changed capacitance value. It has the advantages of small size, high sensitivity and high precision. Piezoresistive accelerometer detects the acceleration value by detecting the change of resistance value affected by the acceleration. The advantage is strong impact resistance. Piezoelectric accelerometer converts mechanical energy into electrical energy through piezoelectric effect. It has high sensitivity and precision, but is not suitable for low-frequency signal measurement. Resonant accelerometer uses the relationship between the force and frequency of the vibration beam. The change of the resonant frequency is proportional to the acceleration. The acceleration is obtained by detecting the resonant frequency. It has high precision but there is co-frequency interference.

[0004] From the detection method classification, accelerometers can be divided into open-loop detection and closed-loop detection. Open-loop accelerometers are usually highly sensitive, and a small acceleration can saturate the output voltage of the accelerometer, so the range is usually small. The closed-loop accelerometer readout circuit introduces an electrostatic force feedback link, which has a large range and can effectively reduce circuit noise and improve the linearity of the circuit. According to the feedback method classification, it can be divided into digital closed-loop and analog closed-loop. The two feedback methods are similar in principle, but compared with the discrete feedback signal of the digital closed-loop, the continuous feedback signal of the analog closed-loop can make the circuit have higher linearity. In recent years, the research on accelerometers has been developing in the direction of miniaturization, low power consumption, and high precision. Capacitive closed-loop accelerometers have become an important direction of accelerometer research due to their relatively simple structure, easy integration, low power consumption, high sensitivity, high linearity and high dynamic range.

[0005] Commonly used accelerometers include three-axis accelerometers, which usually use a closed-loop readout circuit for three-axis parallel measurement, that is, by connecting three identical single-axis readout circuit systems to the three-axis acceleration sensors, the three-axis acceleration can be read out. However, since the readout circuit of a large-range capacitive accelerometer needs to add a feedback stage to ensure the high linearity and high precision of the readout circuit for detecting acceleration, the readout circuit of each capacitive accelerometer will occupy a large area on the chip. To realize a closed-loop readout circuit for three-axis parallel measurement, the required on-chip area is also correspondingly large.

[0006] Therefore, in order to meet the design requirements of miniaturization, traditional three-axis accelerometers usually adopt open-loop detection to ensure that the three-axis acceleration can be detected within a smaller chip area. However, this has the disadvantages of small range and poor linearity, and cannot meet the design requirements of miniaturization while having a large range, high linearity and high precision. Summary of the invention

[0007] In view of the above problems and technical requirements, the inventors have proposed a time-division multiplexed three-axis accelerometer readout circuit. The technical solution of the present invention is as follows:

[0008] A time-division multiplexed three-axis accelerometer readout circuit includes a signal conditioning module and an electrostatic force feedback module connected to each other;

[0009] In the Nth working cycle of the readout circuit, the X-axis acceleration sensor, the Y-axis acceleration sensor and the Z-axis acceleration sensor in the three-axis accelerometer are respectively connected to the input terminal group of the signal conditioning module as the detection axis acceleration sensors, and the signal conditioning module receives the sensing signal output by the current detection axis acceleration sensor, and generates a detection signal according to the sensing signal;

[0010] For any axis acceleration sensor, when the acceleration sensor is a detection axis acceleration sensor of the Nth working cycle, the electrostatic force feedback module provides a feedback voltage to the acceleration sensor according to the detection signal output by the signal conditioning module and samples the feedback voltage;

[0011] When the acceleration sensor is converted from a detection axis acceleration sensor of the Nth working cycle to a non-detection axis acceleration sensor of the Nth working cycle, the electrostatic force feedback module continues to provide the acceleration sensor with the feedback voltage sampled in the Nth working cycle until the acceleration sensor serves as the detection axis acceleration sensor of the N+1th working cycle.

[0012] Its further technical solution is that the signal conditioning module includes a CV conversion circuit, a low-pass filter and a loop compensator, and the CV conversion circuit is connected to the X-axis acceleration sensor, the Y-axis acceleration sensor and the Z-axis acceleration sensor through a first multiplexer;

[0013] The CV conversion circuit includes a charge sensitive amplifier, a feedback capacitor C f1 , feedback resistor R f1 , switch SW rst1 , feedback capacitor C f2 , feedback resistor R f2 And switch SW rst2 ,in,

[0014] The first differential output terminal of the first multiplexer is connected to the non-inverting input terminal of the charge sensitive amplifier, and the second differential output terminal of the first multiplexer is connected to the inverting input terminal of the charge sensitive amplifier;

[0015] The non-inverting input terminal of the charge sensitive amplifier is connected via a switch SW rst1 Connected to the positive output terminal, the positive input terminal of the charge sensitive amplifier is connected to the positive output terminal through the feedback capacitor C f1 Connected with the non-inverting output terminal, the feedback resistor R f1 With the feedback capacitor C f1 in parallel;

[0016] The inverting input terminal of the charge sensitive amplifier is connected via a switch SW rst2 Connected to the inverting output terminal, the inverting input terminal of the charge sensitive amplifier is connected to the inverting output terminal through the feedback capacitor C f2 Connected with the inverting output terminal, the feedback resistor R f2 With the feedback capacitor C f2 in parallel.

[0017] A further technical solution is that the low-pass filter is a second-order low-pass Butterworth filter, including an operational amplifier U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a resistor R 1’ , resistor R 2’ , resistor R 3’ , capacitor C 1’ And the capacitor C 2’ ;

[0018] The non-inverting output terminal of the charge-sensitive amplifier is connected to one end of the capacitor C2, one end of the resistor R2 and one end of the resistor R3 through the resistor R1, the other end of the resistor R2 is connected to the positive output terminal of the operational amplifier U1 and one end of the capacitor C1, and the other end of the capacitor C1 is connected to the other end of the resistor R3 and the non-inverting input terminal of the operational amplifier U1;

[0019] The inverting output terminal of the charge sensitive amplifier is connected to the 1’ With capacitor C 2’ One end of the resistor R 2’ One end and the resistor R 3’ One end of the resistor R 2’ The other end is connected to the operational amplifier U 1’ The positive output terminal and capacitor C 1’ One end of the capacitor C 2’ The other end of the capacitor C2 is connected to the other end of the capacitor C 1’ The other end of the resistor R 3’ The other end and the operational amplifier U 1’ The non-inverting input terminal is connected.

[0020] A further technical solution is that the loop compensator is used to improve the stability of the signal conditioning module, including an operational amplifier U2, a capacitor C d1 , capacitor C d2 , capacitor C f3 , capacitor C f4 , capacitor C i1 , capacitor C i2 , resistor R p1 , resistor R p2 , resistor R i1 , resistor R i2 , resistor R f3 And the resistor R f4 ,in,

[0021] The positive output of operational amplifier U1 is connected to the p1 With resistor R i1 One end and capacitor C d1 One end of the capacitor C d1 And the resistor R i1 The other end is connected to the positive input of operational amplifier U2 and capacitor C f3 One end of the capacitor C f3 The other end is connected through capacitor C i1 Connected to the non-inverting output terminal of the operational amplifier U2, the resistor R f3 With capacitor C f3 in parallel;

[0022] The inverting output of operational amplifier U1 is connected to the p2 With resistor R i2 One end and capacitor C d2 One end of the capacitor C d2 And the resistor R i2 The other end is connected to the inverting input of operational amplifier U2 and capacitor C f4One end of the capacitor C f4 The other end is connected through capacitor C i2 Connected to the inverting output terminal of the operational amplifier U2, the resistor R f4 With capacitor C f4 in parallel.

[0023] A further technical solution is that the electrostatic force feedback module includes three feedback units, and the X-axis acceleration sensor, the Y-axis acceleration sensor and the Z-axis acceleration sensor are respectively connected to the output end group of a feedback unit;

[0024] The output terminal group of the signal conditioning module is connected to the input terminal group of the second multiplexer, the second multiplexer includes three output terminal groups, and the three output terminal groups of the second multiplexer are connected to the input terminal groups of the three feedback units in a one-to-one correspondence;

[0025] When the detection axis acceleration sensor is connected to the input terminal group of the signal conditioning module, the feedback unit connected to the detection axis acceleration sensor is connected to the output terminal group of the signal conditioning module through the second multiplexer.

[0026] Its further technical solution is that the feedback unit includes a high-voltage feedback circuit, which provides a feedback voltage to the detection axis acceleration sensor when connected to the signal conditioning module. The high-voltage feedback circuit includes a variable resistor array, an operational amplifier U3, a resistor R f5 And the resistor R f6 ;

[0027] The first input terminal of the feedback unit is connected to the positive input terminal of the operational amplifier U3 through a variable resistor array, and the second input terminal of the feedback unit is connected to the negative input terminal of the operational amplifier U3 through a variable resistor array; the positive input terminal of the operational amplifier U3 is connected to the negative input terminal of the operational amplifier U3 through a resistor R f5 The positive output terminal of the operational amplifier U3 is connected to the negative input terminal of the operational amplifier U3 through the resistor R f6 Connected to the inverting output terminal of operational amplifier U3.

[0028] A further technical solution is that the feedback unit further includes a sample-and-hold circuit;

[0029] In the same feedback unit, the sampling and holding circuit samples the feedback voltage when the high-voltage feedback circuit is connected to the signal conditioning module, and provides the sampled voltage to the correspondingly connected acceleration sensor when the high-voltage feedback circuit is disconnected from the signal conditioning module;

[0030] The sampling and holding circuit includes an operational amplifier U4, a switch S1, a switch S2, a switch S3, a switch S 1d , switch S 2d , switch S1’ , switch S 2’ , switch S 3’ , switch S 1d’ , switch S 2d’ , capacitor C s1 And the capacitor C s2 ,in,

[0031] The non-inverting input terminal of the operational amplifier U4 is connected to the capacitor C s1 One end of the operational amplifier U4 is connected to the capacitor C and connected to the positive output end through the switch S1. s2 One end is connected to the switch S 1’ Connected to the inverting output terminal;

[0032] The capacitor C s1 The other end of the switch S2 and the switch S 1d The other end of the switch S2 is connected to the positive phase output end of the operational amplifier U4 and one end of the switch S3. 1d The other end is connected through switch S 2d Connected to the other end of switch S3;

[0033] The capacitor C s2 The other end of the switch S 2’ One end and switch S 1d’ One end of the switch S 2’ The other end is connected to the inverting output of the operational amplifier U4 and the switch S 3’ One end of the switch S 1d’ The other end is connected through switch S 2d’ With switch S 3’ The other end of the connection.

[0034] A further technical solution is that the switch S1 and the switch S 1’ Controlled by the clock signal Φ1, the switches S2 and S 2’ , switch S3 and switch S 3’ Controlled by the clock signal Φ2, the switch S 1d And switch S 1d’ By the clock signal Φ 1d control, the switch S 2d And switch S 2d’ By the clock signal Φ 2d Inverting signal control;

[0035] The clock signal Φ1 and the clock signal Φ2 are two-phase non-overlapping clock signals. 1d is the clock signal obtained after the clock signal Φ1 is delayed by a preset time t, wherein the clock signal Φ2d It is the clock signal obtained after the clock signal Φ2 is delayed by a preset time t.

[0036] A further technical solution is that the feedback unit includes a multiplexing circuit, and the multiplexing circuit includes a variable resistor array, an operational amplifier HV gm1 , operational amplifier Gm2, operational amplifier SH gm1 , resistor R f7 , resistor R f8 , capacitor C d3 , capacitor C d4 , capacitor C s3 , capacitor C s4 , switch S f1 , switch S f1’ , switch S f2 , switch S f2’ , switch S f3 , switch S f3’ , switch S f4 And switch S f4’ ,in,

[0037] The first input terminal of the feedback unit is connected to the operational amplifier HV through a variable resistor array. gm1 The second input terminal of the feedback unit is connected to the non-inverting input terminal of the operational amplifier HV through a variable resistor array. gm1 The inverting input terminal is connected;

[0038] Operational Amplifier HV gm1 The non-inverting input terminal is connected through the resistor R f7 And switch S f2 Connected to the positive output terminal of operational amplifier Gm2, operational amplifier HV gm1 The positive phase output terminal passes through the switch S f1 connected to the non-inverting input terminal of the operational amplifier Gm2;

[0039] Operational Amplifier HV gm1 The inverting input is connected through the resistor R f8 And switch S f2’ Connected to the inverting output terminal of operational amplifier Gm2, operational amplifier HV gm1 The inverting output terminal is connected to the switch S f1’ connected to the inverting input terminal of the operational amplifier Gm2;

[0040] The non-inverting input of operational amplifier Gm2 is connected through switch S f3 With operational amplifier SH gm1 The positive output terminal of the operational amplifier Gm2 is connected to the negative input terminal through the switch S f3’ With operational amplifier SH gm1 The inverting output terminal is connected;

[0041] The capacitor C d3 One end of the capacitor C s3 One end of the capacitor C is connected to the positive phase output terminal of the operational amplifier Gm2. s3 The other end of the operational amplifier SH gm1 The non-inverting input terminal is connected to the capacitor C d3 The other end is grounded;

[0042] The capacitor C d4 One end of the capacitor C s4 One end of the capacitor C is connected to the inverting output terminal of the operational amplifier Gm2. s4 The other end of the operational amplifier SH gm1 The inverting input terminal is connected to the capacitor C d4 The other end is grounded;

[0043] Operational Amplifier SH gm1 The non-inverting input terminal is connected through switch S f4 With operational amplifier SH gm1 The non-inverting output terminal of the operational amplifier SH gm1 The inverting input of the f4’ With operational amplifier SH gm1 The inverting output terminal is connected;

[0044] Switch S f1 , switch S f1’ , switch S f2 , switch S f2’ , switch S f4 And switch S f4’ By the clock signal Φ 1’ Control, switch S f3 And switch S f3’ By the clock signal Φ 1’ The inverting signal control.

[0045] A further technical solution is that the variable resistor array includes a positive phase resistor array and a negative phase resistor array;

[0046] The positive phase resistor array includes a positive phase initial unit and n-stage positive phase resistor units cascaded in sequence. The positive phase initial unit includes a resistor R 01 And the resistor R 02 , the positive phase resistor unit includes a positive phase first resistor, a positive phase second resistor and an active switch, the resistance value of the positive phase first resistor is 2R, and the resistance value of the positive phase second resistor is R;

[0047] Resistor R 01The first end of is connected to the first input end of the variable resistor array, and the first end of the first positive phase resistor in the positive phase resistor unit is connected to the first input end of the variable resistor array through a corresponding active switch;

[0048] Resistor R 02 The first end of the resistor R 01 The second end of the resistor R 02 The second end of is connected to the second end of the first positive phase resistor in the first-stage positive phase resistor unit, the first end of the second positive phase resistor in the positive phase resistor unit is connected to the second end of the first positive phase resistor in the same-stage positive phase resistor unit, the second end of the second positive phase resistor in the positive phase resistor unit is connected to the first end of the second positive phase resistor in the next-stage positive phase resistor unit, and the second end of the second positive phase resistor in the last-stage positive phase resistor unit is connected to the first output end of the variable resistor array;

[0049] The inverting resistor array includes an inverting initial unit and n-stage inverting resistor units cascaded in sequence. The inverting initial unit includes a resistor R 01’ And the resistor R 02’ , the inverting resistor unit includes an inverting first resistor, an inverting second resistor and an active switch, the resistance value of the inverting first resistor is 2R, and the resistance value of the inverting second resistor is R;

[0050] Resistor R 01’ The first end of the inverting resistor is connected to the second input end of the variable resistor array, and the first end of the inverting first resistor in the inverting resistor unit is connected to the second input end of the variable resistor array through a corresponding active switch;

[0051] Resistor R 02’ The first end of the resistor R 01’ The second end of the resistor R 02’ The second end of is connected to the second end of the inverted first resistor in the first-stage inverted resistor unit, the first end of the inverted second resistor in the inverted resistor unit is connected to the second end of the inverted first resistor in the same-stage inverted resistor unit, the second end of the inverted second resistor in the inverted resistor unit is connected to the first end of the inverted second resistor in the next-stage inverted resistor unit, and the second end of the inverted second resistor in the last-stage inverted resistor unit is connected to the second output end of the variable resistor array; the resistor R 01 The second end is connected in series with a resistor R 03 And the resistor R 04 With resistor R 01’ The second end of the resistor R 01 , resistor R 01’ , resistor R 03 And the resistor R 04 The resistance value is 2R, the resistor R 02 And the resistor R 02’ The resistance value is R.

[0052] The beneficial technical effects of the present invention are:

[0053] (1) The signal conditioning module is multiplexed in a time-division multiplexing manner to read out the sensor signals of the X-axis, Y-axis, and Z-axis acceleration sensors in the three-axis accelerometer respectively. At the same time, the sampling and holding function of the electrostatic force feedback module is used to continuously provide feedback voltage to the X-axis, Y-axis, and Z-axis acceleration sensors. The design of the three-axis closed-loop accelerometer readout circuit is realized in a smaller area, which meets the design requirements of miniaturization while having a large range, high linearity, and high precision.

[0054] (2) The feedback unit includes a multiplexing circuit, which can time-share the second-stage operational amplifier to implement the sampling and holding function and the high-voltage feedback function, thereby effectively reducing the circuit area and power consumption.

[0055] (3) A variable resistor array is used to adjust the feedback coefficient. The variable resistor array has an R-2R structure and can achieve fine adjustment of the gain without increasing the static operating point of the op amp input. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a schematic diagram of the internal structure of the capacitive acceleration sensor provided by the present invention.

[0057] Figure 2 The present invention is a structural block diagram of an embodiment of a time-division multiplexed three-axis accelerometer readout circuit provided by the present invention.

[0058] Figure 3 The figure is a circuit diagram of an embodiment of a CV conversion circuit provided by the present invention.

[0059] Figure 4 The figure is a circuit diagram of an embodiment of a low-pass filter provided by the present invention.

[0060] Figure 5 It is a circuit principle diagram of an embodiment of the loop compensator provided by the present invention.

[0061] Figure 6 The figure is a circuit diagram of an embodiment of a high voltage feedback circuit provided by the present invention.

[0062] Figure 7 The figure is a circuit diagram of an embodiment of a variable resistor array provided by the present invention.

[0063] Figure 8 The schematic diagram of a circuit of an embodiment of a sampling and holding circuit provided by the present invention.

[0064] Fig. 9 It is a timing diagram of the clock signal for controlling the sampling and holding circuit provided by the present invention.

[0065] Fig.10 It is a circuit principle diagram of an embodiment of the multiplexing circuit provided by the present invention.

[0066] Fig.11 is the clock signal Φ provided by the present invention 1’ Equivalent circuit diagram of the multiplexing circuit when is at a valid level.

[0067] Fig.12 is the clock signal Φ provided by the present invention 1’ Equivalent circuit diagram of the multiplexing circuit when it is an invalid level. DETAILED DESCRIPTION

[0068] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0069] The present invention provides a time-division multiplexed three-axis accelerometer readout circuit, comprising a signal conditioning module and an electrostatic force feedback module connected to each other;

[0070] In the Nth working cycle of the readout circuit, N is a positive integer, the X-axis acceleration sensor, the Y-axis acceleration sensor and the Z-axis acceleration sensor in the three-axis accelerometer are respectively connected to the input terminal group of the signal conditioning module as the detection axis acceleration sensors, and the signal conditioning module receives the sensing signal output by the current detection axis acceleration sensor, and generates a detection signal according to the sensing signal;

[0071] For any axis acceleration sensor, when the acceleration sensor is a detection axis acceleration sensor of the Nth working cycle, the electrostatic force feedback module provides a feedback voltage to the acceleration sensor according to the detection signal output by the signal conditioning module and samples the feedback voltage;

[0072] When the acceleration sensor is converted from a detection axis acceleration sensor of the Nth working cycle to a non-detection axis acceleration sensor of the Nth working cycle, the electrostatic force feedback module continues to provide the acceleration sensor with the feedback voltage sampled in the Nth working cycle until the acceleration sensor serves as the detection axis acceleration sensor of the N+1th working cycle.

[0073] Specifically, the X-axis, Y-axis and Z-axis acceleration sensors are all closed-loop capacitive acceleration sensors, such as Figure 1 As shown in FIG. 1 , the internal structure of a closed-loop capacitive acceleration sensor can generally be represented as a movable plate with a single degree of freedom and two parallel plate capacitors formed by two fixed plates, namely, an upper parallel plate capacitor C formed by the movable plate and the upper fixed plate. T , and the lower parallel plate capacitor C formed by the movable plate and the lower fixed plate BWhen measuring acceleration, the movable plate will be displaced as the acceleration changes, and the displacement can be represented by the capacitance difference between the two parallel plate capacitors, i.e., the differential capacitance value. The signal conditioning module converts the differential capacitance value, i.e., the sensing signal, into a detection voltage value, i.e., the detection signal output.

[0074] At the same time, in order to achieve better linearity between the displacement of the movable plate and the differential capacitance value, the closed-loop capacitive acceleration sensor generally adds a feedback plate above and below the movable plate. When the feedback voltage is applied to the upper and lower feedback plates, the feedback plate will generate a differential electrostatic force on the movable plate due to the electric field formed by the parallel plates. By adjusting the electrostatic force to offset the inertial force generated by the acceleration, the movable plate is always near the equilibrium position, and the best linearity can be obtained. At the same time, since the displacement of the middle plate becomes smaller, when the outside world has a greater acceleration, the circuit will not cause output saturation due to excessive deviation of the middle plate, which can make the accelerometer have a larger range. The feedback voltage provided by the electrostatic force feedback module is used to keep the movable plate in the X-axis, Y-axis and Z-axis acceleration sensors near the equilibrium position.

[0075] Specifically, the basic working principle of the readout circuit structure provided by the present invention is to multiplex the signal conditioning module. In the Nth working cycle, the signal conditioning module generates detection signals of the X-axis, Y-axis and Z-axis acceleration sensors respectively. Within the time of a single axial detection, the signal conditioning module, the electrostatic force feedback module and the detection axial acceleration sensor are approximately formed into a single-axis closed-loop structure. The signal conditioning module converts the differential capacitance value of the detection axial capacitive acceleration sensor into a detection voltage value. The electrostatic force feedback module loads a feedback voltage to the feedback plate of the detection axial capacitive acceleration sensor according to the detection voltage value, so that the movable plate signal in the detection axial capacitive acceleration sensor is in a balanced position.

[0076] Different from the traditional single-axis closed-loop structure, for any axis acceleration sensor, when the acceleration sensor is the detection axis acceleration sensor of the Nth working cycle, the electrostatic force feedback module provides feedback voltage to the acceleration sensor according to the detection signal output by the signal conditioning module, and samples the feedback voltage; when the acceleration sensor is converted from the detection axis acceleration sensor of the Nth working cycle to the non-detection axis acceleration sensor of the Nth working cycle, the electrostatic force feedback module continues to provide the acceleration sensor with the voltage sampled in the Nth working cycle until the acceleration sensor is used as the detection axis acceleration sensor of the N+1th working cycle, and the electrostatic force feedback module provides it with the feedback voltage generated in the N+1th working cycle. In this way, when any axis acceleration sensor is a non-detection axis acceleration sensor, the electrostatic force feedback module can still provide feedback voltage to the acceleration sensor of the axis, keep the movable pole plate in the acceleration sensor near the equilibrium position, and prevent the excessive acceleration applied by the outside from causing irreversible deformation of the movable pole plate beam, thereby affecting the detection result.

[0077] In this embodiment, the X-axis, Y-axis and Z-axis acceleration sensors are used as detection axis acceleration sensors in turn within one working cycle. In the N+1th working cycle, the X-axis acceleration sensor is first used as the detection axis acceleration sensor, and the X-axis acceleration sensor is connected to the input terminal group of the signal conditioning module, and the Y-axis and Z-axis acceleration sensors are disconnected from the signal conditioning module. The signal conditioning module generates an X-axis detection signal according to the sensing signal of the X-axis acceleration sensor. The electrostatic force feedback module generates the X-axis feedback voltage of the N+1th working cycle according to the X-axis detection signal and samples it, and the feedback voltage is loaded onto the feedback plate of the X-axis acceleration sensor. At the same time, the Y-axis and Z-axis acceleration sensors are used as non-detection axis acceleration sensors, and the electrostatic force feedback module loads the Y-axis feedback voltage and the Z-axis feedback voltage generated in the Nth working cycle onto the feedback plates of the Y-axis and Z-axis acceleration sensors, respectively.

[0078] In the next one-third cycle, the detection axis acceleration sensor is switched from the X-axis acceleration sensor to the Y-axis acceleration sensor. Similarly, the signal conditioning module generates a Y-axis detection signal, and the electrostatic force feedback module generates and samples the Y-axis feedback voltage of the N+1th working cycle according to the Y-axis detection signal. At this time, the electrostatic force feedback module provides the X-axis feedback voltage generated in the N+1th working cycle, the Y-axis feedback voltage generated in the N+1th working cycle, and the Z-axis feedback voltage generated in the Nth working cycle to the feedback plates of the X-axis, Y-axis, and Z-axis acceleration sensors, respectively.

[0079] In the last one-third of the cycle, the detection axis acceleration sensor is switched from the Y-axis acceleration sensor to the Z-axis acceleration sensor. Similarly, the signal conditioning module generates a Z-axis detection signal, and the electrostatic force feedback module generates and samples the Z-axis feedback voltage of the N+1th working cycle based on the Z-axis detection signal. At this time, the electrostatic force feedback module provides the X-axis feedback voltage, Y-axis feedback voltage, and Z-axis feedback voltage generated in the N+1th working cycle to the feedback plates of the X-axis, Y-axis, and Z-axis acceleration sensors, respectively.

[0080] like Figure 1 As shown, the signal conditioning module includes a CV conversion circuit, a low-pass filter and a loop compensator, and the CV conversion circuit is connected to the X-axis acceleration sensor, the Y-axis acceleration sensor and the Z-axis acceleration sensor through a first multiplexer. The first multiplexer is a three-to-one switch, and in specific implementation, the acceleration sensor can be connected to the signal conditioning module by controlling the selection of the three-to-one switch.

[0081] The electrostatic force feedback module includes three feedback units, and the X-axis acceleration sensor, the Y-axis acceleration sensor, and the Z-axis acceleration sensor are respectively connected to the output terminal group of a feedback unit; the second multiplexer is a one-to-three switch, and the output terminal group of the signal conditioning module is connected to the input terminal group of the second multiplexer, and the second multiplexer includes three groups of output terminal groups, and the three groups of output terminal groups of the second multiplexer are connected to the input terminal groups of the three feedback units in a one-to-one correspondence. When the detection axis acceleration sensor is connected to the input terminal group of the signal conditioning module, the feedback unit connected to the detection axis acceleration sensor is connected to the output terminal group of the signal conditioning module through the second multiplexer.

[0082] The CV conversion circuit adopts chopper stabilization technology (CHS) to reduce low-frequency noise and offset and convert the differential capacitance value into a voltage value. The specific method of the chopper stabilization technology is consistent with the prior art. The CV conversion circuit includes a charge sensitive amplifier, a feedback capacitor C f1 , feedback resistor R f1 , switch SW rst1 , feedback capacitor C f2 , feedback resistor R f2 And switch SW rst2 ,in,

[0083] The first differential output terminal of the first multiplexer is connected to the positive phase input terminal of the charge sensitive amplifier, and the second differential output terminal of the first multiplexer is connected to the negative phase input terminal of the charge sensitive amplifier; the positive phase input terminal of the charge sensitive amplifier is connected to the positive phase input terminal of the charge sensitive amplifier through the switch SW rst1 Connected to the positive output terminal, the positive input terminal of the charge sensitive amplifier is connected to the positive output terminal through the feedback capacitor C f1 Connected with the non-inverting output terminal, the feedback resistor Rf1 With the feedback capacitor C f1 The inverting input terminal of the charge sensitive amplifier is connected in parallel via a switch SW rst2 Connected to the inverting output terminal, the inverting input terminal of the charge sensitive amplifier is connected to the inverting output terminal through the feedback capacitor C f2 Connected with the inverting output terminal, the feedback resistor R f2 With the feedback capacitor C f2 in parallel.

[0084] The input terminal group of the signal conditioning module specifically refers to the positive input terminal and the negative input terminal of the charge sensitive amplifier. The acceleration sensor is connected to the signal conditioning module, specifically, the upper fixed electrode plate of the acceleration sensor is connected to the positive input terminal of the charge sensitive amplifier through the first multiplexer, and the lower fixed electrode plate of the acceleration sensor is connected to the negative input terminal of the charge sensitive amplifier through the first multiplexer. Figure 3 The figure shows the connection diagram of the acceleration sensor and the CV conversion circuit. Figure 3 The first multiplexer is omitted. Wherein, C0 is the upper parallel plate capacitance C when the movable plate is kept in the equilibrium position. T And the lower parallel plate capacitor C B The capacitance value of the parallel plate is ΔC, which is the upper parallel plate capacitance C. T And the lower parallel plate capacitor C B The capacitance change, C T =C0+ΔC,C B =C0-ΔC.

[0085] Since changing the capacitance value or the voltage difference ΔV across the capacitor can change the amount of charge Q stored on the capacitor, in order to ensure that the charge Q changed by the voltage difference ΔV across the capacitor is not amplified by the charge sensitive amplifier, balancing capacitors Cr1 and Cr2 are set to be parallel to the upper plate capacitor C T And the lower parallel plate capacitor C B Forming a capacitive bridge, the upper parallel plate capacitor C T The first bridge arm is formed in series with the balancing capacitor Cr1, and the lower parallel plate capacitor C B The first bridge arm is connected in parallel with the second bridge arm, and the carrier signal V is loaded on the movable plate. m , carrier signal V m The square wave signal is connected to one end of the trim capacitor Cr1 and one end of the trim capacitor Cr2 and loaded with the carrier signal V m The inverted signal.

[0086] The CV conversion circuit uses the carrier signal V mThe input signal is modulated to a high frequency and amplified by a charge-sensitive amplifier. The signal containing the low-frequency noise component of the charge-sensitive amplifier is demodulated through subsequent chopping, so that the amplified input signal returns to a low frequency, while the low-frequency noise and offset of the charge-sensitive amplifier are modulated to a high frequency, thereby achieving the separation of the low-frequency input signal and the low-frequency noise offset.

[0087] Specifically, the switch SW rst1 With switch SW rst2 The carrier signal V m A set of switches controlled by the carrier signal V m When the switch SW is high rst1 Close, switch SW rst2 Disconnect; carrier signal V m When the switch SW is low rst2 Close, switch SW rst1 Disconnect, and use this method to achieve chopping demodulation, so that the output phase remains unchanged, and can effectively eliminate low-frequency noise and op amp offset. f1 And capacitor C f2 As feedback capacitor, resistor R f1 And the resistor R f2 As a feedback resistor, it ensures that the common mode point of the charge sensitive amplifier input voltage remains unchanged. Since the feedback resistor and the feedback capacitor will form an additional discharge path, in order to avoid the discharge path consuming too much signal energy, the discharge cycle of the discharge path needs to be much longer than the carrier signal V m cycle, the resistance R f1 And the resistor R f2 The value is generally in the range of hundreds of MΩ to GΩ.

[0088] Ignoring the current flowing through the feedback resistor, in one carrier cycle, let the carrier signal V m The voltage V of the positive phase carrier in the first half cycle M = Common mode voltage V CM , C f1 =C f21 =C f , then the differential voltage V output by the CV conversion circuit out1 =2V CM ΔC / C f =V M ΔC / C f .

[0089] Since the chopper stabilization technology is used to reduce noise, a low-pass filter needs to be added to suppress the noise modulated to high frequencies. In this embodiment, the low-pass filter is a second-order low-pass Butterworth filter, such as Figure 4 As shown, the low-pass filter includes an operational amplifier U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a resistor R1’ , resistor R 2’ , resistor R 3’ , capacitor C 1’ And the capacitor C 2’ ;

[0090] The non-inverting output terminal of the charge-sensitive amplifier is connected to one end of the capacitor C2, one end of the resistor R2 and one end of the resistor R3 through the resistor R1, the other end of the resistor R2 is connected to the positive output terminal of the operational amplifier U1 and one end of the capacitor C1, and the other end of the capacitor C1 is connected to the other end of the resistor R3 and the non-inverting input terminal of the operational amplifier U1;

[0091] The inverting output terminal of the charge sensitive amplifier is connected to the 1’ With capacitor C 2’ One end of the resistor R 2’ One end and the resistor R 3’ One end of the resistor R 2’ The other end is connected to the operational amplifier U 1’ The positive output terminal and capacitor C 1’ One end of the capacitor C 2’ The other end of the capacitor C2 is connected to the other end of the capacitor C 1’ The other end of the resistor R 3’ The other end and the operational amplifier U 1’ The positive input terminal of C1 = C 1’ 、C2=C 2’ 、R1=R 1’ 、R2=R 2’ 、R3=R 3’ When , the transfer function of the low-pass filter is:

[0092]

[0093] The loop compensator is used to improve the stability of the signal conditioning module. Commonly used loop compensators include three types: Type I compensator (TYPE I), Type II compensator (TYPE II) and Type III compensator (TYPE III). The loop compensator in this embodiment is a Type III compensator, that is, a compensator with three poles and two zeros. Figure 5 As shown, including operational amplifier U2, capacitor C d1 , capacitor C d2 , capacitor C f3 , capacitor C f4 , capacitor C i1 , capacitor C i2 , resistor R p1 , resistor R p2 , resistor R i1, resistor R i2 , resistor R f3 And the resistor R f4 , where the positive-phase output terminal of the operational amplifier U1 is connected through the resistor R p1 With resistor R i1 One end and capacitor C d1 One end of the capacitor C d1 And the resistor R i1 The other end is connected to the positive input of operational amplifier U2 and capacitor C f3 One end of the capacitor C f3 The other end is connected through capacitor C i1 Connected to the non-inverting output terminal of the operational amplifier U2, the resistor R f3 With capacitor C f3 In parallel, the inverting output of operational amplifier U1 is connected through resistor R p2 With resistor R i2 One end and capacitor C d2 One end of the capacitor C d2 And the resistor R i2 The other end is connected to the inverting input of operational amplifier U2 and capacitor C f4 One end of the capacitor C f4 The other end is connected through capacitor C i2 Connected to the inverting output terminal of the operational amplifier U2, the resistor R f4 With capacitor C f4 in parallel.

[0094] Capacitor C d1 With capacitor C d2 The capacitance value is C d , capacitor C f3 With capacitor C f4 The capacitance value is C f , capacitor C i1 With capacitor C i2 The capacitance value is C i , resistor R p1 With resistor R p2 The resistance value is R p , resistor R f3 With resistor R f4 The resistance value is R f , resistor R i1 With resistor R i2 The resistance value is R i , then the transfer function of the loop compensator is:

[0095]

[0096] For any feedback unit, the input end group of the feedback unit is connected to an output end group of the second multiplexer, the output end group of the feedback unit is connected to the feedback plate in the acceleration sensor of the corresponding axis, the input end group of the feedback unit includes a first input end and a second input end, and the output end group includes a first output end and a second output end.

[0097] In one embodiment of the present invention, the feedback unit includes a high-voltage feedback circuit and a sampling and holding circuit arranged at the rear stage of the high-voltage feedback circuit. When the high-voltage feedback circuit is connected to the signal conditioning module, a feedback voltage is provided to the feedback plate in the detection axis acceleration sensor, so that the middle plate in the detection axis acceleration sensor is maintained near the equilibrium position to realize the high-voltage feedback function. In the same feedback unit, the sampling and holding circuit samples the feedback voltage when the high-voltage feedback circuit is connected to the signal conditioning module, and provides the sampled voltage to the corresponding connected acceleration sensor when the high-voltage feedback circuit is disconnected from the signal conditioning module to realize the sampling and holding function. It is ensured that the mechanical structure in the non-detection axis acceleration sensor will not be irreversibly deformed due to excessive impact.

[0098] like Figure 6 As shown, the high voltage feedback circuit includes a variable resistor array, an operational amplifier U3, a resistor R f5 And the resistor R f6 The first input terminal of the feedback unit is connected to the positive input terminal of the operational amplifier U3 through a variable resistor array, and the second input terminal of the feedback unit is connected to the negative input terminal of the operational amplifier U3 through a variable resistor array; the positive input terminal of the operational amplifier U3 is connected to the negative input terminal of the operational amplifier U3 through a resistor R f5 The positive output terminal of the operational amplifier U3 is connected to the negative input terminal of the operational amplifier U3 through the resistor R f6 Connected to the inverting output terminal of operational amplifier U3.

[0099] It should be noted that, since the voltage required for electrostatic force feedback is relatively high, a high-voltage MOS tube needs to be used in the MOS tube in the internal circuit of the operational amplifier U3, and a voltage-limiting element is added to the circuit structure that is sensitive to the voltage difference, such as a Zener diode between the gate and source of the MOS tube, to prevent the MOS tube from being broken down and causing abnormal circuit operation.

[0100] Specifically, the variable resistor array is used to change the input resistance of the operational amplifier U3 to meet the requirements of different feedback coefficients required for different axial acceleration detection. In order to prevent the static operating point of the input terminal of the operational amplifier U3 from changing with the change of the input resistance, the present invention designs a variable resistor array with an R-2R structure, which is used to reduce the adjustable step size while ensuring that the static operating point of the input terminal of the operational amplifier does not change. This structure has the characteristic of fixed input impedance, so for a fixed feedback resistor voltage divider, the input terminal of the operational amplifier has a fixed input impedance.

[0101] like Figure 7 As shown, the variable resistor array includes a positive phase resistor array and a negative phase resistor array, the positive phase resistor array includes a positive phase initial unit and n-stage positive phase resistor units cascaded in sequence, the positive phase initial unit includes a resistor R 01 And the resistor R 02 The positive phase resistor unit includes a positive phase first resistor, a positive phase second resistor and an active switch. The resistance value of the positive phase first resistor is 2R, and the resistance value of the positive phase second resistor is R.

[0102] Resistor R 01 The first end of is connected to the first input end of the variable resistor array, and the first end of the first positive phase resistor in the positive phase resistor unit is connected to the first input end of the variable resistor array through a corresponding active switch;

[0103] Resistor R 02 The first end of the resistor R 01 The second end of the resistor R 02 The second end of is connected to the second end of the first positive phase resistor in the first-stage positive phase resistor unit, the first end of the second positive phase resistor in the positive phase resistor unit is connected to the second end of the first positive phase resistor in the same-stage positive phase resistor unit, the second end of the second positive phase resistor in the positive phase resistor unit is connected to the first end of the second positive phase resistor in the next-stage positive phase resistor unit, the second end of the second positive phase resistor in the last-stage positive phase resistor unit is connected to the first output end of the variable resistor array, and all the second resistors in the positive phase resistor unit are connected in series. The first input end of the feedback unit is connected to the positive phase input end of the operational amplifier U3 through the variable resistor array, that is, the first input end of the feedback unit is connected to the first input end of the variable resistor array, and the positive phase input end of the operational amplifier U3 is connected to the first output end of the variable resistor array.

[0104] Similar to the structure of the positive phase resistor array, the negative phase resistor array includes a negative phase initial unit and n-stage negative phase resistor units cascaded in sequence. The negative phase initial unit includes a resistor R 01’ And the resistor R 02’ , the inverting resistor unit includes an inverting first resistor, an inverting second resistor and an active switch, the resistance value of the inverting first resistor is 2R, and the resistance value of the inverting second resistor is R;

[0105] Resistor R 01’ The first end of the inverting first resistor in the inverting resistor unit is connected to the second input end of the variable resistor array through a corresponding active switch; the resistor R 02’ The first end of the resistor R 01’ The second end of the resistor R 02’ The second end of the feedback unit is connected to the second end of the inverting first resistor in the first-stage inverting resistor unit, the first end of the inverting second resistor in the inverting resistor unit is connected to the second end of the inverting first resistor in the same-stage inverting resistor unit, the second end of the inverting second resistor in the inverting resistor unit is connected to the first end of the inverting second resistor in the next-stage inverting resistor unit, and the second end of the inverting second resistor in the last-stage inverting resistor unit is connected to the second output end of the variable resistor array; the second input end of the feedback unit is connected to the inverting input end of the operational amplifier U3 through the variable resistor array, that is, the second input end of the feedback unit is connected to the second input end of the variable resistor array, and the inverting input end of the operational amplifier U3 is connected to the second output end of the variable resistor array.

[0106] Resistor R 01 The second end is connected in series with a resistor R 03 And the resistor R 04 With resistor R 01’ The second end of the resistor R 01 , resistor R 01’ , resistor R 03 And the resistor R 04 The resistance value is 2R, the resistor R 02 And the resistor R 02’ The resistance value is R.

[0107] The active switches in the n-level positive phase resistor unit are sequentially connected with S0-S n-1 Indicates that the active switches in the n-level inverting resistor unit are also sequentially represented by S0-S n-1 Indicates that the on-off state of the active switch in the positive phase resistor unit and the reverse phase resistor unit of the same order is the same, and the voltage between the first and second input terminals of the variable resistor array is V in , R f5 =R f6 =R f’ The voltage between the positive output terminal and the negative output terminal of the high-voltage feedback circuit operational amplifier U3 is the feedback voltage V out2 for:

[0108]

[0109] Among them, S iIndicates the on-off state of the i-th active switch in the positive phase resistance unit and the reverse phase resistance unit. When the i-th active switch is turned on, S i =1; when the i-th active switch is turned on, S i = 0. By controlling the on-off state of each active switch in the positive phase resistance unit and the negative phase resistance unit, high-precision gain adjustment of the high-voltage feedback circuit can be achieved.

[0110] like Figure 8 As shown, the sampling and holding circuit includes an operational amplifier U4, a switch S1, a switch S2, a switch S3, a switch S 1d , switch S 2d , switch S 1’ , switch S 2’ , switch S 3’ , switch S 1d’ , switch S 2d’ , capacitor C s1 And the capacitor C s2 ,in,

[0111] The positive-phase output terminal of the operational amplifier U3 is connected to the 1d With capacitor C s1 The inverting output of the operational amplifier U3 is connected to one end of the switch S 1d’ With capacitor C s2 One end of the connection;

[0112] The non-inverting input terminal of the operational amplifier U4 is connected to the capacitor C s1 One end of the operational amplifier U4 is connected to the capacitor C and connected to the positive output end through the switch S1. s2 One end is connected to the switch S 1’ Connected to the inverting output terminal;

[0113] The capacitor C s1 The other end of the switch S2 and the switch S 1d The other end of the switch S2 is connected to the positive phase output end of the operational amplifier U4 and one end of the switch S3. 1d The other end is connected through switch S 2d connected to the other end of the switch S3 and connected to a feedback plate in the corresponding axial acceleration sensor as a first output end of the feedback unit;

[0114] The capacitor C s2 The other end of the switch S 2’ One end and switch S 1d’ One end of the switch S 2’ The other end is connected to the inverting output of the operational amplifier U4 and the switch S 3’One end of the switch S 1d’ The other end is connected through switch S 2d’ With switch S 3’ The other end is connected to the other end and is connected to another feedback plate in the corresponding axial acceleration sensor as the second output end of the feedback unit.

[0115] The switch S1 and the switch S 1’ Controlled by the clock signal Φ1, the switches S2 and S 2’ , switch S3 and switch S 3’ Controlled by the clock signal Φ2, the switch S 1d And switch S 1d’ By the clock signal Φ 1d control, the switch S 2d And switch S 2d’ By the clock signal Φ 2d The clock signal Φ1 and the clock signal Φ2 are two-phase non-overlapping clock signals, and the clock signal Φ 1d is the clock signal obtained after the clock signal Φ1 is delayed by a preset time t, wherein the clock signal Φ 2d The clock signal Φ2 is a clock signal obtained by delaying the clock signal Φ2 for a preset time t. 1d The clock signal Φ2 is also a two-phase non-overlapping clock signal. Fig. 9 The clock signals Φ1, Φ2, and Φ 1d and clock signal Φ 2d The inverted signal Timing diagram of .

[0116] Taking the sampling and holding circuit connected to the feedback plate in the X-axis acceleration sensor as an example, when the X-axis acceleration sensor is the detection axis acceleration sensor of the Nth working cycle, the clock signal Φ1 and the clock signal Φ 1d and clock signal is a valid level, i.e. a high level, switch S1 and switch S 1d , switch S 2d , switch S 1’ , switch S 1d’ And switch S 2d’ Close, switch S2, switch S 2’ , switch S3 and switch S 3’ The operational amplifier U4 is disconnected and connected in a unit negative feedback form. The feedback voltage output by the high-voltage feedback circuit connected to the sampling and holding circuit is loaded to the feedback plate through the operational amplifier U4 and is s1 And capacitor C s2 The sampled.

[0117] After that, when the X-axis acceleration sensor is converted to the non-detection axis acceleration sensor of the Nth working cycle, in order to prevent multiple switches from operating at the same time and affecting the stability of the circuit, the clock signal Φ1 and the clock signal Φ 1d and clock signal Inverted to low level in sequence, at the same time, the clock signal Φ2 is in the clock signal Φ1 and the clock signal Φ 1d After inverting to a low level, it inverts to a high level. 1d , switch S 2d , switch S 1’ , switch S 1d’ And switch S 2d’ Disconnect, switch S2, switch S 2’ , switch S3 and switch S 3’ Closed. Capacitor C s1 And capacitor C s2 The plate originally connected to the output end of the high-voltage feedback circuit is connected to the corresponding feedback plate, and the sampled feedback voltage is loaded to the feedback plate to maintain the output of the feedback voltage.

[0118] In another embodiment of the present invention, in order to further reduce the circuit area and power consumption, the high voltage feedback circuit and the sample and hold circuit are integrated into a multiplexing circuit, wherein the multiplexing circuit includes a variable resistor array, an operational amplifier HV gm1 , operational amplifier Gm2, operational amplifier SH gm1 , resistor R f7 , resistor R f8 , capacitor C d3 , capacitor C d4 , capacitor C s3 , capacitor C s4 , switch S f1 , switch S f1’ , switch S f2 , switch S f2’ , switch S f3 , switch S f3’ , switch S f4 And switch S f4’ The high voltage feedback function and the sampling and holding function are realized by multiplexing the operational amplifier Gm2 in time sharing. The structure of the variable resistor array is consistent with that of the variable resistor array in the above embodiment, and will not be described in detail here.

[0119] Specifically, the first input terminal of the feedback unit is connected to the operational amplifier HV through a variable resistor array. gm1 The non-inverting input terminal of the operational amplifier HV is connected, that is, the first input terminal of the feedback unit is connected to the first input terminal of the variable resistor array. gm1 The positive input terminal of the feedback unit is connected to the first output terminal of the variable resistor array; the second input terminal of the feedback unit is connected to the operational amplifier HVgm1 The inverting input terminal of the feedback unit is connected to the first input terminal of the variable resistor array, and the operational amplifier HV gm1 The inverting input terminal is connected to the second output terminal of the variable resistor array.

[0120] Operational Amplifier HV gm1 The non-inverting input terminal is connected through the resistor R f7 And switch S f2 Connected to the positive output terminal of operational amplifier Gm2, operational amplifier HV gm1 The positive phase output terminal passes through the switch S f1 connected to the non-inverting input terminal of the operational amplifier Gm2;

[0121] Operational Amplifier HV gm1 The inverting input is connected through the resistor R f8 And switch S f2’ Connected to the inverting output terminal of operational amplifier Gm2, operational amplifier HV gm1 The inverting output terminal is connected to the switch S f1’ connected to the inverting input terminal of the operational amplifier Gm2;

[0122] The non-inverting input of operational amplifier Gm2 is connected through switch S f3 With operational amplifier SH gm1 The positive output terminal of the operational amplifier Gm2 is connected to the negative input terminal through the switch S f3’ With operational amplifier SH gm1 The inverting output terminal is connected;

[0123] The capacitor C d3 One end of the capacitor C s3 and the positive phase output terminal of the operational amplifier Gm2, and is connected to the corresponding feedback plate as the first output terminal of the feedback unit. The capacitor C s3 The other end of the operational amplifier SH gm1 The non-inverting input terminal is connected to the capacitor C d3 The other end is grounded;

[0124] The capacitor C d4 One end of the capacitor C s4 The capacitor C is connected to the inverting output terminal of the operational amplifier Gm2 and is connected to the corresponding feedback plate as the second output terminal of the feedback unit. s4 The other end of the operational amplifier SH gm1 The inverting input terminal is connected to the capacitor C d4 The other end is grounded;

[0125] Operational Amplifier SH gm1 The non-inverting input terminal is connected through switch Sf4 With operational amplifier SH gm1 The non-inverting output terminal of the operational amplifier SH gm1 The inverting input of the f4’ With operational amplifier SH gm1 The inverting output terminal is connected;

[0126] Switch S f1 , switch S f1’ , switch S f2 , switch S f2’ , switch S f4 And switch S f4’ By the clock signal Φ 1’ Control, switch S f3 And switch S f3’ By the clock signal Φ 1’ The inverting signal control.

[0127] In order to ensure the consistency of the static working point, HV gm1 With SH gm1 It is a single-stage sleeve cascode operational amplifier with the same structure. When the multiplexing circuit works as a high-voltage feedback circuit, the clock signal Φ 1’ is a valid level, the clock signal Φ 1’ When it is a valid level, the equivalent circuit of the multiplexing circuit is as follows Fig.11 As shown, the feedback voltage is applied to the feedback plate by the positive and negative output terminals of the operational amplifier Gm2, and the feedback voltage is s3 And capacitor C s4 The sampled capacitor C d3 And capacitor C d4 For compensation capacitor.

[0128] When the multiplexing circuit works as a sample-and-hold circuit, the clock signal Φ 1’ is an invalid level, the clock signal Φ 1’ When it is an invalid level, the equivalent circuit of the multiplexing circuit is as follows Fig.12 As shown, the capacitor C s3 And capacitor C s4 The sampled feedback voltage is loaded onto the corresponding feedback plate. Compared with the previous embodiment, the multiplexing structure further reduces the circuit power consumption and layout area while realizing the high voltage feedback function and the sample and hold function.

[0129] It should be noted that the terms "first" and "second" used in the above description are only used for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The above is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the scope of protection of the present invention.

Claims

1. A time-division multiplexed three-axis accelerometer readout circuit, characterized in that: including a connected signal conditioning module and an electrostatic force feedback module; In the Nth working cycle of the readout circuit, the X-axis acceleration sensor, the Y-axis acceleration sensor and the Z-axis acceleration sensor in the three-axis accelerometer are respectively connected to the input terminal group of the signal conditioning module as the detection axis acceleration sensors, and the signal conditioning module receives the sensing signal output by the current detection axis acceleration sensor, and generates a detection signal according to the sensing signal; For any axis acceleration sensor, when the acceleration sensor is a detection axis acceleration sensor of the Nth working cycle, the electrostatic force feedback module provides a feedback voltage to the acceleration sensor according to the detection signal output by the signal conditioning module and samples the feedback voltage; When the acceleration sensor is converted from a detection axis acceleration sensor of the Nth working cycle to a non-detection axis acceleration sensor of the Nth working cycle, the electrostatic force feedback module continues to provide the acceleration sensor with the feedback voltage sampled in the Nth working cycle until the acceleration sensor serves as the detection axis acceleration sensor of the N+1th working cycle.

2. The time-division multiplexed three-axis accelerometer readout circuit according to claim 1, characterized in that: The signal conditioning module includes a CV conversion circuit, a low-pass filter and a loop compensator, and the CV conversion circuit is connected to the X-axis acceleration sensor, the Y-axis acceleration sensor and the Z-axis acceleration sensor through a first multiplexer; The CV conversion circuit includes a charge sensitive amplifier, a feedback capacitor C f1 , feedback resistor R f1 , switch SW rst1 , feedback capacitor C f2 , feedback resistor R f2 And switch SW rst2 ,in, The first differential output terminal of the first multiplexer is connected to the non-inverting input terminal of the charge sensitive amplifier, and the second differential output terminal of the first multiplexer is connected to the inverting input terminal of the charge sensitive amplifier; The non-inverting input terminal of the charge sensitive amplifier is connected via a switch SW rst1 Connected to the positive output terminal, the positive input terminal of the charge sensitive amplifier is connected to the positive output terminal through the feedback capacitor C f1 Connected with the non-inverting output terminal, the feedback resistor R f1 With the feedback capacitor C f1 in parallel; The inverting input terminal of the charge sensitive amplifier is connected via a switch SW rst2 Connected to the inverting output terminal, the inverting input terminal of the charge sensitive amplifier is connected to the inverting output terminal through the feedback capacitor C f2 Connected with the inverting output terminal, the feedback resistor R f2 With the feedback capacitor C f2 in parallel.

3. The time-division multiplexed three-axis accelerometer readout circuit according to claim 1, characterized in that: The low-pass filter is a second-order low-pass Butterworth filter, including an operational amplifier U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2, a resistor R 1’ , resistor R 2’ , resistor R 3’ , capacitor C 1’ And the capacitor C 2’ ; The non-inverting output terminal of the charge-sensitive amplifier is connected to one end of the capacitor C2, one end of the resistor R2 and one end of the resistor R3 through the resistor R1, the other end of the resistor R2 is connected to the positive output terminal of the operational amplifier U1 and one end of the capacitor C1, and the other end of the capacitor C1 is connected to the other end of the resistor R3 and the non-inverting input terminal of the operational amplifier U1; The inverting output terminal of the charge sensitive amplifier is connected to the 1’ With capacitor C 2’ One end of the resistor R 2’ One end and the resistor R 3’ One end of the resistor R 2’ The other end is connected to the operational amplifier U 1’ The positive output terminal and capacitor C 1’ One end of the capacitor C 2’ The other end of the capacitor C2 is connected to the other end of the capacitor C 1’ The other end of the resistor R 3’ The other end and the operational amplifier U 1’ The non-inverting input terminal is connected.

4. The time-division multiplexed three-axis accelerometer readout circuit according to claim 3, characterized in that: The loop compensator is used to improve the stability of the signal conditioning module, including an operational amplifier U2, a capacitor C d1 , capacitor C d2 , capacitor C f3 , capacitor C f4 , capacitor C i1 , capacitor C i2 , resistor R p1 , resistor R p2 , resistor R i1 , resistor R i2 , resistor R f3 And the resistor R f4 ,in, The positive-inverting output of operational amplifier U1 is connected to the p1 With resistor R i1 One end and capacitor C d1 One end of the capacitor C d1 And the resistor R i1 The other end is connected to the positive input of operational amplifier U2 and capacitor C f3 One end of the capacitor C f3 The other end is connected through capacitor C i1 Connected to the non-inverting output terminal of the operational amplifier U2, the resistor R f3 With capacitor C f3 in parallel; The inverting output of operational amplifier U1 is connected to the p2 With resistor R i2 One end and capacitor C d2 One end of the capacitor C d2 And the resistor R i2 The other end is connected to the inverting input of operational amplifier U2 and capacitor C f4 One end of the capacitor C f4 The other end is connected through capacitor C i2 Connected to the inverting output terminal of the operational amplifier U2, the resistor R f4 With capacitor C f4 in parallel.

5. The time-division multiplexed three-axis accelerometer readout circuit according to claim 1, characterized in that: The electrostatic force feedback module includes three feedback units, and the X-axis acceleration sensor, the Y-axis acceleration sensor and the Z-axis acceleration sensor are respectively connected to the output end group of a feedback unit; The output terminal group of the signal conditioning module is connected to the input terminal group of the second multiplexer, the second multiplexer includes three output terminal groups, and the three output terminal groups of the second multiplexer are connected to the input terminal groups of the three feedback units in a one-to-one correspondence; When the detection axis acceleration sensor is connected to the input terminal group of the signal conditioning module, the feedback unit connected to the detection axis acceleration sensor is connected to the output terminal group of the signal conditioning module through the second multiplexer.

6. The time-division multiplexed three-axis accelerometer readout circuit according to claim 5, characterized in that: The feedback unit includes a high-voltage feedback circuit, which provides a feedback voltage to the detection axis acceleration sensor when connected to the signal conditioning module. The high-voltage feedback circuit includes a variable resistor array, an operational amplifier U3, a resistor R f5 And the resistor R f6 ; The first input terminal of the feedback unit is connected to the positive input terminal of the operational amplifier U3 through a variable resistor array, and the second input terminal of the feedback unit is connected to the negative input terminal of the operational amplifier U3 through a variable resistor array; the positive input terminal of the operational amplifier U3 is connected to the negative input terminal of the operational amplifier U3 through a resistor R f5 The positive output terminal of the operational amplifier U3 is connected to the negative input terminal of the operational amplifier U3 through the resistor R f6 Connected to the inverting output terminal of operational amplifier U3.

7. The time-division multiplexed three-axis accelerometer readout circuit according to claim 6, characterized in that: The feedback unit also includes a sample-and-hold circuit; In the same feedback unit, the sampling and holding circuit samples the feedback voltage when the high-voltage feedback circuit is connected to the signal conditioning module, and provides the sampled voltage to the correspondingly connected acceleration sensor when the high-voltage feedback circuit is disconnected from the signal conditioning module; The sampling and holding circuit includes an operational amplifier U4, a switch S1, a switch S2, a switch S3, a switch S 1d , switch S 2d , switch S 1’ , switch S 2’ , switch S 3’ , switch S 1d’ , switch S 2d’ , capacitor C s1 And the capacitor C s2 ,in, The non-inverting input terminal of the operational amplifier U4 is connected to the capacitor C s1 One end of the operational amplifier U4 is connected to the capacitor C and connected to the positive output end through the switch S1. s2 One end is connected to the switch S 1’ Connected to the inverting output terminal; The capacitor C s1 The other end of the switch S2 and the switch S 1d The other end of the switch S2 is connected to the positive phase output end of the operational amplifier U4 and one end of the switch S3. 1d The other end is connected through switch S 2d Connected to the other end of switch S3; The capacitor C s2 The other end of the switch S 2’ One end and switch S 1d’ One end of the switch S 2’ The other end is connected to the inverting output of the operational amplifier U4 and the switch S 3’ One end of the switch S 1d’ The other end is connected through switch S 2d’ With switch S 3’ The other end of the connection.

8. The time-division multiplexed three-axis accelerometer readout circuit according to claim 7, characterized in that: The switch S1 and the switch S 1’ Controlled by the clock signal Φ1, the switches S2 and S 2’ , switch S3 and switch S 3’ Controlled by the clock signal Φ2, the switch S 1d And switch S 1d’ By the clock signal Φ 1d control, the switch S 2d And switch S 2d’ By the clock signal Φ 2d Inverting signal control; The clock signal Φ1 and the clock signal Φ2 are two-phase non-overlapping clock signals. 1d is the clock signal obtained after the clock signal Φ1 is delayed by a preset time t, wherein the clock signal Φ 2d It is the clock signal obtained after the clock signal Φ2 is delayed by a preset time t.

9. The time-division multiplexed three-axis accelerometer readout circuit according to claim 5, characterized in that: The feedback unit includes a multiplexing circuit, and the multiplexing circuit includes a variable resistor array, an operational amplifier HV gm1 , operational amplifier Gm2, operational amplifier SH gm1 , resistor R f7 , resistor R f8 , capacitor C d3 , capacitor C d4 , capacitor C s3 , capacitor C s4 , switch S f1 , switch S f1’ , switch S f2 , switch S f2’ , switch S f3 , switch S f3’ , switch S f4 And switch S f4’ ,in, The first input terminal of the feedback unit is connected to the operational amplifier HV through a variable resistor array. gm1 The second input terminal of the feedback unit is connected to the non-inverting input terminal of the operational amplifier HV through a variable resistor array. gm1 The inverting input terminal is connected; Operational Amplifier HV gm1 The non-inverting input terminal is connected through the resistor R f7 And switch S f2 Connected to the positive output terminal of operational amplifier Gm2, operational amplifier HV gm1 The positive phase output terminal passes through the switch S f1 connected to the non-inverting input terminal of the operational amplifier Gm2; Operational Amplifier HV gm1 The inverting input is connected through the resistor R f8 And switch S f2’ Connected to the inverting output terminal of operational amplifier Gm2, operational amplifier HV gm1 The inverting output terminal is connected to the switch S f1’ connected to the inverting input terminal of the operational amplifier Gm2; The non-inverting input of operational amplifier Gm2 is connected through switch S f3 With operational amplifier SH gm1 The positive output terminal of the operational amplifier Gm2 is connected to the negative input terminal through the switch S f3’ With operational amplifier SH gm1 The inverting output terminal is connected; The capacitor C d3 One end of the capacitor C s3 One end of the capacitor C is connected to the positive output terminal of the operational amplifier Gm2. s3 The other end of the operational amplifier SH gm1 The non-inverting input terminal is connected to the capacitor C d3 The other end is grounded; The capacitor C d4 One end of the capacitor C s4 One end of the capacitor C is connected to the inverting output terminal of the operational amplifier Gm2. s4 The other end of the operational amplifier SH gm1 The inverting input terminal is connected to the capacitor C d4 The other end is grounded; Operational Amplifier SH gm1 The non-inverting input terminal is connected through switch S f4 With operational amplifier SH gm1 The non-inverting output terminal of the operational amplifier SH gm1 The inverting input of the f4’ With operational amplifier SH gm1 The inverting output terminal is connected; Switch S f1 , switch S f1’ , switch S f2 , switch S f2’ , switch S f4 And switch S f4’ By the clock signal Φ 1’ Control, switch S f3 And switch S f3’ By the clock signal Φ 1’ The inverting signal control.

10. The time-division multiplexed three-axis accelerometer readout circuit according to claim 6 or 9, characterized in that: The variable resistor array includes a positive phase resistor array and a negative phase resistor array; The positive phase resistor array includes a positive phase initial unit and n-stage positive phase resistor units cascaded in sequence. The positive phase initial unit includes a resistor R 01 And the resistor R 02 , the positive phase resistor unit includes a positive phase first resistor, a positive phase second resistor and an active switch, the resistance value of the positive phase first resistor is 2R, and the resistance value of the positive phase second resistor is R; Resistor R 01 The first end of is connected to the first input end of the variable resistor array, and the first end of the first positive phase resistor in the positive phase resistor unit is connected to the first input end of the variable resistor array through a corresponding active switch; Resistor R 02 The first end of the resistor R 01 The second end of the resistor R 02 The second end of is connected to the second end of the first positive phase resistor in the first-stage positive phase resistor unit, the first end of the second positive phase resistor in the positive phase resistor unit is connected to the second end of the first positive phase resistor in the same-stage positive phase resistor unit, the second end of the second positive phase resistor in the positive phase resistor unit is connected to the first end of the second positive phase resistor in the next-stage positive phase resistor unit, and the second end of the second positive phase resistor in the last-stage positive phase resistor unit is connected to the first output end of the variable resistor array; The inverting resistor array includes an inverting initial unit and n-stage inverting resistor units cascaded in sequence. The inverting initial unit includes a resistor R 01’ And the resistor R 02’ , the inverting resistor unit includes an inverting first resistor, an inverting second resistor and an active switch, the resistance value of the inverting first resistor is 2R, and the resistance value of the inverting second resistor is R; Resistor R 01’ The first end of the inverting resistor is connected to the second input end of the variable resistor array, and the first end of the inverting first resistor in the inverting resistor unit is connected to the second input end of the variable resistor array through a corresponding active switch; Resistor R 02’ The first end of the resistor R 01’ The second end of the resistor R 02’ The second end of is connected to the second end of the inverted first resistor in the first-stage inverted resistor unit, the first end of the inverted second resistor in the inverted resistor unit is connected to the second end of the inverted first resistor in the same-stage inverted resistor unit, the second end of the inverted second resistor in the inverted resistor unit is connected to the first end of the inverted second resistor in the next-stage inverted resistor unit, and the second end of the inverted second resistor in the last-stage inverted resistor unit is connected to the second output end of the variable resistor array; Resistor R 01 The second end is connected in series with a resistor R 03 And the resistor R 04 With resistor R 01’ The second end of the resistor R 01 , resistor R 01’ , resistor R 03 And the resistor R 04 The resistance value is 2R, the resistor R 02 And the resistor R 02’ The resistance value is R.

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