Array substrate, preparation method thereof and electronic paper display panel

Abstract

The invention discloses an array substrate and a preparation method thereof and an electronic paper display panel, and mainly relates to the technical field of display, the array substrate is used in the electronic paper display panel with an array substrate side as a light incident surface, and the array substrate further comprises a substrate, a common electrode block and a pixel electrode block, the common electrode blocks and the pixel electrode blocks are arranged on the substrate, the array substrate comprises pixel unit areas, each pixel unit area is internally provided with the common electrode block and the pixel electrode block, projections of the common electrode blocks and the pixel electrode blocks are overlapped to form a storage capacitor, and the common electrode blocks and the pixel electrode blocks are arranged on the substrate. A hollow part is arranged on the common electrode block, and the hollow part penetrates through the common electrode block. Through the design, the light transmittance of the pixel unit area can be improved, and the brightness of the electronic paper display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and an electronic paper display panel. Background Art

[0002] With the continuous development of science and technology, the frequency of electronic digital products is increasing, and various new products are constantly being developed. Electronic paper display panels are a new type of display device, mainly used in electronic tags, billboards, electronic readers and other devices. The display effect of this electronic paper display panel is close to that of natural paper, which can reduce visual fatigue when reading.

[0003] For an electronic paper display panel whose array substrate is located on the light-emitting side of the electronic paper display panel, although the movement of electrophoretic particles can be better controlled, due to the large area of ​​the common electrode block of the electronic paper display panel, even if a transparent conductive material is used, the light transmittance in each pixel unit area of ​​the electronic paper display panel will still decrease. Summary of the invention

[0004] The purpose of the present application is to provide an array substrate and a preparation method thereof and an electronic paper display panel, so as to improve the light transmittance of a pixel unit area and improve the brightness of the electronic paper display panel.

[0005] The present application discloses an array substrate, which is used in an electronic paper display panel whose array substrate side is a light incident surface. The array substrate also includes a substrate, a common electrode block and a pixel electrode block. The common electrode block and the pixel electrode block are both arranged on the substrate. The array substrate includes a pixel unit area, and the common electrode block and the pixel electrode block are arranged in each pixel unit area. The common electrode block and the pixel electrode block are overlapped by projection to form a storage capacitor. A hollow portion is arranged on the common electrode block, and the hollow portion passes through the common electrode block.

[0006] Optionally, the pixel electrode block includes a pixel main body and a pixel extension, the pixel main body is connected to the pixel extension, the common electrode block includes a common electrode main body and a common electrode extension, the common electrode main body is connected to the common electrode extension, the hollow portion is arranged on the common electrode main body, the pixel main body and the common electrode main body are both made of light-transmitting conductive materials, the pixel main body and the common electrode main body overlap in projection to form a first sub-storage capacitor, and the pixel extension and the common electrode extension overlap in projection to form a second sub-storage capacitor; The array substrate also includes a first substrate channel and a second substrate channel, and the first substrate channel and the second substrate channel are arranged on the substrate of each pixel unit area; the common electrode extension portion is at least partially located in the second substrate channel, and the pixel extension portion is at least partially located in the first substrate channel.

[0007] Optionally, the array substrate comprises a first conductor layer, a first insulating layer, a second conductor layer, a second insulating layer, a passivation layer and a pixel electrode layer, and the first conductor layer, the first insulating layer, the second conductor layer, the second insulating layer, the passivation layer and the pixel electrode layer are sequentially stacked on the substrate; The array substrate further includes a first insulating channel and a second insulating channel, each of the pixel unit regions is provided with the first insulating channel and the second insulating channel; the first insulating channel and the second insulating channel both penetrate the first insulating layer and the second insulating layer; The pixel extension portion includes a first pixel extension portion and a second pixel extension portion, the first pixel extension portion is located in the first substrate trench, the second pixel extension portion is located in the first insulating trench, and the second pixel extension portion is connected to the first pixel extension portion and the pixel main portion; The common electrode extension portion includes a first common electrode extension portion and a second common electrode extension portion, the first common electrode extension portion is located in the second substrate channel, the second common electrode extension portion is located in the second insulating channel, and the second common electrode extension portion is connected to the first common electrode extension portion and the common electrode main portion.

[0008] Optionally, the three consecutive pixel unit regions are defined as a first pixel unit region, a second pixel unit region, and a third pixel unit region, the first pixel unit region and the third pixel unit region are respectively located on both sides of the second pixel unit region, the first pixel unit region is used to reflect red light, the second pixel unit region is used to reflect blue light, and the third pixel unit region is used to reflect green light; The common electrode main body in the first pixel unit area is defined as a first common electrode main body, the common electrode main body in the second pixel unit area is defined as a second common electrode main body, and the common electrode main body in the third pixel unit area is defined as a third common electrode main body; the hollowed-out portion on the first common electrode main body is defined as a first hollowed-out portion, the hollowed-out portion on the second common electrode main body is defined as a second hollowed-out portion, and the hollowed-out portion on the third common electrode main body is defined as a third hollowed-out portion; The area of ​​the third hollow portion is smaller than that of the first hollow portion, and the area of ​​the first hollow portion is smaller than that of the second hollow portion; the area of ​​the third common electrode main body is larger than that of the first common electrode main body, and the area of ​​the first common electrode main body is larger than that of the second common electrode main body.

[0009] Optionally, the first substrate channel is located outside the second substrate channel, and the first insulating channel is located outside the second insulating channel; the first common electrode extension portion and the second common electrode extension portion are both made of light-transmitting conductive material, and the first pixel extension portion and the second pixel extension portion are both made of light-reflective conductive material.

[0010] Optionally, the first substrate channel includes a first sub-substrate channel, a second sub-substrate channel, a third sub-substrate channel and a fourth sub-substrate channel, the first sub-substrate channel, the second sub-substrate channel, the third sub-substrate channel and the fourth sub-substrate channel are arranged at intervals and sequentially surround the periphery of the second substrate channel, a common electrode avoidance gap is formed between the first sub-substrate channel and the second sub-substrate channel, a common electrode avoidance gap is formed between the second sub-substrate channel and the third sub-substrate channel, a common electrode avoidance gap is formed between the third sub-substrate channel and the fourth sub-substrate channel, and a common electrode avoidance gap is formed between the fourth sub-substrate channel and the first sub-substrate channel; The first insulating channel includes a first sub-insulating channel, a second sub-insulating channel, a third sub-insulating channel and a fourth sub-insulating channel, the first sub-insulating channel, the second sub-insulating channel, the third sub-insulating channel and the fourth sub-insulating channel are arranged at intervals and sequentially surround the periphery of the second insulating channel, a common electrode avoidance gap is formed between the first sub-insulating channel and the second sub-insulating channel, a common electrode avoidance gap is formed between the second sub-insulating channel and the third sub-insulating channel, a common electrode avoidance gap is formed between the third sub-insulating channel and the fourth sub-insulating channel, and a common electrode avoidance gap is formed between the fourth sub-insulating channel and the first sub-insulating channel; The first sub-insulating channel, the second sub-insulating channel, the third sub-insulating channel and the fourth sub-insulating channel overlap with the orthographic projections of the first sub-substrate channel, the second sub-substrate channel, the third sub-substrate channel and the fourth sub-substrate channel respectively; The array substrate further includes a common electrode connecting segment, the common electrode connecting segment passes through the common electrode avoiding gap, and two ends of the common electrode connecting segment are respectively connected to the common electrode main bodies in two pixel unit areas adjacent to each other in the horizontal direction or in the vertical direction.

[0011] Optionally, two pixel unit regions adjacent to each other in the transverse direction or in the longitudinal direction are defined as a first pixel unit region and a second pixel unit region, and two adjacent common electrode avoidance gaps in the first pixel unit region and the second pixel unit region are staggered.

[0012] Optionally, the array substrate comprises a first conductor layer, a first insulating layer, a second conductor layer, a second insulating layer and a pixel electrode layer, and the first conductor layer, the first insulating layer, the second conductor layer, the second insulating layer and the pixel electrode layer are sequentially stacked on the substrate; The pixel main body is located in the pixel electrode layer, and the pixel extension portion passes through the second insulating layer and the first insulating layer and is connected to the pixel main body. The common electrode main body is located in the first conductor layer or in the second conductor layer.

[0013] The present application also discloses a method for preparing an array substrate, which is used to prepare the array substrate described above, and comprises the following steps: forming a common electrode block on the substrate; A hollow portion is provided on the common electrode block; A pixel electrode block is formed on the substrate.

[0014] The present application also discloses an electronic paper display panel, which includes an electronic paper reflective display layer and an array substrate. The array substrate is located on the light incident side of the electronic paper display panel and is used to drive the electronic paper reflective display layer to display images.

[0015] Compared with the existing electronic paper display panel solutions, the present application sets a hollow portion on the common electrode block, and the hollow portion runs through the common electrode block, so that external light can directly pass through the hollow portion and will not be attenuated by the common electrode block, thereby reducing the loss of light intensity by the common electrode block, thereby improving the light transmittance of each pixel unit area and enhancing the display brightness of the electronic paper display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of the present application; Figure 2is a cross-sectional schematic diagram of an array substrate according to the first embodiment of the present application; Figure 3 is a plan view of a hollow portion of the first embodiment of the present application; Figure 4 is a schematic diagram of a pixel electrode block and a common electrode block according to the first embodiment of the present application; Figure 5 is a schematic diagram of a first insulating channel and a second insulating channel of the first embodiment of the present application; Figure 6 is a schematic cross-sectional view of a substrate channel of the first embodiment of the present application; Figure 7 is a schematic diagram of a hollow portion of the first embodiment of the present application; Figure 8 It is a plan view of a common electrode avoidance gap in the first embodiment of the present application; Fig. 9 is a schematic diagram of an array substrate according to a second embodiment of the present application; Fig.10 It is a schematic diagram of a process of preparing a method for an array substrate according to an embodiment of the present application.

[0017] Among them, 10, electronic paper display panel; 20, electronic paper reflective display layer; 30, electrophoretic particle layer; 40, common electrode layer; 60, filter layer; 61, red color resistance; 62, green color resistance; 63, blue color resistance; 70, array substrate; 80, pixel unit area; 81, first pixel unit area; 82, second pixel unit area; 83, third pixel unit area; 100, substrate; 110, first conductor layer; 120, first insulating layer; 130, second conductor layer; 140, second insulating layer; 150, passivation layer; 160, pixel electrode layer; 200, common electrode block; 210, common electrode main body; 211, first common electrode main body; 212, second common electrode main body; 213, third common electrode main body; 220, common electrode extension; 221, first common electrode extension; 222, second common electrode extension; 230, hollow hollow portion; 231, first hollow portion; 232, second hollow portion; 233, third hollow portion; 240, common electrode connection segment; 300, pixel electrode block; 310, pixel main body; 320, pixel extension portion; 321, first pixel extension portion; 322, second pixel extension portion; 410, first substrate channel; 411, first sub-substrate channel; 412, second sub-substrate channel; 413, third sub-substrate channel; 414 , fourth sub-substrate channel; 420, second substrate channel; 510, first insulating channel; 520, second insulating channel; 511, first sub-insulating channel; 512, second sub-insulating channel; 513, third sub-insulating channel; 514, fourth sub-insulating channel; 610, common electrode avoidance gap; 620, insulating isolation wall; 710, data line; 720, scan line; 730, active switch; 810, first passivation channel. DETAILED DESCRIPTION

[0018] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0019] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, features defined as "first" and "second" may explicitly or implicitly include one or more of the features; "plurality" means two or more. The term "including" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may exist or be added.

[0020] In addition, terms indicating orientation or positional relationships, such as “center,” “lateral,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are described based on the orientation or relative positional relationships shown in the accompanying drawings and are merely simplified descriptions for the convenience of describing the present application. They do not indicate that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limitations on the present application.

[0021] In addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internally connected between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] The present application is described in detail below with reference to the accompanying drawings and optional embodiments.

[0023] Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of the present application, such as Figure 1 As shown, Figure 1 The direction indicated by the middle arrow represents the propagation direction of part of the light. The present application discloses an electronic paper display panel 10, which includes an electronic paper reflective display layer 20 and an array substrate 70. The array substrate 70 is located on the light incident side of the electronic paper display panel 10, and the array substrate 70 is used to drive the electronic paper reflective display layer 20 to display a picture.

[0024] The electronic paper reflective display layer 20 includes an electrophoretic particle layer 30 and a common electrode layer 40, the electrophoretic particle layer 30 includes black electrophoretic particles and white electrophoretic particles, the common electrode layer 40 is arranged on the side of the electrophoretic particle layer 30 away from the array substrate 70, and the electrophoretic particle layer 30 is arranged on the side of the pixel electrode block 300 away from the substrate 100, and an electric field is formed between the pixel electrode block 300 on the array substrate 70 and the common electrode layer 40 to drive the electrophoretic particles to move.

[0025] The electronic paper display panel 10 includes a filter layer 60 , which is disposed between the pixel electrode block 300 and the electrophoretic particle layer 30 . The filter layer 60 includes a red color resist 61 , a green color resist 62 , and a blue color resist 63 .

[0026] The present application also discloses an array substrate 70, which can be used in the electronic paper display panel 10 described above. For the array substrate 70, the present application provides the following design, which is specifically introduced through several embodiments: Embodiment 1: Figure 2 is a cross-sectional schematic diagram of an array substrate according to the first embodiment of the present application, Figure 3 is a plan view of a hollow portion of the first embodiment of the present application, combined with Figure 1-Figure 3 As shown, the present application discloses an array substrate 70, which is used in an electronic paper display panel 10 in which the array substrate 70 side is a light incident surface, and the array substrate 70 also includes a substrate 100, a common electrode block 200 and a pixel electrode block 300, and the common electrode block 200 and the pixel electrode block 300 are both arranged on the substrate 100, and the array substrate 70 includes a pixel unit area 80, and each of the pixel unit areas 80 is provided with the common electrode block 200 and the pixel electrode block 300, and the common electrode block 200 and the pixel electrode block 300 overlap by projection to form a storage capacitor, and a hollow portion 230 is provided on the common electrode block 200, and the hollow portion 230 passes through the common electrode block 200.

[0027] In the current electronic paper display panel 10 in which the array substrate 70 side is the light incident surface, although the common electrode block 200 and the pixel electrode block 300 are both made of light-transmitting conductive material, due to the large area of ​​the common electrode block 200, when the electronic paper display panel 10 is displayed, the light needs to first pass through the array substrate 70 and illuminate the electrophoretic particles of the electronic paper reflective display layer 20 below, and then be reflected by the electrophoretic particles and then pass through the array substrate 70 to be reflected out. Finally, the light used for display passes through the array substrate 70 twice, resulting in a relatively low light transmittance in each pixel unit area 80, especially for the electronic paper display panel 10 provided with a filter layer 60, the light transmittance is even lower.

[0028] Compared with the existing electronic paper display panel solutions, the present application sets a hollow portion 230 on the common electrode block 200, and the hollow portion 230 runs through the common electrode block 200, so that external light can directly pass through the hollow portion 230 and will not be attenuated by the common electrode block 200, thereby reducing the loss of light intensity by the common electrode block 200, thereby improving the light transmittance of each pixel unit area 80 and enhancing the display brightness of the electronic paper display panel 10.

[0029] The array substrate 70 includes a first conductor layer 110, a first insulating layer 120, a second conductor layer 130, a second insulating layer 140, a passivation layer 150 and a pixel electrode layer 160, and the first conductor layer 110, the first insulating layer 120, the second conductor layer 130, the second insulating layer 140, the passivation layer 150 and the pixel electrode layer 160 are stacked in sequence on the substrate 100.

[0030] The array substrate 70 further includes a data line 710, a scan line 720 and an active switch 730. The data line 710, the scan line 720 and the active switch 730 are all arranged on the substrate 100. The data line 710 and the scan line 720 are crisscrossed to define a pixel unit area 80. The scan line 720 is connected to the gate of the active switch 730, the data line 710 is connected to the source of the active switch 730, and the drain of the active switch 730 is connected to the pixel electrode block 300.

[0031] The data line 710 and the scan line 720 are arranged in different layers, that is, when the data line 710 is located on the first conductor layer 110, the scan line 720 is located on the second conductor layer 130, and when the data line 710 is located on the second conductor layer 130, the scan line 720 is located on the first conductor layer 110; and the active switch 730 can be a top gate active switch 730 or a bottom gate active switch 730.

[0032] Exemplarily, the scan line 720 of the present application is located in the first conductor layer 110 , the data line 710 is located in the second conductor layer 130 , the gate of the active switch 730 is located in the first conductor layer 110 , and the source and drain of the active switch 730 are located in the second conductor layer 130 .

[0033] When the electronic paper display panel 10 refreshes the screen, the movement speed of the electrophoretic particles is slower than the charging speed of the pixel electrode block 300. For example, when the second row is refreshed after the first row is refreshed, the electrophoretic particles on the first row of pixel electrode blocks 300 have not moved to the target position. Therefore, a larger storage capacitor is required to maintain the electrophoretic particles moving to the target position. In addition, since the operating voltage of the electronic paper display panel 10 is relatively large, for example, taking the maximum driving voltage of the data line 710 as positive or negative 15, the voltage difference between the source and drain of the active switch 730 will be relatively large, resulting in more leakage of the active switch 730. Therefore, the electronic paper display panel 10 is required to have a larger storage capacitor.

[0034] Since the hollow portion 230 is provided on the common electrode block 200, the overlapping area between the common electrode block 200 and the pixel electrode block 300 is reduced, resulting in a smaller storage capacitor formed between the pixel electrode block 300 and the common electrode block 200. This will cause the electrophoretic particles to be unable to move to the target position, resulting in display abnormalities, such as color deviation problems.

[0035] Figure 4 is a schematic diagram of a pixel electrode block and a common electrode block according to the first embodiment of the present application, such as Figure 4 As shown, the present application arranges a first substrate channel 410 and a second substrate channel 420 on the substrate 100, and then arranges the pixel extension portion 320 in the first substrate channel 410, and arranges the common electrode extension portion 220 in the second substrate channel 420, thereby increasing the overlapping area between the pixel electrode block 300 and the common electrode block 200 in the vertical direction. Specifically: The pixel electrode block 300 includes a pixel main body 310 and a pixel extension part 320, and the pixel main body 310 is connected to the pixel extension part 320. The common electrode block 200 includes a common electrode main body 210 and a common electrode extension part 220, and the common electrode main body 210 is connected to the common electrode extension part 220. The hollow part 230 is arranged on the common electrode main body 210. The pixel main body 310 and the common electrode main body 210 are both made of light-transmitting conductive materials. The pixel main body 310 and the common electrode main body 210 overlap in projection to form a first sub-storage capacitor, and the pixel extension part 320 and the common electrode extension part 220 overlap in projection to form a second sub-storage capacitor.

[0036] The array substrate 70 also includes a first substrate channel 410 and a second substrate channel 420, and the first substrate channel 410 and the second substrate channel 420 are arranged on the substrate 100 of each of the pixel unit areas 80; the common electrode extension portion 220 is at least partially located in the second substrate channel 420, and the pixel extension portion 320 is at least partially located in the first substrate channel 410.

[0037] In this embodiment, the pixel main body 310 is located in the pixel electrode layer 160, and the common electrode main body 210 is located in the first conductor layer 110. Specifically, the array substrate 70 includes a first conductor layer 110, a first insulating layer 120, a second conductor layer 130, a second insulating layer 140 and a pixel electrode layer 160. The first conductor layer 110, the first insulating layer 120, the second conductor layer 130, the second insulating layer 140 and the pixel electrode layer 160 are stacked in sequence on the substrate 100.

[0038] The pixel main body 310 is located in the pixel electrode layer 160 , and the pixel extension portion 320 penetrates the second insulating layer 140 and the first insulating layer 120 and is connected to the pixel main body 310 . The common electrode main body 210 is located in the first conductor layer 110 .

[0039] In the present application, a first substrate channel 410 and a second substrate channel 420 are arranged on the substrate 100, and then a pixel extension portion 320 is arranged in the first substrate channel 410, and a common electrode extension portion 220 is arranged in the second substrate channel 420, so that the projection overlap between the pixel main portion 310 and the common electrode main portion 210 forms a first sub-storage capacitor, and the projection overlap between the pixel extension portion 320 and the common electrode extension portion 220 forms a second sub-storage capacitor, thereby increasing the size of the storage capacitor in each pixel unit area 80, avoiding the color deviation problem of the electronic paper display panel 10, and improving the display effect of the display panel.

[0040] Figure 5 is a schematic diagram of a first insulating channel and a second insulating channel of the first embodiment of the present application, such as Figure 5 As shown, in order to further increase the size of the second storage capacitor, the present application also provides a first insulating channel 510 and a second insulating channel 520, and the first pixel extension portion 321 of the pixel extension portion 320 is provided in the first substrate channel 410, the second pixel extension portion 322 of the pixel extension portion 320 is provided in the first insulating channel 510, and the first common electrode extension portion 221 of the common electrode extension portion 220 is provided in the second substrate channel 420, and the second common electrode extension portion 222 is provided in the second insulating channel 520.

[0041] In other words, the second pixel extension portion 322 and the second common electrode extension portion 222 are formed by disposing the first insulating channel 510 and the second insulating channel 520 on the first insulating layer 120 and the second insulating layer 140 and then filling the first insulating channel 510 and the second insulating channel 520 with conductive materials.

[0042] Specifically, the array substrate 70 includes a first conductor layer 110, a first insulating layer 120, a second conductor layer 130, a second insulating layer 140, a passivation layer 150 and a pixel electrode layer 160, and the first conductor layer 110, the first insulating layer 120, the second conductor layer 130, the second insulating layer 140, the passivation layer 150 and the pixel electrode layer 160 are stacked in sequence on the substrate 100.

[0043] The array substrate 70 further includes a first insulating channel 510 and a second insulating channel 520 , and each of the pixel unit regions 80 is provided with the first insulating channel 510 and the second insulating channel 520 ; the first insulating channel 510 and the second insulating channel 520 both penetrate the first insulating layer 120 and the second insulating layer 140 .

[0044] The pixel extension portion 320 includes a first pixel extension portion 321 and a second pixel extension portion 322 . The first pixel extension portion 321 is located in the first substrate channel 410 , the second pixel extension portion 322 is located in the first insulating channel 510 , and the second pixel extension portion 322 is connected to the first pixel extension portion 321 and the pixel main portion 310 .

[0045] The common electrode extension portion 220 includes a first common electrode extension portion 221 and a second common electrode extension portion 222 . The first common electrode extension portion 221 is located in the second substrate channel 420 , the second common electrode extension portion 222 is located in the second insulating channel 520 , and the second common electrode extension portion 222 is connected to the first common electrode extension portion 221 and the common electrode main body 210 .

[0046] Since the overlapping area between the second pixel extension portion 322 and the second common electrode extension portion 222 is increased, the size of the second storage capacitor is increased, thereby further increasing the total storage capacitor size in each pixel unit region 80 .

[0047] Moreover, by increasing the overlapping area between the first pixel extension portion 321 and the first common electrode extension portion 221, as well as the overlapping area between the second pixel extension portion 322 and the second common electrode extension portion 222, even if a hollow portion 230 is provided on the common electrode block 200, the overlapping area between the common electrode block 200 and the pixel electrode block 300 will not be reduced, and the storage capacitance will not be reduced.

[0048] Exemplarily, the depth of the first substrate channel 410 and the second substrate channel 420 is greater than or equal to 10 um and less than or equal to 100 um; the width of the first substrate channel 410 and the second substrate channel 420 is greater than or equal to 5 um, and the thickness of the substrate is 0.5 mm.

[0049] Furthermore, the orthographic projection of the first insulating channel 510 coincides with the orthographic projection of the first substrate channel 410; the orthographic projection of the second insulating channel 520 coincides with the orthographic projection of the second substrate channel 420. This can avoid the first pixel extension 321 and the second pixel extension 322 being misaligned and unable to be connected together, and the first common electrode extension 221 and the second common electrode extension 222 being misaligned and unable to be connected together; it can also avoid the orthographic projection area of ​​the pixel extension 320 and the common electrode extension 220 on the substrate 100 being too large, resulting in excessive loss of light intensity, thereby avoiding a reduction in light transmittance of each pixel unit area 80.

[0050] Secondly, one mask can be used to set the first substrate channel 410, the second substrate channel 420, the first insulating channel 510 and the second insulating channel 520, thereby saving the preparation cost.

[0051] Figure 6 is a cross-sectional schematic diagram of a substrate channel of the first embodiment of the present application, combined with Figure 6 As shown, the substrate 100 is a glass substrate 100, the material of the glass substrate 100 is silicon dioxide, the materials of the first insulating layer 120 and the second insulating layer 140 are silicon nitride, and the dielectric constant of the substrate 100 is smaller than the dielectric constant of the first insulating layer 120 and the second insulating layer 140. Since the operating voltage of the electronic paper display panel 10 is relatively large, there is a risk of breakdown between the first pixel extension portion 321 and the first common electrode extension portion 221 on the first substrate channel 410.

[0052] Therefore, the present application also sets an insulating isolation wall 620 between the first substrate channel 410 and the second substrate channel 420. The material of the insulating isolation wall 620 is an insulating material. Specifically, an insulating isolation wall 620 is set between the first substrate channel 410 and the second substrate channel 420. The material of the insulating isolation wall 620 is the same as the material of the first insulating layer 120 and the material of the second insulating layer 140. The spacing between the first common electrode extension portion 221 and the first pixel extension portion 321 is equal to the spacing between the second common electrode extension portion 222 and the second pixel extension portion 322.

[0053] Since the insulating isolation wall 620 has the same dielectric constant as the first insulating layer 120 and the second insulating layer 140, it can ensure that the distance between the second common electrode extension portion 222 and the second pixel extension portion 322 is as small as the distance between the first common electrode extension portion 221 and the first pixel extension portion 321, thereby further increasing the size of the storage capacitor and avoiding the risk of breakdown between the first common electrode extension portion 221 and the first pixel extension portion 321.

[0054] Figure 7 is a schematic diagram of a hollow portion of the first embodiment of the present application, Figure 8 is a plan view of a common electrode avoidance gap of the first embodiment of the present application, combined with Figure 7 and Figure 8 As shown, Figure 7 The direction indicated by the middle arrow is the propagation direction of part of the light. The three consecutive pixel unit areas 80 are defined as a first pixel unit area 81, a second pixel unit area 82 and a third pixel unit area 83. The first pixel unit area 81 and the third pixel unit area 83 are respectively located on both sides of the second pixel unit area 82. The first pixel unit area 81 is used to reflect red light, the second pixel unit area 82 is used to reflect blue light, and the third pixel unit area 83 is used to reflect green light.

[0055] The common electrode main body 210 in the first pixel unit area 81 is defined as a first common electrode main body 211, the common electrode main body 210 in the second pixel unit area 82 is defined as a second common electrode main body 212, and the common electrode main body 210 in the third pixel unit area 83 is defined as a third common electrode main body 213; the hollow portion 230 on the first common electrode main body 211 is defined as a first hollow portion 231, the hollow portion 230 on the second common electrode main body 212 is defined as a second hollow portion 232, and the hollow portion 230 on the third common electrode main body 213 is defined as a third hollow portion 233.

[0056] The area of ​​the third hollow portion 233 is smaller than the area of ​​the first hollow portion 231, and the area of ​​the first hollow portion 231 is smaller than the area of ​​the second hollow portion 232; the area of ​​the third common electrode main body 213 is larger than the area of ​​the first common electrode main body 211, and the area of ​​the first common electrode main body 211 is larger than the area of ​​the second common electrode main body 212.

[0057] Since the light transmittances of the green color resist 62, the red color resist 61, and the blue color resist 63 decrease in sequence, the area of ​​the third hollow portion 233 is smaller than the area of ​​the first hollow portion 231, and the area of ​​the first hollow portion 231 is smaller than the area of ​​the second hollow portion 232, so that the light transmittances of the third pixel unit area 83, the second pixel unit area 82, and the first pixel unit area 81 can be balanced, thereby avoiding the phenomenon that when the electronic paper display panel 10 displays a picture, the first pixel unit area 81, the second pixel unit area 82, and the third pixel unit area 83 of the array substrate 70 have the same transmittance, resulting in different output light intensities under the same driving voltage from the first pixel unit area 81, the second pixel unit area 82, and the third pixel unit area 83 of the electronic paper display panel 10, resulting in an abnormal picture.

[0058] The red color resist 61 of the electronic paper display panel 10 is located in the first pixel unit area 81 , the blue color resist 63 is located in the second pixel unit area 82 , and the green color resist 62 is located in the third pixel unit area 83 .

[0059] See also Figure 8 The first substrate channel 410 of the present application includes a first sub-substrate channel 411, a second sub-substrate channel 412, a third sub-substrate channel 413 and a fourth sub-substrate channel 414. The first sub-substrate channel 411, the second sub-substrate channel 412, the third sub-substrate channel 413 and the fourth sub-substrate channel 414 are arranged at intervals and sequentially surround the periphery of the second substrate channel 420. A common electrode avoidance gap 610 is formed between the first sub-substrate channel 411 and the second sub-substrate channel 412, a common electrode avoidance gap 610 is formed between the second sub-substrate channel 412 and the third sub-substrate channel 413, a common electrode avoidance gap 610 is formed between the third sub-substrate channel 413 and the fourth sub-substrate channel 414, and a common electrode avoidance gap 610 is formed between the fourth sub-substrate channel 414 and the first sub-substrate channel 411.

[0060] The first insulating channel 510 includes a first sub-insulating channel 511, a second sub-insulating channel 512, a third sub-insulating channel 513 and a fourth sub-insulating channel 514. The first sub-insulating channel 511, the second sub-insulating channel 512, the third sub-insulating channel 513 and the fourth sub-insulating channel 514 are arranged at intervals and surround the periphery of the second insulating channel 520 in sequence. A common electrode avoidance gap 610 is formed between the first sub-insulating channel 511 and the second sub-insulating channel 512, a common electrode avoidance gap 610 is formed between the second sub-insulating channel 512 and the third sub-insulating channel 513, a common electrode avoidance gap 610 is formed between the third sub-insulating channel 513 and the fourth sub-insulating channel 514, and a common electrode avoidance gap 610 is formed between the fourth sub-insulating channel 514 and the first sub-insulating channel 511.

[0061] The first sub-insulating channel 511, the second sub-insulating channel 512, the third sub-insulating channel 513 and the fourth sub-insulating channel 514 overlap with the orthographic projections of the first sub-substrate channel 411, the second sub-substrate channel 412, the third sub-substrate channel 413 and the fourth sub-substrate channel 414, respectively.

[0062] That is, the orthographic projections of the first sub-insulating channel 511 and the first sub-substrate channel 411 overlap, the orthographic projections of the second sub-insulating channel 512 and the second sub-substrate channel 412 overlap, the orthographic projections of the third sub-insulating channel 513 and the third sub-substrate channel 413 overlap, and the orthographic projections of the fourth sub-insulating channel 514 and the fourth sub-substrate channel 414 overlap.

[0063] The array substrate 70 further includes a common electrode connecting segment 240 , which passes through the common electrode avoiding gap 610 , and two ends of the common electrode connecting segment 240 are respectively connected to the common electrode main bodies 210 in two pixel unit areas 80 adjacent to each other in the horizontal direction or in the vertical direction.

[0064] The scan line 720 of the present application is located in the first conductor layer 110, the data line 710 is located in the second conductor layer 130, and the common electrode connecting segment 240 is located on the first conductor layer 110, and connects two adjacent common electrode main bodies 210 in the same row parallel to the length direction of the scan line 720; when the data line 710 is located in the first conductor layer 110 and the scan line 720 is located in the second conductor layer 130, the common electrode connecting segment 240 is located on the first conductor layer 110, and connects two adjacent common electrode main bodies 210 in the same column parallel to the length direction of the data line 710.

[0065] Common electrode avoidance gaps 610 are reserved around the common electrode main body 210, so that the common electrode connecting section 240 can be located on the upper and lower sides or the left and right sides of the common electrode main body 210 according to the specific positions of the scan lines 720 and the data lines 710, thereby improving adaptability.

[0066] The second substrate channel 420 is an annular channel, the second insulating channel 520 is an annular channel, and the orthographic projection of the second insulating channel 520 on the substrate 100 coincides with the orthographic projection of the second substrate channel 420 on the substrate 100. Thus, the overlapping area between the pixel extension portion 320 and the common electrode extension portion 220 is increased, thereby further increasing the size of the storage capacitor.

[0067] In addition, the first substrate channel 410 is located on the outside of the second substrate channel 420, and the first insulating channel 510 is located on the outside of the second insulating channel 520; the first common electrode extension portion 221 and the second common electrode extension portion 222 are both made of light-transmitting conductive materials, such as indium tin oxide materials, and the first pixel extension portion 321 and the second pixel extension portion 322 are both made of light-reflective conductive materials, such as metal copper, aluminum materials, etc.

[0068] In this way, after the external light is irradiated on the first pixel extension part 321, it will be reflected by the pixel extension part 320 to the electronic paper reflective display layer 20 below, thereby improving the degree of light convergence, improving the contrast of the electronic paper display panel 10, and improving the display effect.

[0069] Moreover, the two pixel unit areas 80 adjacent to each other in the horizontal or vertical direction are defined as a first pixel unit area 81 and a second pixel unit area 82, and the two adjacent common electrode avoidance gaps 610 in the first pixel unit area 81 and the second pixel unit area 82 are staggered. In other words, the two common electrode avoidance gaps 610 close to each other in the two pixel unit areas 80 adjacent to each other in the horizontal or vertical direction are not opposite, that is, when folded with the centers of the two pixel unit areas 80 as the axis of symmetry, the common electrode avoidance gap 610 on the left and the common electrode avoidance gap 610 on the right will not overlap.

[0070] To prevent light in the first pixel unit area 81 from irradiating the second pixel unit area 82 through the common electrode avoidance gap 610, when the light originally entering the first pixel unit area 81 irradiates the common electrode avoidance gap 610 in the first pixel unit area 81, it will irradiate the pixel extension portion 320 of the second pixel unit area 82, and then be reflected back to the first pixel unit area 81 by the pixel extension portion 320, thereby further improving the degree of light convergence and improving the contrast of the electronic paper display panel 10.

[0071] Moreover, the second pixel extension portion 322 can be directly connected to the pixel main body portion 310 through a via. Preferably, the present application provides a first passivation channel 810 with the same shape as the first insulating channel 510 on the passivation layer 150, that is, the orthographic projection of the first passivation channel 810 on the substrate 100 coincides with the orthographic projection of the first insulating channel 510 on the substrate 100, and the first passivation channel 810 is filled with a reflective conductive material to connect the pixel main body portion 310 and the pixel extension portion 320. In this way, whether the first insulating layer 120, the second insulating layer 140 or the passivation layer 150 is filled with a reflective conductive material, the light propagating from the common electrode avoidance gap 610 of the first pixel unit area 81 to the second pixel unit area 82 can be reflected back into the first pixel unit area 81.

[0072] Since the area of ​​the third hollow portion 233 is smaller than the area of ​​the first hollow portion 231, and the area of ​​the first hollow portion 231 is smaller than the area of ​​the second hollow portion 232, the overlapping area between the common electrode main portion 210 and the pixel main portion 310 in the third pixel unit area 83 will be larger than the overlapping area between the common electrode main portion 210 and the pixel main portion 310 in the first pixel unit area 81, and the overlapping area between the common electrode main portion 210 and the pixel main portion 310 in the first pixel unit area 81 will be larger than the overlapping area between the common electrode main portion 210 and the pixel main portion 310 in the second pixel unit area 82, which will result in different sizes of storage capacitors in the first pixel unit area 81, the second pixel unit area 82 and the third pixel unit area 83.

[0073] Therefore, the present application sets the total distance of the common electrode avoidance gap 610 in the third pixel unit area 83 to be greater than the total distance of the common electrode avoidance gap 610 in the first pixel unit area 81, and the total distance of the common electrode avoidance gap 610 in the first pixel unit area 81 is greater than the total distance of the common electrode avoidance gap 610 in the second pixel unit area 82, so that the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 in the third pixel unit area 83 is smaller than the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 in the first pixel unit area 81, and the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 in the first pixel unit area 81 is smaller than the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 in the second pixel unit area 82. 320, so that the overlapping area between the common electrode main portion 210 and the pixel main portion 310 in the first pixel unit area 81 plus the sum of the overlapping areas of the common electrode extension portion 220 and the pixel extension portion 320, the overlapping area between the common electrode main portion 210 and the pixel main portion 310 in the second pixel unit area 82 plus the sum of the overlapping areas of the common electrode extension portion 220 and the pixel extension portion 320, and the overlapping area between the common electrode main portion 210 and the pixel main portion 310 in the third pixel unit area 83 are all equal, so that the storage capacitors in the first pixel unit area 81, the second pixel unit area 82 and the third pixel unit area 83 are the same in size, thereby avoiding display abnormalities.

[0074] Embodiment 2: Fig. 9 is a schematic diagram of an array substrate according to a second embodiment of the present application. Fig. 9As shown, different from the first embodiment, the common electrode main body 210 of this embodiment is located in the second conductor layer 130. Specifically, the array substrate 70 includes a first conductor layer 110, a first insulating layer 120, a second conductor layer 130, a second insulating layer 140 and a pixel electrode layer 160. The first conductor layer 110, the first insulating layer 120, the second conductor layer 130, the second insulating layer 140 and the pixel electrode layer 160 are stacked in sequence on the substrate 100.

[0075] The pixel main body 310 is located in the pixel electrode layer 160 , and the pixel extension portion 320 penetrates the second insulating layer 140 and the first insulating layer 120 and is connected to the pixel main body 310 . The common electrode main body 210 is located in the second conductor layer 130 .

[0076] Compared with the solution of the first embodiment, this embodiment reduces the distance between the common electrode body 210 and the pixel body 310 by locating the common electrode body 210 in the second conductor layer 130, thereby increasing the size of the storage capacitor of each pixel unit area 80.

[0077] Moreover, the scan line 720 of the present application is located in the first conductor layer 110, the data line 710 is located in the second conductor layer 130, and the common electrode connecting segment 240 of this embodiment is located on the second conductor layer 130, connecting two adjacent common electrode main bodies 210 in the same column parallel to the length direction of the data line 710; when the data line 710 is located in the first conductor layer 110 and the scan line 720 is located in the second conductor layer 130, the common electrode connecting segment 240 is located on the second conductor layer 130, and connects two adjacent common electrode main bodies 210 in the same row parallel to the length direction of the scan line 720.

[0078] Fig.10 FIG. 1 is a schematic diagram of a process of manufacturing an array substrate according to an embodiment of the present application. Fig.10 As shown, the present application also discloses a method for preparing an array substrate 70. The method for preparing an array substrate 70 is used to prepare the array substrate 70, and the steps include: S1: forming a common electrode block on the substrate; S2: Opening a hollow portion on the common electrode block; S3: forming a pixel electrode block on the substrate.

[0079] Wherein, S1: the step of forming a common electrode block on the substrate comprises: S11: forming a first substrate channel and a second substrate channel on the substrate; S12: forming a first conductor layer on the substrate, and patterning to form a common electrode block, and filling the first substrate channel and the second substrate channel with a conductive material, wherein the common electrode block comprises a common electrode main portion, a first common electrode extension portion and a second common electrode extension portion, and the conductive material in the second substrate channel forms the first common electrode extension portion; Step S2: opening a hollow portion on the common electrode block includes: S21: opening a hollow portion on the common electrode block, and the hollow portion is arranged on the common electrode main body; Step S3: forming a pixel electrode block on the substrate comprises: S31: forming a first insulating layer, a second conductive layer, and a second insulating layer in sequence on the common electrode block; S32: forming a first insulating channel and a second insulating channel on the second insulating layer and the first insulating layer; S33: filling the first insulating trench and the second insulating trench with a conductive material, wherein the conductive material filled in the second insulating trench forms the second common electrode extension portion, and the second common electrode extension portion is connected to the first common electrode extension portion and the common electrode main portion; S34: forming the passivation layer on the second insulating layer; S35: A pixel electrode layer is formed on the second insulating layer, and a pixel electrode block is patterned, wherein the pixel electrode block includes a pixel main portion, a first pixel extension portion, and a second pixel extension portion, wherein the conductive material in the first substrate channel forms the first pixel extension portion, and the conductive material filled in the first insulating channel forms the second pixel extension portion, and the second pixel extension portion is connected to the first pixel extension portion and the pixel main portion.

[0080] Compared with the existing electronic paper display panel 10 solution, the present application sets a hollow portion 230 on the common electrode block 200, and the hollow portion 230 runs through the common electrode block 200, so that external light can directly pass through the hollow portion 230, thereby reducing the loss of light intensity by the common electrode block 200, improving the light transmittance of each pixel unit area 80, and improving the display brightness of the electronic paper display panel 10.

[0081] It should be noted that the limitations on the various steps involved in this solution, without affecting the implementation of the specific solution, are not deemed to limit the order of the steps. The steps written in front can be executed first, or later, or even simultaneously. As long as this solution can be implemented, it should be deemed to fall within the scope of protection of this application.

[0082] It should be noted that the inventive concept of the present application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effects will be enhanced.

[0083] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: The array substrate is used in an electronic paper display panel whose array substrate side is a light incident surface. The array substrate also includes a substrate, a common electrode block and a pixel electrode block. The common electrode block and the pixel electrode block are both arranged on the substrate. The array substrate includes a pixel unit area. The common electrode block and the pixel electrode block are arranged in each pixel unit area. The common electrode block and the pixel electrode block are overlapped by projection to form a storage capacitor. A hollow portion is arranged on the common electrode block, and the hollow portion passes through the common electrode block.

2. The array substrate according to claim 1, characterized in that: The pixel electrode block comprises a pixel main body and a pixel extension part, wherein the pixel main body is connected to the pixel extension part, the common electrode block comprises a common electrode main body and a common electrode extension part, wherein the common electrode main body is connected to the common electrode extension part, the hollow part is arranged on the common electrode main body part, the pixel main body part and the common electrode main body part are both made of light-transmitting conductive materials, the pixel main body part and the common electrode main body part overlap in projection to form a first sub-storage capacitor, and the pixel extension part and the common electrode extension part overlap in projection to form a second sub-storage capacitor; The array substrate further comprises a first substrate channel and a second substrate channel, and the first substrate channel and the second substrate channel are disposed on the substrate of each pixel unit area; The pixel extension portion is at least partially located in the first substrate trench, and the common electrode extension portion is at least partially located in the second substrate trench.

3. The array substrate according to claim 2, characterized in that: The array substrate comprises a first conductor layer, a first insulating layer, a second conductor layer, a second insulating layer, a passivation layer and a pixel electrode layer, wherein the first conductor layer, the first insulating layer, the second conductor layer, the second insulating layer, the passivation layer and the pixel electrode layer are sequentially stacked on the substrate; The array substrate further includes a first insulating channel and a second insulating channel, each of the pixel unit regions is provided with the first insulating channel and the second insulating channel; the first insulating channel and the second insulating channel both penetrate the first insulating layer and the second insulating layer; The pixel extension portion includes a first pixel extension portion and a second pixel extension portion, the first pixel extension portion is located in the first substrate trench, the second pixel extension portion is located in the first insulating trench, and the second pixel extension portion is connected to the first pixel extension portion and the pixel main portion; The common electrode extension portion includes a first common electrode extension portion and a second common electrode extension portion, the first common electrode extension portion is located in the second substrate channel, the second common electrode extension portion is located in the second insulating channel, and the second common electrode extension portion is connected to the first common electrode extension portion and the common electrode main portion.

4. The array substrate according to claim 3, characterized in that: The three consecutive pixel unit regions are defined as a first pixel unit region, a second pixel unit region and a third pixel unit region, wherein the first pixel unit region and the third pixel unit region are respectively located on both sides of the second pixel unit region, the first pixel unit region is used to reflect red light, the second pixel unit region is used to reflect blue light, and the third pixel unit region is used to reflect green light; defining the common electrode main body in the first pixel unit area as a first common electrode main body, defining the common electrode main body in the second pixel unit area as a second common electrode main body, and defining the common electrode main body in the third pixel unit area as a third common electrode main body; The hollow portion on the first common electrode main body is defined as a first hollow portion, the hollow portion on the second common electrode main body is defined as a second hollow portion, and the hollow portion on the third common electrode main body is defined as a third hollow portion; The area of ​​the third hollow portion is smaller than that of the first hollow portion, and the area of ​​the first hollow portion is smaller than that of the second hollow portion; the area of ​​the third common electrode main body is larger than that of the first common electrode main body, and the area of ​​the first common electrode main body is larger than that of the second common electrode main body.

5. The array substrate according to claim 4, characterized in that: The first substrate channel is located outside the second substrate channel, and the first insulating channel is located outside the second insulating channel; the first common electrode extension portion and the second common electrode extension portion are both made of light-transmitting conductive material, and the first pixel extension portion and the second pixel extension portion are both made of light-reflecting conductive material.

6. The array substrate according to claim 5, characterized in that: The first substrate channel includes a first sub-substrate channel, a second sub-substrate channel, a third sub-substrate channel and a fourth sub-substrate channel, the first sub-substrate channel, the second sub-substrate channel, the third sub-substrate channel and the fourth sub-substrate channel are arranged at intervals and sequentially surround the periphery of the second substrate channel, a common electrode avoidance gap is formed between the first sub-substrate channel and the second sub-substrate channel, a common electrode avoidance gap is formed between the second sub-substrate channel and the third sub-substrate channel, a common electrode avoidance gap is formed between the third sub-substrate channel and the fourth sub-substrate channel, and a common electrode avoidance gap is formed between the fourth sub-substrate channel and the first sub-substrate channel; The first insulating channel includes a first sub-insulating channel, a second sub-insulating channel, a third sub-insulating channel and a fourth sub-insulating channel, the first sub-insulating channel, the second sub-insulating channel, the third sub-insulating channel and the fourth sub-insulating channel are arranged at intervals and sequentially surround the periphery of the second insulating channel, a common electrode avoidance gap is formed between the first sub-insulating channel and the second sub-insulating channel, a common electrode avoidance gap is formed between the second sub-insulating channel and the third sub-insulating channel, a common electrode avoidance gap is formed between the third sub-insulating channel and the fourth sub-insulating channel, and a common electrode avoidance gap is formed between the fourth sub-insulating channel and the first sub-insulating channel; The first sub-insulating channel, the second sub-insulating channel, the third sub-insulating channel and the fourth sub-insulating channel overlap with the orthographic projections of the first sub-substrate channel, the second sub-substrate channel, the third sub-substrate channel and the fourth sub-substrate channel respectively; The array substrate further includes a common electrode connecting segment, the common electrode connecting segment passes through the common electrode avoiding gap, and two ends of the common electrode connecting segment are respectively connected to the common electrode main bodies in two pixel unit areas adjacent to each other in the horizontal direction or in the vertical direction.

7. The array substrate according to claim 6, characterized in that: The two pixel unit regions adjacent in the horizontal direction or in the vertical direction are defined as a first pixel unit region and a second pixel unit region, and the two adjacent common electrode avoidance gaps in the first pixel unit region and the second pixel unit region are staggered.

8. The array substrate according to claim 2, characterized in that: The array substrate comprises a first conductor layer, a first insulating layer, a second conductor layer, a second insulating layer and a pixel electrode layer, wherein the first conductor layer, the first insulating layer, the second conductor layer, the second insulating layer and the pixel electrode layer are sequentially stacked on the substrate; The pixel main body is located in the pixel electrode layer, and the pixel extension portion passes through the second insulating layer and the first insulating layer and is connected to the pixel main body. The common electrode main body is located in the first conductor layer or in the second conductor layer.

9. A method for preparing an array substrate, characterized in that: The method for preparing the array substrate is used to prepare the array substrate as described in any one of claims 1 to 8, and the steps include: forming a common electrode block on the substrate; A hollow portion is provided on the common electrode block; A pixel electrode block is formed on the substrate.

10. An electronic paper display panel, characterized in that: The electronic paper display panel comprises an electronic paper reflective display layer and an array substrate as described in any one of claims 1 to 8, wherein the array substrate is located on the light incident side of the electronic paper display panel, and the array substrate is used to drive the electronic paper reflective display layer to display a picture.

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