Array substrate, method for preparing same, and electronic paper display panel

Abstract

The present application discloses an array substrate, a preparation method thereof, and an electronic paper display panel, mainly relating to the field of display technologies. The array substrate is used in an electronic paper display panel with the light incident surface on the side of the array substrate. The array substrate further includes a substrate, a common electrode block, and a pixel electrode block. The common electrode block and the pixel electrode block are both disposed on the substrate. The array substrate includes a pixel unit area, and the common electrode block and the pixel electrode block are both disposed in each pixel unit area. A storage capacitor is formed by the projection overlap between the common electrode block and the pixel electrode block. A hollowed-out portion is provided on the common electrode block, and the hollowed-out portion penetrates through the common electrode block. Through the above design, the light transmittance of the pixel unit area can be improved, and the brightness of the electronic paper display panel can be increased.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to an array substrate, a preparation method thereof, and an electronic paper display panel. Background Art

[0002] With the continuous development of technology, the frequency of replacement of electronic digital products is getting higher and higher, and various new products are also continuously developed. The electronic paper display panel is a new type of display device, mainly used in devices such as electronic tags, billboards, and e-readers. The display effect of this electronic paper display panel is close to that of natural paper, which can reduce visual fatigue during reading.

[0003] For an electronic paper display panel with the array substrate on the light-emitting side, although the movement of electrophoretic particles can be well controlled, due to the large area of the common electrode block of the electronic paper display panel, even if a light-transmissive conductive material is used, it will still cause a decrease in the light transmittance in each pixel unit area of the electronic paper display panel. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate, a preparation method thereof, and an electronic paper display panel, which can improve the light transmittance of the pixel unit area and the brightness of the electronic paper display panel.

[0005] This application discloses an array substrate, which is used in an electronic paper display panel with the array substrate side as the light-incident surface. The array substrate further includes a substrate, a common electrode block, and a pixel electrode block. The common electrode block and the pixel electrode block are both disposed on the substrate. The array substrate includes pixel unit areas, and both the common electrode block and the pixel electrode block are disposed in each pixel unit area. A storage capacitor is formed by the projection overlap between the common electrode block and the pixel electrode block. A hollow portion is provided on the common electrode block, and the hollow portion penetrates through the common electrode block.

[0006] Optionally, the pixel electrode block includes a pixel main body portion and a pixel extension portion, the pixel main body portion is connected to the pixel extension portion, the common electrode block includes a common electrode main body portion and a common electrode extension portion, the common electrode main body portion is connected to the common electrode extension portion, the hollow portion is provided on the common electrode main body portion, both the pixel main body portion and the common electrode main body portion are light-transmissive conductive materials, a first sub-storage capacitor is formed by the projection overlap between the pixel main body portion and the common electrode main body portion, and a second sub-storage capacitor is formed by the projection overlap between the pixel extension portion and the common electrode extension portion;

[0007] The array substrate further includes a first substrate channel and a second substrate channel, and the first substrate channel and the second substrate channel are disposed on the substrate of each pixel unit region; at least a part of the common electrode extension is located in the second substrate channel, and at least a part of the pixel extension is located in the first substrate channel.

[0008] Optionally, the array substrate includes a first conductor layer, a first insulating layer, a second conductor layer, a second insulating layer, a passivation layer, and a pixel electrode layer, and the first conductor layer, the first insulating layer, the second conductor layer, the second insulating layer, the passivation layer, and the pixel electrode layer are sequentially stacked on the substrate;

[0009] The array substrate further includes a first insulating channel and a second insulating channel, and the first insulating channel and the second insulating channel are disposed in each pixel unit region; both the first insulating channel and the second insulating channel penetrate through the first insulating layer and the second insulating layer;

[0010] The pixel extension includes a first pixel extension and a second pixel extension, the first pixel extension is located in the first substrate channel, the second pixel extension is located in the first insulating channel, and the second pixel extension is connected to the first pixel extension and the pixel main body;

[0011] The common electrode extension includes a first common electrode extension and a second common electrode extension, the first common electrode extension is located in the second substrate channel, the second common electrode extension is located in the second insulating channel, and the second common electrode extension is connected to the first common electrode extension and the common electrode main body.

[0012] Optionally, three consecutive pixel unit regions are defined as a first pixel unit region, a second pixel unit region, and a third pixel unit region. The first pixel unit region and the third pixel unit region are respectively located on both sides of the second pixel unit region. The first pixel unit region is used to reflect red light, the second pixel unit region is used to reflect blue light, and the third pixel unit region is used to reflect green light;

[0013] The common electrode main body in the first pixel unit region is defined as a first common electrode main body, the common electrode main body in the second pixel unit region is defined as a second common electrode main body, and the common electrode main body in the third pixel unit region is defined as a third common electrode main body; the hollowed-out part on the first common electrode main body is defined as a first hollowed-out part, the hollowed-out part on the second common electrode main body is defined as a second hollowed-out part, and the hollowed-out part on the third common electrode main body is defined as a third hollowed-out part;

[0014] The area of the third hollow portion is smaller than that of the first hollow portion, and the area of the first hollow portion is smaller than that of the second hollow portion; the area of the third common electrode main body portion is larger than that of the first common electrode main body portion, and the area of the first common electrode main body portion is larger than that of the second common electrode main body portion.

[0015] Optionally, the first substrate channel is located outside the second substrate channel, and the first insulating channel is located outside the second insulating channel; both the first common electrode extension portion and the second common electrode extension portion are made of a light-transmitting conductive material, and both the first pixel extension portion and the second pixel extension portion are made of a light-reflecting conductive material.

[0016] Optionally, the first substrate channel includes a first sub-substrate channel, a second sub-substrate channel, a third sub-substrate channel, and a fourth sub-substrate channel. The first sub-substrate channel, the second sub-substrate channel, the third sub-substrate channel, and the fourth sub-substrate channel are arranged at intervals and sequentially surround the periphery of the second substrate channel. A common electrode avoidance notch is formed between the first sub-substrate channel and the second sub-substrate channel, a common electrode avoidance notch is formed between the second sub-substrate channel and the third sub-substrate channel, a common electrode avoidance notch is formed between the third sub-substrate channel and the fourth sub-substrate channel, and a common electrode avoidance notch is formed between the fourth sub-substrate channel and the first sub-substrate channel;

[0017] The first insulating channel includes a first sub-insulating channel, a second sub-insulating channel, a third sub-insulating channel, and a fourth sub-insulating channel. The first sub-insulating channel, the second sub-insulating channel, the third sub-insulating channel, and the fourth sub-insulating channel are arranged at intervals and sequentially surround the periphery of the second insulating channel. A common electrode avoidance notch is formed between the first sub-insulating channel and the second sub-insulating channel, a common electrode avoidance notch is formed between the second sub-insulating channel and the third sub-insulating channel, a common electrode avoidance notch is formed between the third sub-insulating channel and the fourth sub-insulating channel, and a common electrode avoidance notch is formed between the fourth sub-insulating channel and the first sub-insulating channel;

[0018] The first sub-insulating channel, the second sub-insulating channel, the third sub-insulating channel, and the fourth sub-insulating channel respectively overlap with the orthographic projections of the first sub-substrate channel, the second sub-substrate channel, the third sub-substrate channel, and the fourth sub-substrate channel;

[0019] The array substrate further includes a common electrode connection segment. The common electrode connection segment passes through the common electrode avoidance notch, and both ends of the common electrode connection segment are respectively connected to the common electrode main body portions in two adjacent pixel unit regions horizontally or vertically.

[0020] Optionally, two adjacent pixel unit regions, either horizontally or vertically adjacent, are defined as a first pixel unit region and a second pixel unit region, and two adjacent common electrode avoidance notches within the first pixel unit region and within the second pixel unit region are arranged in a staggered manner.

[0021] Optionally, the array substrate includes a first conductor layer, a first insulating layer, a second conductor layer, a second insulating layer, and a pixel electrode layer, and the first conductor layer, the first insulating layer, the second conductor layer, the second insulating layer, and the pixel electrode layer are sequentially stacked on the substrate;

[0022] The pixel main body is located within the pixel electrode layer, and the pixel extension penetrates through the second insulating layer and the first insulating layer to be connected to the pixel main body, and the common electrode main body is located within the first conductor layer or within the second conductor layer.

[0023] The present application also discloses a method for manufacturing an array substrate, and the method for manufacturing the array substrate is used to manufacture the above-mentioned array substrate, and the steps include:

[0024] Form a common electrode block on the substrate;

[0025] Open a hollow portion on the common electrode block;

[0026] Form a pixel electrode block on the substrate.

[0027] The present application also discloses an electronic paper display panel, and the electronic paper display panel includes an electronic paper reflective display layer and an array substrate, the array substrate is located on the light incident side of the electronic paper display panel, and the array substrate is used to drive the electronic paper reflective display layer to display an image.

[0028] Compared with the existing electronic paper display panel solutions, in the present application, by providing a hollow portion on the common electrode block, the hollow portion penetrates through the common electrode block, so that external light can directly pass through the hollow portion and will not be attenuated by the common electrode block, thereby reducing the loss of light intensity by the common electrode block, improving the light transmittance of each pixel unit region, and enhancing the display brightness of the electronic paper display panel. Description of the Drawings

[0029] The included drawings are used to provide a further understanding of the embodiments of the present application, and they form a part of the specification, are used to illustrate the embodiments of the present application, and are used to explain the principles of the present application together with the text description. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts. In the drawings:

[0030] Figure 1 Schematic diagram of an electronic paper display panel according to an embodiment of the present application;

[0031] Figure 2 Cross-sectional schematic diagram of an array substrate according to the first embodiment of the present application;

[0032] Figure 3 Planar schematic diagram of a hollowed-out portion according to the first embodiment of the present application;

[0033] Figure 4 Schematic diagram of a pixel electrode block and a common electrode block according to the first embodiment of the present application;

[0034] Figure 5 Schematic diagram of a first insulating channel and a second insulating channel according to the first embodiment of the present application;

[0035] Figure 6 Cross-sectional schematic diagram of a substrate channel according to the first embodiment of the present application;

[0036] Figure 7 Schematic diagram of a hollowed-out portion according to the first embodiment of the present application;

[0037] Figure 8 Planar schematic diagram of a common electrode avoidance notch according to the first embodiment of the present application;

[0038] Figure 9 Schematic diagram of an array substrate according to the second embodiment of the present application;

[0039] Figure 10 Process schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present application.

[0040] Among them, 10 is an electronic paper display panel; 20 is an electronic paper reflective display layer; 30 is an electrophoretic particle layer; 40 is a common electrode layer; 60 is a light filtering layer; 61 is a red color resistor; 62 is a green color resistor; 63 is a blue color resistor; 70 is an array substrate; 80 is a pixel unit area; 81 is a first pixel unit area; 82 is a second pixel unit area; 83 is a third pixel unit area; 100 is a substrate; 110 is a first conductor layer; 120 is a first insulating layer; 130 is a second conductor layer; 140 is a second insulating layer; 150 is a passivation layer; 160 is a pixel electrode layer; 200 is a common electrode block; 210 is a common electrode main body; 211 is a first common electrode main body; 212 is a second common electrode main body; 213 is a third common electrode main body; 220 is a common electrode extension; 221 is a first common electrode extension; 222 is a second common electrode extension; 230 is a hollowed-out part; 231 is a first hollowed-out part; 232 is a second hollowed-out part; 233 is a third hollowed-out part; 240 is a common electrode connection segment; 300 is a pixel electrode block; 310 is a pixel main body; 320 is a pixel extension; 321 is a first pixel extension; 322 is a second pixel extension; 410 is a first substrate channel; 411 is a first sub-substrate channel; 412 is a second sub-substrate channel; 413 is a third sub-substrate channel; 414 is a fourth sub-substrate channel; 420 is a second substrate channel; 510 is a first insulating channel; 520 is a second insulating channel; 511 is a first sub-insulating channel; 512 is a second sub-insulating channel; 513 is a third sub-insulating channel; 514 is a fourth sub-insulating channel; 610 is a common electrode avoidance notch; 620 is an insulating isolation wall; 710 is a data line; 720 is a scanning line; 730 is an active switch; 810 is a first passivation channel. Detailed implementation manners

[0041] It should be understood that the terms, the specific structures and functional details disclosed here are only for describing specific embodiments, which are representative. However, the present application can be specifically implemented in many alternative forms and should not be construed as being limited only to the embodiments described here.

[0042] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating relative importance or implicitly indicating the quantity of the indicated technical features. Thus, unless otherwise specified, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features; the meaning of "a plurality" is two or more. The term "comprising" and any variation thereof mean an inclusive inclusion, and there may be or be added one or more other features, integers, steps, operations, units, components and / or their combinations.

[0043] In addition, terms indicating orientation or positional relationships such as "center", "horizontal", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are described based on the orientation or relative positional relationships shown in the drawings, and are only for the purpose of facilitating the simplified description of the present application, rather than indicating that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0044] In addition, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0045] The present application will be described in detail below with reference to the drawings and optional embodiments.

[0046] Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of the present application, as Figure 1 shown, Figure 1 As shown by the arrow direction in the figure, the present application discloses an electronic paper display panel 10. The electronic paper display panel 10 includes an electronic paper reflective display layer 20 and an array substrate 70. The array substrate 70 is located on the light incident side of the electronic paper display panel 10, and the array substrate 70 is used to drive the electronic paper reflective display layer 20 to display an image.

[0047] The electronic paper reflective display layer 20 includes an electrophoretic particle layer 30 and a common electrode layer 40. The electrophoretic particle layer 30 includes black electrophoretic particles and white electrophoretic particles. The common electrode layer 40 is disposed on the side of the electrophoretic particle layer 30 facing away from the array substrate 70. The electrophoretic particle layer 30 is disposed on the side of the pixel electrode block 300 facing away from the substrate 100. An electric field is formed between the pixel electrode block 300 on the array substrate 70 and the common electrode layer 40 to drive the electrophoretic particles to move.

[0048] The electronic paper display panel 10 includes a filter layer 60. The filter layer 60 is disposed between the pixel electrode block 300 and the electrophoretic particle layer 30. The filter layer 60 includes a red color resistor 61, a green color resistor 62, and a blue color resistor 63.

[0049] The present application also discloses an array substrate 70, which can be used in the above-mentioned electronic paper display panel 10. For the array substrate 70, the present application provides the following design and specifically introduces it through several embodiments:

[0050] Embodiment 1:

[0051] Figure 2 It is a cross-sectional schematic diagram of an array substrate according to the first embodiment of the present application, Figure 3 It is a plan schematic diagram of a hollowed-out portion according to the first embodiment of the present application. Combining Figures 1 - 3 as shown, the present application discloses an array substrate 70, which is used in an electronic paper display panel 10 with the light incident surface on the side of the array substrate 70. The array substrate 70 further includes a substrate 100, a common electrode block 200, and a pixel electrode block 300. The common electrode block 200 and the pixel electrode block 300 are both disposed on the substrate 100. The array substrate 70 includes a pixel unit region 80, and the common electrode block 200 and the pixel electrode block 300 are both disposed in each pixel unit region 80. A storage capacitor is formed by the projection overlap between the common electrode block 200 and the pixel electrode block 300. A hollowed-out portion 230 is provided on the common electrode block 200, and the hollowed-out portion 230 penetrates through the common electrode block 200.

[0052] In the current electronic paper display panel 10 with the light incident surface on the side of the array substrate 70, although both the common electrode block 200 and the pixel electrode block 300 are made of a light-transmissive conductive material, due to the large area of the common electrode block 200, when the electronic paper display panel 10 displays, light needs to first pass through the array substrate 70, irradiate the electrophoretic particles on the underlying electronic paper reflection display layer 20, and then pass through the array substrate 70 again after being reflected by the electrophoretic particles and be reflected out. Finally, the light used for display passes through the array substrate 70 twice, resulting in a relatively low light transmittance in each pixel unit region 80. Especially for the electronic paper display panel 10 provided with a filter layer 60, the light transmittance is even lower.

[0053] Compared with the existing solutions of electronic paper display panels, in the present application, by providing a hollowed-out portion 230 on the common electrode block 200, and the hollowed-out portion 230 penetrates through the common electrode block 200, the external light can directly pass through the hollowed-out portion 230 without being attenuated by the common electrode block 200, thereby reducing the loss of light intensity by the common electrode block 200, improving the light transmittance of each pixel unit region 80, and enhancing the display brightness of the electronic paper display panel 10.

[0054] The array substrate 70 includes a first conductor layer 110, a first insulating layer 120, a second conductor layer 130, a second insulating layer 140, a passivation layer 150, and a pixel electrode layer 160. The first conductor layer 110, the first insulating layer 120, the second conductor layer 130, the second insulating layer 140, the passivation layer 150, and the pixel electrode layer 160 are sequentially stacked on the substrate 100.

[0055] The array substrate 70 further includes data lines 710, scan lines 720, and active switches 730. The data lines 710, the scan lines 720, and the active switches 730 are all disposed on the substrate 100. The data lines 710 and the scan lines 720 are arranged in a crisscross manner to define a pixel unit area 80. The scan lines 720 are connected to the gates of the active switches 730, the data lines 710 are connected to the sources of the active switches 730, and the drains of the active switches 730 are connected to the pixel electrode blocks 300.

[0056] The data lines 710 and the scan lines 720 are disposed in different layers. That is, when the data lines 710 are located on the first conductor layer 110, the scan lines 720 are located on the second conductor layer 130; when the data lines 710 are located on the second conductor layer 130, the scan lines 720 are located on the first conductor layer 110. And the active switches 730 can be top-gate active switches 730 or bottom-gate active switches 730.

[0057] Exemplarily, in the present application, the scan lines 720 are located within the first conductor layer 110, the data lines 710 are located within the second conductor layer 130, the gates of the active switches 730 are located within the first conductor layer 110, and the sources and drains of the active switches 730 are located within the second conductor layer 130.

[0058] When the electronic paper display panel 10 refreshes the screen, the movement speed of the electrophoretic particles is slower than the charging speed of the pixel electrode blocks 300. For example, when refreshing the second row after refreshing the first row, the electrophoretic particles on the pixel electrode blocks 300 of the first row have not yet moved to the target position. Therefore, a relatively large storage capacitor is required to maintain the movement of the electrophoretic particles to the target position. Moreover, since the working voltage of the electronic paper display panel 10 is relatively large, for example, taking the maximum driving voltage of the data lines 710 as plus or minus 15, then the voltage difference between the sources and drains of the active switches 730 will be relatively large, resulting in more leakage of the active switches 730. Therefore, the electronic paper display panel 10 needs to have a relatively large storage capacitor.

[0059] Since the hollow portion 230 is provided on the common electrode block 200, the overlapping area between the common electrode block 200 and the pixel electrode block 300 is reduced, and the size of the storage capacitor formed between the pixel electrode block 300 and the common electrode block 200 also becomes smaller, which will cause the electrophoretic particles to be unable to move to the target position, resulting in display anomalies such as color deviation problems.

[0060] Figure 4 It is a schematic diagram of a pixel electrode block and a common electrode block according to the first embodiment of the present application, as Figure 4 shown. In the present application, by providing the first substrate channel 410 and the second substrate channel 420 on the substrate 100, and then disposing the pixel extension portion 320 in the first substrate channel 410 and the common electrode extension portion 220 in the second substrate channel 420, the overlapping area between the pixel electrode block 300 and the common electrode block 200 in the vertical direction is increased. Specifically:

[0061] The pixel electrode block 300 includes a pixel main body portion 310 and a pixel extension portion 320, the pixel main body portion 310 is connected to the pixel extension portion 320, the common electrode block 200 includes a common electrode main body portion 210 and a common electrode extension portion 220, the common electrode main body portion 210 is connected to the common electrode extension portion 220, the hollow portion 230 is provided on the common electrode main body portion 210, both the pixel main body portion 310 and the common electrode main body portion 210 are light-transmissive conductive materials, and a first sub-storage capacitor is formed by the projection overlap between the pixel main body portion 310 and the common electrode main body portion 210, and a second sub-storage capacitor is formed by the projection overlap between the pixel extension portion 320 and the common electrode extension portion 220.

[0062] The array substrate 70 further includes a first substrate channel 410 and a second substrate channel 420, and the first substrate channel 410 and the second substrate channel 420 are provided on the substrate 100 of each pixel unit region 80; at least a part of the common electrode extension portion 220 is located in the second substrate channel 420, and at least a part of the pixel extension portion 320 is located in the first substrate channel 410.

[0063] In this embodiment, the pixel main body portion 310 is located in the pixel electrode layer 160, and the common electrode main body portion 210 is located in the first conductor layer 110. Specifically: the array substrate 70 includes a first conductor layer 110, a first insulating layer 120, a second conductor layer 130, a second insulating layer 140, and a pixel electrode layer 160, and the first conductor layer 110, the first insulating layer 120, the second conductor layer 130, the second insulating layer 140, and the pixel electrode layer 160 are sequentially stacked on the substrate 100.

[0064] The pixel main body 310 is located within the pixel electrode layer 160, and the pixel extension 320 penetrates through the second insulating layer 140, the first insulating layer 120 and is connected to the pixel main body 310. The common electrode main body 210 is located within the first conductor layer 110.

[0065] In this application, a first substrate channel 410 and a second substrate channel 420 are provided on the substrate 100. Then, the pixel extension 320 is disposed within the first substrate channel 410, and the common electrode extension 220 is disposed within the second substrate channel 420. In this way, a first sub-storage capacitor is formed by the projection overlap between the pixel main body 310 and the common electrode main body 210, and a second sub-storage capacitor is formed by the projection overlap between the pixel extension 320 and the common electrode extension 220. Thereby, the size of the storage capacitor within each pixel unit region 80 is increased, the problem of color deviation in the electronic paper display panel 10 is avoided, and the display effect of the display panel is improved.

[0066] Figure 5 is a schematic diagram of a first insulating channel and a second insulating channel according to the first embodiment of the present application. As Figure 5 shown, in order to further increase the size of the second storage capacitor, a first insulating channel 510 and a second insulating channel 520 are also provided in this application. The first pixel extension 321 of the pixel extension 320 is disposed within the first substrate channel 410, the second pixel extension 322 of the pixel extension 320 is disposed within the first insulating channel 510, the first common electrode extension 221 of the common electrode extension 220 is disposed within the second substrate channel 420, and the second common electrode extension 222 is disposed within the second insulating channel 520.

[0067] In other words, by providing a first insulating channel 510 and a second insulating channel 520 on the first insulating layer 120 and the second insulating layer 140, and then filling conductive materials within the first insulating channel 510 and the second insulating channel 520 to form the second pixel extension 322 and the second common electrode extension 222 respectively.

[0068] Specifically, the array substrate 70 includes a first conductor layer 110, a first insulating layer 120, a second conductor layer 130, a second insulating layer 140, a passivation layer 150 and a pixel electrode layer 160. The first conductor layer 110, the first insulating layer 120, the second conductor layer 130, the second insulating layer 140, the passivation layer 150 and the pixel electrode layer 160 are sequentially stacked on the substrate 100.

[0069] The array substrate 70 further includes a first insulating channel 510 and a second insulating channel 520, and each pixel unit region 80 is provided with the first insulating channel 510 and the second insulating channel 520; both the first insulating channel 510 and the second insulating channel 520 penetrate through the first insulating layer 120 and the second insulating layer 140.

[0070] The pixel extension portion 320 includes a first pixel extension portion 321 and a second pixel extension portion 322. The first pixel extension portion 321 is located in the first substrate channel 410, the second pixel extension portion 322 is located in the first insulating channel 510, and the second pixel extension portion 322 is connected to the first pixel extension portion 321 and the pixel main body portion 310.

[0071] The common electrode extension portion 220 includes a first common electrode extension portion 221 and a second common electrode extension portion 222. The first common electrode extension portion 221 is located in the second substrate channel 420, the second common electrode extension portion 222 is located in the second insulating channel 520, and the second common electrode extension portion 222 is connected to the first common electrode extension portion 221 and the common electrode main body portion 210.

[0072] Since the overlapping area of the second pixel extension portion 322 and the second common electrode extension portion 222 is increased, it is equivalent to increasing the size of the second storage capacitor, thereby further increasing the total storage capacitor size in each pixel unit region 80.

[0073] Moreover, by increasing the overlapping area of the first pixel extension portion 321 and the first common electrode extension portion 221, and the overlapping area of the second pixel extension portion 322 and the second common electrode extension portion 222, even if a hollow portion 230 is provided on the common electrode block 200, it will not cause a reduction in the overlapping area between the common electrode block 200 and the pixel electrode block 300, nor will it cause the storage capacitor to become smaller.

[0074] Exemplarily, the depths of the first substrate channel 410 and the second substrate channel 420 are greater than or equal to 10 um and less than or equal to 100 um; the widths of the first substrate channel 410 and the second substrate channel 420 are greater than or equal to 5 um, and the thickness of the substrate is 0.5 mm.

[0075] Further, the orthographic projection of the first insulating channel 510 coincides with the orthographic projection of the first substrate channel 410; the orthographic projection of the second insulating channel 520 coincides with the orthographic projection of the second substrate channel 420. On the one hand, this can avoid the misalignment of the first pixel extension 321 and the second pixel extension 322, resulting in the inability to connect them together, and the misalignment of the first common electrode extension 221 and the second common electrode extension 222, resulting in the inability to connect them together; it can also avoid the excessive orthographic projection area of the pixel extension 320 and the common electrode extension 220 on the substrate 100, resulting in excessive loss of light intensity, thereby avoiding the reduction of the light transmittance of each pixel unit area 80.

[0076] On the other hand, a single mask can be used to set the first substrate channel 410, the second substrate channel 420, the first insulating channel 510, and the second insulating channel 520, thereby saving the manufacturing cost.

[0077] Figure 6 It is a cross-sectional schematic diagram of a substrate channel according to the first embodiment of the present application. As shown in Figure 6 the figure, the substrate 100 is a glass substrate 100, the material of the glass substrate 100 is silicon dioxide, the materials of the first insulating layer 120 and the second insulating layer 140 are silicon nitride, the dielectric constant of the substrate 100 is less than the dielectric constants of the first insulating layer 120 and the second insulating layer 140, and since the operating voltage of the electronic paper display panel 10 is relatively high, there is a risk of breakdown between the first pixel extension 321 and the first common electrode extension 221 on the first substrate channel 410.

[0078] Therefore, the present application also provides an insulating isolation wall 620 between the first substrate channel 410 and the second substrate channel 420. The material of the insulating isolation wall 620 is an insulating material. Specifically, an insulating isolation wall 620 is provided between the first substrate channel 410 and the second substrate channel 420. The material of the insulating isolation wall 620 is the same as the materials of the first insulating layer 120 and the second insulating layer 140. The distance between the first common electrode extension 221 and the first pixel extension 321 is equal to the distance between the second common electrode extension 222 and the second pixel extension 322.

[0079] Since the insulating isolation wall 620 has the same dielectric constant as the first insulating layer 120 and the second insulating layer 140, it can ensure that the distance between the second common electrode extension 222 and the second pixel extension 322 is as small as the distance between the first common electrode extension 221 and the first pixel extension 321, thereby further increasing the capacitance of the storage capacitor and avoiding the risk of breakdown between the first common electrode extension 221 and the first pixel extension 321.

[0080] Figure 7 It is a schematic diagram of a hollowed-out part of the first embodiment of the present application. Figure 8 It is a plan view of a common electrode avoidance notch of the first embodiment of the present application. Combining Figure 7 and Figure 8 as shown, Figure 7 The direction indicated by the arrow in the figure is the propagation direction of part of the light. Define three consecutive pixel unit regions 80 as the first pixel unit region 81, the second pixel unit region 82, and the third pixel unit region 83. The first pixel unit region 81 and the third pixel unit region 83 are respectively located on both sides of the second pixel unit region 82. The first pixel unit region 81 is used to reflect red light, the second pixel unit region 82 is used to reflect blue light, and the third pixel unit region 83 is used to reflect green light.

[0081] Define the common electrode main body 210 in the first pixel unit region 81 as the first common electrode main body 211, define the common electrode main body 210 in the second pixel unit region 82 as the second common electrode main body 212, and define the common electrode main body 210 in the third pixel unit region 83 as the third common electrode main body 213; define the hollowed-out part 230 on the first common electrode main body 211 as the first hollowed-out part 231, define the hollowed-out part 230 on the second common electrode main body 212 as the second hollowed-out part 232, and define the hollowed-out part 230 on the third common electrode main body 213 as the third hollowed-out part 233.

[0082] The area of the third hollowed-out part 233 is smaller than the area of the first hollowed-out part 231, and the area of the first hollowed-out part 231 is smaller than the area of the second hollowed-out part 232; the area of the third common electrode main body 213 is larger than the area of the first common electrode main body 211, and the area of the first common electrode main body 211 is larger than the area of the second common electrode main body 212.

[0083] Since the light transmittance of the green color resistor 62, the red color resistor 61, and the blue color resistor 63 decreases in sequence, the area of the light passing through the third hollowed-out part 233 is smaller than the area of the first hollowed-out part 231, and the area of the first hollowed-out part 231 is smaller than the area of the second hollowed-out part 232. Thus, the light transmittance of the third pixel unit region 83, the second pixel unit region 82, and the first pixel unit region 81 can be balanced, avoiding the phenomenon that when the electronic paper display panel 10 displays a picture, due to the same transmittance of the first pixel unit region 81, the second pixel unit region 82, and the third pixel unit region 83 of the array substrate 70, the emitted light intensities of the first pixel unit region 81, the second pixel unit region 82, and the third pixel unit region 83 of the electronic paper display panel 10 are different under the same driving voltage, resulting in abnormal picture appearance.

[0084] The red color resistor 61 of the electronic paper display panel 10 is located in the first pixel unit area 81, the blue color resistor 63 is located in the second pixel unit area 82, and the green color resistor 62 is located in the third pixel unit area 83.

[0085] See Figure 8 , the first substrate channel 410 of the present application includes a first sub-substrate channel 411, a second sub-substrate channel 412, a third sub-substrate channel 413, and a fourth sub-substrate channel 414. The first sub-substrate channel 411, the second sub-substrate channel 412, the third sub-substrate channel 413, and the fourth sub-substrate channel 414 are arranged at intervals and successively surround the periphery of the second substrate channel 420. A common electrode avoidance notch 610 is formed between the first sub-substrate channel 411 and the second sub-substrate channel 412, a common electrode avoidance notch 610 is formed between the second sub-substrate channel 412 and the third sub-substrate channel 413, a common electrode avoidance notch 610 is formed between the third sub-substrate channel 413 and the fourth sub-substrate channel 414, and a common electrode avoidance notch 610 is formed between the fourth sub-substrate channel 414 and the first sub-substrate channel 411.

[0086] The first insulating channel 510 includes a first sub-insulating channel 511, a second sub-insulating channel 512, a third sub-insulating channel 513, and a fourth sub-insulating channel 514. The first sub-insulating channel 511, the second sub-insulating channel 512, the third sub-insulating channel 513, and the fourth sub-insulating channel 514 are arranged at intervals and successively surround the periphery of the second insulating channel 520. A common electrode avoidance notch 610 is formed between the first sub-insulating channel 511 and the second sub-insulating channel 512, a common electrode avoidance notch 610 is formed between the second sub-insulating channel 512 and the third sub-insulating channel 513, a common electrode avoidance notch 610 is formed between the third sub-insulating channel 513 and the fourth sub-insulating channel 514, and a common electrode avoidance notch 610 is formed between the fourth sub-insulating channel 514 and the first sub-insulating channel 511.

[0087] The first sub-insulating channel 511, the second sub-insulating channel 512, the third sub-insulating channel 513, and the fourth sub-insulating channel 514 respectively overlap with the orthographic projections of the first sub-substrate channel 411, the second sub-substrate channel 412, the third sub-substrate channel 413, and the fourth sub-substrate channel 414.

[0088] That is, the positive projections of the first sub-insulating channel 511 and the first sub-substrate channel 411 overlap, the positive projections of the second sub-insulating channel 512 and the second sub-substrate channel 412 overlap, the positive projections of the third sub-insulating channel 513 and the third sub-substrate channel 413 overlap, and the positive projections of the fourth sub-insulating channel 514 and the fourth sub-substrate channel 414 overlap.

[0089] The array substrate 70 further includes a common electrode connection section 240. The common electrode connection section 240 passes through the common electrode avoidance notch 610, and both ends of the common electrode connection section 240 are respectively connected to the common electrode main bodies 210 in two adjacent pixel unit areas 80, either horizontally or vertically.

[0090] In the present application, the scan line 720 is located in the first conductor layer 110, the data line 710 is located in the second conductor layer 130, and the common electrode connection section 240 is located on the first conductor layer 110 and connects two adjacent common electrode main bodies 210 in the same row parallel to the length direction of the scan line 720; when the data line 710 is located in the first conductor layer 110 and the scan line 720 is located in the second conductor layer 130, the common electrode connection section 240 is located on the first conductor layer 110 and connects two adjacent common electrode main bodies 210 in the same column parallel to the length direction of the data line 710.

[0091] Common electrode avoidance notches 610 are reserved around the common electrode main body 210. In this way, according to the specific positions of the scan line 720 and the data line 710, whether the common electrode connection section 240 is located on the upper and lower sides or the left and right sides of the common electrode main body 210 can be determined, improving the adaptability.

[0092] The second sub-substrate channel 420 is an annular channel, and the second sub-insulating channel 520 is an annular channel. The positive projection of the second sub-insulating channel 520 on the substrate 100 coincides with the positive projection of the second sub-substrate channel 420 on the substrate 100. Thereby, the overlapping area between the pixel extension part 320 and the common electrode extension part 220 is increased, and further the size of the storage capacitor is increased.

[0093] Moreover, the first sub-substrate channel 410 is located outside the second sub-substrate channel 420, and the first sub-insulating channel 510 is located outside the second sub-insulating channel 520; both the first common electrode extension part 221 and the second common electrode extension part 222 are made of a light-transmitting conductive material, such as indium tin oxide material, etc., and both the first pixel extension part 321 and the second pixel extension part 322 are made of a light-reflecting conductive material, such as metal copper, aluminum material, etc.

[0094] After the external light shines on the first pixel extension part 321, it will be reflected by the pixel extension part 320 onto the lower electronic paper reflective display layer 20, thereby improving the degree of light convergence, enhancing the contrast of the electronic paper display panel 10, and improving the display effect.

[0095] Moreover, two adjacent pixel unit regions 80 in the horizontal or vertical direction are respectively defined as a first pixel unit region 81 and a second pixel unit region 82, and two adjacent common electrode avoidance notches 610 in the first pixel unit region 81 and the second pixel unit region 82 are arranged in a staggered manner. In other words, in two adjacent pixel unit regions 80 in the horizontal or vertical direction, the two common electrode avoidance notches 610 that are close to each other are not opposite. That is, when folded with the center of the two pixel unit regions 80 as the axis of symmetry, the left common electrode avoidance notch 610 and the right common electrode avoidance notch 610 will not overlap.

[0096] It is avoided that the light in the first pixel unit region 81 shines into the second pixel unit region 82 through the common electrode avoidance notch 610. When the light that originally enters the first pixel unit region 81 shines on the common electrode avoidance notch 610 in the first pixel unit region 81, it will shine on the pixel extension part 320 of the second pixel unit region 82, and thus be reflected back to the first pixel unit region 81 by the pixel extension part 320, thereby further improving the degree of light convergence and enhancing the contrast of the electronic paper display panel 10.

[0097] Moreover, the second pixel extension part 322 and the pixel main body part 310 can be directly connected through a via. Preferably, in the present application, a first passivation trench 810 having the same shape as the first insulating trench 510 is provided on the passivation layer 150, that is, the orthographic projection of the first passivation trench 810 on the substrate 100 coincides with the orthographic projection of the first insulating trench 510 on the substrate 100, and a reflective conductive material is filled in the first passivation trench 810 to connect the pixel main body part 310 and the pixel extension part 320. In this way, whether on the first insulating layer 120 and the second insulating layer 140 or the passivation layer 150, a reflective conductive material is filled to reflect the light propagating from the common electrode avoidance notch 610 of the first pixel unit region 81 back into the first pixel unit region 81.

[0098] Since the area of the third hollow portion 233 is smaller than the area of the first hollow portion 231, and the area of the first hollow portion 231 is smaller than the area of the second hollow portion 232, the overlapping area between the common electrode main body portion 210 and the pixel main body portion 310 within the third pixel unit region 83 is greater than the overlapping area between the common electrode main body portion 210 and the pixel main body portion 310 within the first pixel unit region 81. The overlapping area between the common electrode main body portion 210 and the pixel main body portion 310 within the first pixel unit region 81 is greater than the overlapping area between the common electrode main body portion 210 and the pixel main body portion 310 within the second pixel unit region 82, resulting in different storage capacitor sizes within the first pixel unit region 81, the second pixel unit region 82, and the third pixel unit region 83.

[0099] Therefore, in the present application, by setting the total distance of the common electrode avoidance notch 610 within the third pixel unit region 83 to be greater than the total distance of the common electrode avoidance notch 610 within the first pixel unit region 81, and the total distance of the common electrode avoidance notch 610 within the first pixel unit region 81 to be greater than the total distance of the common electrode avoidance notch 610 within the second pixel unit region 82, the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 within the third pixel unit region 83 is smaller than the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 within the first pixel unit region 81. The overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 within the first pixel unit region 81 is smaller than the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 within the second pixel unit region 82. Thus, the sum of the overlapping area between the common electrode main body portion 210 and the pixel main body portion 310 plus the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 within the first pixel unit region 81, the sum of the overlapping area between the common electrode main body portion 210 and the pixel main body portion 310 plus the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 within the second pixel unit region 82, and the sum of the overlapping area between the common electrode main body portion 210 and the pixel main body portion 310 plus the overlapping area between the common electrode extension portion 220 and the pixel extension portion 320 within the third pixel unit region 83 are all equal, making the storage capacitor sizes within the first pixel unit region 81, the second pixel unit region 82, and the third pixel unit region 83 the same, and avoiding abnormal display phenomena.

[0100] Embodiment 2:

[0101] Figure 9 It is a schematic diagram of an array substrate according to the second embodiment of the present application, as Figure 9As shown, different from the first embodiment, the common electrode main body 210 in this embodiment is located within the second conductor layer 130. Specifically, the array substrate 70 includes a first conductor layer 110, a first insulating layer 120, a second conductor layer 130, a second insulating layer 140, and a pixel electrode layer 160. The first conductor layer 110, the first insulating layer 120, the second conductor layer 130, the second insulating layer 140, and the pixel electrode layer 160 are sequentially stacked on the substrate 100.

[0102] The pixel main body 310 is located within the pixel electrode layer 160, and the pixel extension 320 penetrates through the second insulating layer 140 and the first insulating layer 120 to be connected to the pixel main body 310. The common electrode main body 210 is located within the second conductor layer 130.

[0103] Compared with the solution of the first embodiment, in this embodiment, by locating the common electrode main body 210 within the second conductor layer 130, the distance between the common electrode main body 210 and the pixel main body 310 is reduced, thereby increasing the size of the storage capacitor of each pixel unit region 80.

[0104] Moreover, in the present application, the scan line 720 is located within the first conductor layer 110, the data line 710 is located within the second conductor layer 130, and the common electrode connection segment 240 in this embodiment is located on the second conductor layer 130 and connects two adjacent common electrode main bodies 210 in the same column parallel to the length direction of the data line 710; when the data line 710 is located within the first conductor layer 110 and the scan line 720 is located within the second conductor layer 130, the common electrode connection segment 240 is located on the second conductor layer 130 and connects two adjacent common electrode main bodies 210 in the same row parallel to the length direction of the scan line 720.

[0105] Figure 10 It is a process schematic diagram of a method for manufacturing an array substrate according to an embodiment of the present application. As Figure 10 shown, the present application also discloses a method for manufacturing an array substrate 70. The method for manufacturing the array substrate 70 is used to manufacture the array substrate 70, and the steps include:

[0106] S1: Form a common electrode block on the substrate;

[0107] S2: Open a hollow portion in the common electrode block;

[0108] S3: Form a pixel electrode block on the substrate.

[0109] Among them, the step of S1: forming a common electrode block on the substrate includes:

[0110] S11: Form a first substrate channel and a second substrate channel on the substrate;

[0111] S12: Form a first conductor layer on the substrate, pattern it to form a common electrode block, and fill the first substrate channel and the second substrate channel with a conductive material. The common electrode block includes a common electrode main body, a first common electrode extension, and a second common electrode extension. The conductive material in the second substrate channel forms the first common electrode extension;

[0112] Step S2: The steps of opening a hollow portion in the common electrode block include:

[0113] S21: Open a hollow portion in the common electrode block, and the hollow portion is disposed on the common electrode main body;

[0114] Step S3: The steps of forming a pixel electrode block on the substrate include:

[0115] S31: Form a first insulating layer, a second conductor layer, and a second insulating layer on the common electrode block in sequence;

[0116] S32: Form a first insulating channel and a second insulating channel on the second insulating layer and the first insulating layer;

[0117] S33: Fill the first insulating channel and the second insulating channel with a conductive material. The conductive material filled in the second insulating channel forms the second common electrode extension, and the second common electrode extension is connected to the first common electrode extension and the common electrode main body;

[0118] S34: Form the passivation layer on the second insulating layer;

[0119] S35: Form a pixel electrode layer on the second insulating layer and pattern it to form a pixel electrode block. The pixel electrode block includes a pixel main body, a first pixel extension, and a second pixel extension. The conductive material in the first substrate channel forms the first pixel extension, and the conductive material filled in the first insulating channel forms the second pixel extension. The second pixel extension is connected to the first pixel extension and the pixel main body.

[0120] Compared with the existing solution of the electronic paper display panel 10, in this application, by providing a hollow portion 230 on the common electrode block 200, the hollow portion 230 penetrates the common electrode block 200, so that external light can directly pass through the hollow portion 230, thereby reducing the loss of light intensity by the common electrode block 200, improving the light transmittance of each pixel unit area 80, and enhancing the display brightness of the electronic paper display panel 10.

[0121] It should be noted that the limitations of each step involved in this solution do not, on the premise of not affecting the implementation of the specific solution, determine the sequence of steps. The steps written in the front can be executed first, or can be executed later, or even can be executed simultaneously. As long as this solution can be implemented, it should be regarded as falling within the protection scope of this application.

[0122] It should be noted that the inventive concept of this application can form a very large number of embodiments. However, due to the limited space of the application documents, it is impossible to list them all. Therefore, on the premise of not conflicting with each other, the above-described embodiments or technical features can be arbitrarily combined to form new embodiments. After the combination of each embodiment or technical feature, the original technical effect will be enhanced.

[0123] The above content is a further detailed description of this application in combination with specific optional implementation manners. It cannot be determined that the specific implementation of this application is only limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, without departing from the concept of this application, several simple deductions or substitutions can also be made, and all should be regarded as falling within the protection scope of this application.

Claims

1. An array substrate, characterized in that, The array substrate is used in an electronic paper display panel with the light-incident surface on the array substrate side. The array substrate further includes a substrate, a common electrode block, and a pixel electrode block. The common electrode block and the pixel electrode block are both disposed on the substrate. The array substrate includes a pixel unit area, and the common electrode block and the pixel electrode block are both disposed in each pixel unit area. A storage capacitor is formed by the projection overlap between the common electrode block and the pixel electrode block. A hollow portion is provided on the common electrode block, and the hollow portion penetrates through the common electrode block; The pixel electrode block includes a pixel main body portion and a pixel extension portion, and the pixel main body portion is connected to the pixel extension portion. The common electrode block includes a common electrode main body portion and a common electrode extension portion, and the common electrode main body portion is connected to the common electrode extension portion. The hollow portion is provided on the common electrode main body portion. Both the pixel main body portion and the common electrode main body portion are made of a light-transmissive conductive material. A first sub-storage capacitor is formed by the projection overlap between the pixel main body portion and the common electrode main body portion. A second sub-storage capacitor is formed by the projection overlap between the pixel extension portion and the common electrode extension portion; The array substrate further includes a first substrate channel and a second substrate channel, and the first substrate channel and the second substrate channel are both disposed on the substrate of each pixel unit area; At least a part of the pixel extension portion is located in the first substrate channel, and at least a part of the common electrode extension portion is located in the second substrate channel.

2. The array substrate according to claim 1, wherein The array substrate includes a first conductor layer, a first insulating layer, a second conductor layer, a second insulating layer, a passivation layer, and a pixel electrode layer. The first conductor layer, the first insulating layer, the second conductor layer, the second insulating layer, the passivation layer, and the pixel electrode layer are sequentially stacked on the substrate; The array substrate further includes a first insulating channel and a second insulating channel. The first insulating channel and the second insulating channel are both provided in each pixel unit area. The first insulating channel and the second insulating channel both penetrate through the first insulating layer and the second insulating layer; The pixel extension portion includes a first pixel extension portion and a second pixel extension portion. The first pixel extension portion is located in the first substrate channel, and the second pixel extension portion is located in the first insulating channel. The second pixel extension portion is connected to the first pixel extension portion and the pixel main body portion; The common electrode extension portion includes a first common electrode extension portion and a second common electrode extension portion. The first common electrode extension portion is located in the second substrate channel, and the second common electrode extension portion is located in the second insulating channel. The second common electrode extension portion is connected to the first common electrode extension portion and the common electrode main body portion.

3. The array substrate according to claim 2, wherein Define three consecutive pixel unit areas as a first pixel unit area, a second pixel unit area, and a third pixel unit area. The first pixel unit area and the third pixel unit area are respectively located on both sides of the second pixel unit area. The first pixel unit area is used to reflect red light, the second pixel unit area is used to reflect blue light, and the third pixel unit area is used to reflect green light; Define the common electrode main body portion within the first pixel unit region as the first common electrode main body portion, the common electrode main body portion within the second pixel unit region as the second common electrode main body portion, and the common electrode main body portion within the third pixel unit region as the third common electrode main body portion; Define the hollowed-out portion on the first common electrode main body portion as the first hollowed-out portion, the hollowed-out portion on the second common electrode main body portion as the second hollowed-out portion, and the hollowed-out portion on the third common electrode main body portion as the third hollowed-out portion; The area of the third hollowed-out portion is smaller than the area of the first hollowed-out portion, and the area of the first hollowed-out portion is smaller than the area of the second hollowed-out portion; the area of the third common electrode main body portion is larger than the area of the first common electrode main body portion, and the area of the first common electrode main body portion is larger than the area of the second common electrode main body portion.

4. The array substrate according to claim 3, wherein The first substrate channel is located outside the second substrate channel, and the first insulating channel is located outside the second insulating channel; both the first common electrode extension portion and the second common electrode extension portion are made of a light-transmitting conductive material, and both the first pixel extension portion and the second pixel extension portion are made of a light-reflecting conductive material.

5. The array substrate according to claim 4, wherein The first substrate channel includes a first sub-substrate channel, a second sub-substrate channel, a third sub-substrate channel, and a fourth sub-substrate channel. The first sub-substrate channel, the second sub-substrate channel, the third sub-substrate channel, and the fourth sub-substrate channel are arranged at intervals and sequentially surround the second substrate channel. A common electrode avoidance notch is formed between the first sub-substrate channel and the second sub-substrate channel, a common electrode avoidance notch is formed between the second sub-substrate channel and the third sub-substrate channel, a common electrode avoidance notch is formed between the third sub-substrate channel and the fourth sub-substrate channel, and a common electrode avoidance notch is formed between the fourth sub-substrate channel and the first sub-substrate channel; The first insulating channel includes a first sub-insulating channel, a second sub-insulating channel, a third sub-insulating channel, and a fourth sub-insulating channel. The first sub-insulating channel, the second sub-insulating channel, the third sub-insulating channel, and the fourth sub-insulating channel are arranged at intervals and sequentially surround the second insulating channel. A common electrode avoidance notch is formed between the first sub-insulating channel and the second sub-insulating channel, a common electrode avoidance notch is formed between the second sub-insulating channel and the third sub-insulating channel, a common electrode avoidance notch is formed between the third sub-insulating channel and the fourth sub-insulating channel, and a common electrode avoidance notch is formed between the fourth sub-insulating channel and the first sub-insulating channel; The first sub-insulating channel, the second sub-insulating channel, the third sub-insulating channel, and the fourth sub-insulating channel respectively overlap with the orthographic projections of the first sub-substrate channel, the second sub-substrate channel, the third sub-substrate channel, and the fourth sub-substrate channel; The array substrate further includes a common electrode connection segment. The common electrode connection segment passes through the common electrode avoidance notch, and the two ends of the common electrode connection segment are respectively connected to the common electrode main body portions within two adjacent pixel unit regions, either horizontally or vertically.

6. The array substrate according to claim 5, wherein Define two adjacent pixel unit regions horizontally or vertically as a first pixel unit region and a second pixel unit region respectively, and two adjacent common electrode avoidance notches in the first pixel unit region and the second pixel unit region are arranged in a dislocation manner.

7. The array substrate according to claim 1, wherein The array substrate includes a first conductor layer, a first insulating layer, a second conductor layer, a second insulating layer, and a pixel electrode layer. The first conductor layer, the first insulating layer, the second conductor layer, the second insulating layer, and the pixel electrode layer are sequentially stacked on the substrate; The pixel main body is located in the pixel electrode layer, and the pixel extension penetrates through the second insulating layer and the first insulating layer to be connected to the pixel main body. The common electrode main body is located in the first conductor layer or in the second conductor layer.

8. A method for preparing an array substrate, characterized in that, The manufacturing method of the array substrate is used to manufacture the array substrate according to any one of the above claims 1-7, and the steps include: Form a common electrode block on the substrate; Open a hollow part on the common electrode block; Form a pixel electrode block on the substrate.

9. An electronic paper display panel, characterized in that, The electronic paper display panel includes an electronic paper reflection display layer and the array substrate according to any one of claims 1-7. The array substrate is located on the light incident side of the electronic paper display panel, and the array substrate is used to drive the electronic paper reflection display layer to display an image.

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