Amplification circuit

Abstract

An amplification circuit includes an amplifier, a first mirror branch circuit, a second mirror branch circuit, a first variable current source, a second variable current source, and an operational amplifier. The amplifier can receive a working current and an input signal and output the amplified input signal. The first mirror branch circuit and the second mirror branch circuit are coupled to the amplifier. The first variable current source is coupled to the first mirror branch circuit and generates a first reference current. The second variable current source is coupled to the second mirror branch circuit and generates a second reference current. The operational amplifier is coupled to the first mirroring branch circuit, the second mirroring branch circuit and the amplifier. The first reference current and the second reference current are related to the working current.

Description

Technical Field

[0001] The invention relates to an amplifier circuit, and in particular to an amplifier circuit with a variable current source. Background Art

[0002] The current mirror is a basic structure in analog circuits and is widely used in various bias circuits and loads of amplifier devices. For this reason, the accurate mapping characteristics of the current mirror are particularly important, and the stability and accuracy of its output current can determine the quality of the current mirror characteristics.

[0003] Current current mirror circuits often use Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). When the MOSFET operates in the linear region, its effective channel length will remain fixed. However, when the drain bias of the MOSFET is increased to the saturation region, the channel length will be shortened, so that the working current and voltage relationship in the saturation region is not related to the gate-source voltage (VGS) of the transistor as in the ideal state, but is related to the drain-source voltage (VDS) of the transistor due to the channel length modulation effect. Therefore, the current mirror circuit of the current amplifier circuit is easily affected by the changes in the process and bias of the MOSFET. In addition, since the current value of the amplifier circuit is not easy to adjust, there is still a lack of solutions to improve the controllability of the current amplifier circuit. Summary of the invention

[0004] An embodiment provides an amplifier circuit, including an amplifier, a first mirror branch circuit, a second mirror branch circuit, a first variable current source, a second variable current source, and an operational amplifier. The amplifier is used to receive a working current, including a first end for receiving an input signal, and a second end for outputting the amplified input signal. The first mirror branch circuit is coupled to the amplifier. The second mirror branch circuit is coupled to the amplifier. The first variable current source is coupled to the first mirror branch circuit to generate a first reference current for the first mirror branch circuit. The second variable current source is coupled to the second mirror branch circuit to generate a second reference current for the second mirror branch circuit. The operational amplifier includes a first input end coupled to the second mirror branch circuit, a second input end coupled to the first mirror branch circuit, and an output end coupled to the amplifier. The amplifier circuit has a plurality of gain modes, the first reference current is related to the working current, and the second reference current is related to the working current.

[0005] Another embodiment provides an amplifier circuit, including an input terminal, an output terminal, a first transistor, a second transistor, a third transistor, a fourth transistor, a first variable current source, a second variable current source, an operational amplifier, and a control circuit. The input terminal is used to receive an input signal. The output terminal is used to output the amplified input signal. The first transistor includes a first terminal for receiving a first reference current, a second terminal coupled to a first reference voltage terminal, and a control terminal. The second transistor includes a first terminal, a second terminal coupled to the first reference voltage terminal, and a control terminal coupled to the input terminal and the control terminal of the first transistor. The third transistor includes a first terminal coupled to the output terminal for receiving a working current, a second terminal coupled to the first terminal of the second transistor, and a control terminal. The fourth transistor includes a first terminal for receiving a second reference current, a second terminal, and a control terminal coupled to the control terminal of the third transistor. The first variable current source is used to generate the first reference current. The second variable current source is coupled to the second end of the fourth transistor to generate the second reference current. The operational amplifier includes a first input terminal coupled between the fourth transistor and the second variable current source, a second input terminal coupled between the first transistor and the first variable current source, and an output terminal coupled between the first transistor and the second transistor. The control circuit is coupled to the first variable current source and the second variable current source. The amplifier circuit has a plurality of gain modes. The control circuit controls the first variable current source and the second variable current source so that in each gain mode, the first reference current is related to the operating current, and the second reference current is related to the operating current. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 Schematic diagram of an amplifier circuit in an embodiment. Figure 2 FIG. 4 is a schematic diagram of an amplifier circuit in another embodiment. Figure 3 FIG. 4 is a schematic diagram of a part of the amplifier circuit in the embodiment. Figure 4 FIG. 4 is a schematic diagram of a first switch array of a first variable current source in an embodiment. Figure 5 FIG. 4 is a schematic diagram of a second switch array of a second variable current source in an embodiment. Figure 6 2 is a schematic diagram showing that, in an embodiment, the first switch array controls the first reference current so that the first reference current has current values ​​in seven stages. Figure 7 Schematic diagram of the switch in the embodiment.

Explanation of symbols

[0006] Herein, when two voltages are mentioned to be equal, it means that the difference between the two voltages is less than 10% of one of the two voltages.

[0007] Figure 1 is a schematic diagram of an amplifier circuit 100 in an embodiment. The amplifier circuit 100 may include an amplifier 105 , a first mirror branch circuit 110 , a second mirror branch circuit 120 , a first variable current source 510 , a second variable current source 520 , and an operational amplifier 130 .

[0008] The amplifier 105 can be used to receive the operating current ILNA. The amplifier 105 may include a first terminal and a second terminal, wherein the first terminal may be coupled to the input terminal N1 and used to receive the input signal RFIN, and the second terminal may be coupled to the output terminal N2 and used to output the amplified input signal RFOUT. The input signal RFIN may be a radio frequency signal, and the amplified input signal RFOUT may be an amplified radio frequency signal. According to an embodiment, the amplifier 105 is, for example, a low-noise amplifier (LNA). The amplifier 105 may also include a bias terminal coupled to the reference voltage terminal VREF, which may have a ground voltage or a predetermined bias voltage.

[0009] The first mirroring branch circuit 110 may be coupled to the amplifier 105 and may include a transistor. The second mirroring branch circuit 120 may be coupled to a bias terminal of the amplifier 105 and may include a transistor.

[0010] The first variable current source 510 may be coupled to the first mirror branch circuit 110 to generate a first reference current IREF1. The second variable current source 520 may be coupled to the second mirror branch circuit 120 to generate a second reference current IREF2. The first mirror branch circuit 110 is driven according to the first reference current IREF1, and the second mirror branch circuit 120 is driven according to the second reference current IREF2.

[0011] The operational amplifier 130 may include a first input terminal, a second input terminal, and an output terminal. The operational amplifier 130 may be a differential amplifier, the first input terminal may be a negative input terminal, and the second input terminal may be a positive input terminal. The first input terminal of the operational amplifier 130 may be coupled to the second mirror branch circuit 120, the second input terminal of the operational amplifier 130 may be coupled to the first mirror branch circuit 110, and the output terminal of the operational amplifier 130 may be coupled to the amplifier 105.

[0012] The amplifier circuit 100 may have a plurality of gain modes, the first reference current IREF1 may be related to the operating current ILNA, and the second reference current IREF2 may be related to the operating current ILNA. In different gain modes, different first reference current IREF1, second reference current IREF2 and operating current ILNA may be used.

[0013] Figure 1In the embodiment, the first mirror branch circuit 110 and the first variable current source 510 form a first current mirror circuit, and the second mirror branch circuit 120 and the second variable current source 520 form a second current mirror circuit, so that the first reference current IREF1 and the working current ILNA, and the second reference current IREF2 and the working current ILNA can have a current mirror relationship. The first reference current IREF1 and the working current ILNA change synchronously and can be positively correlated, and the second reference current IREF2 and the working current ILNA change synchronously and can be positively correlated. For example, the working current ILNA can be K times the first reference current IREF1, which can be expressed as ILNA=IREF1*K; and the working current ILNA can be K1 times the second reference current IREF2, which can be expressed as ILNA=IREF2*K1. Among them, the parameter K and the parameter K1 can be predetermined parameters.

[0014] like Figure 1 As shown, the amplifier 105 may include a node NT. The second input terminal of the operational amplifier 130 (e.g., a node between the first mirror branch circuit 110 and the first variable current source 510) may have a first voltage VDS1, the node NT of the amplifier 105 may have a second voltage VDS2, and the first input terminal of the operational amplifier 130 (e.g., a node between the second mirror branch circuit 120 and the second variable current source 520) may have a third voltage VDS3. The first voltage VDS1, the second voltage VDS2, and the third voltage VDS3 may be equal to reduce the effect of the transistor bias current variation on the process corner of process / voltage / temperature (PVT).

[0015] Figure 2 FIG. 2 is a schematic diagram of an amplifier circuit 200 in another embodiment. The amplifier circuit 200 may include an input terminal N1, an output terminal N2, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first variable current source 510, a second variable current source 520, an operational amplifier 130, and a control circuit 255.

[0016] The input terminal N1 of the amplifier circuit 200 can be used to receive the input signal RFIN. The output terminal N2 of the amplifier circuit 200 can be used to output the amplified input signal RFOUT. The input signal RFIN can be a radio frequency signal, and the amplified input signal RFOUT can be an amplified radio frequency signal.

[0017] The first transistor T1 may include a first terminal, a second terminal and a control terminal, wherein the first terminal may be used to receive a first reference current IREF1, and the second terminal may be coupled to a first reference voltage terminal V1. The first reference voltage terminal V1 may be a ground voltage or a predetermined bias voltage.

[0018] The second transistor T2 may include a first terminal, a second terminal and a control terminal, wherein the second terminal may be coupled to the first reference voltage terminal V1 , and the control terminal may be coupled to the input terminal N1 and the control terminal of the first transistor T1 and used to receive the input signal RFIN.

[0019] The third transistor T3 may include a first end, a second end and a control end, wherein the first end may be coupled to the output end N2 and used to receive the operating current ILNA through the reference voltage end V3 and to output the amplified input signal RFOUT, the second end may be coupled to the first end of the second transistor T2, and the control end may be coupled to the reference voltage end V2, and the reference voltage end V2 may also be the reference voltage end VREF.

[0020] The fourth transistor T4 may include a first terminal, a second terminal and a control terminal, wherein the first terminal may be used to receive the second reference current IREF2 via the reference voltage terminal V4, the second terminal may be coupled to the second variable current source 520, and the control terminal may be coupled to the control terminal of the third transistor T3.

[0021] The first variable current source 510 may generate a first reference current IREF1. The second variable current source 520 may generate a second reference current IREF2. The operational amplifier 130 may include a first input terminal, a second input terminal, and an output terminal. For example, the operational amplifier 130 may be a differential amplifier, the first input terminal may be a negative input terminal, and the second input terminal may be a positive input terminal. The first input terminal of the operational amplifier 130 may be coupled between the fourth transistor T4 and the second variable current source 520, the second input terminal of the operational amplifier 130 may be coupled between the first transistor T1 and the first variable current source 510, and the output terminal of the operational amplifier 130 may be coupled between the control terminal of the first transistor T1 and the control terminal of the second transistor T2.

[0022] Figure 1 The first mirror branch circuit 110 may be formed by a first transistor T1, the second mirror branch circuit 120 may be formed by a fourth transistor T4, and the amplifier 105 may be formed by a second transistor T2 and a third transistor T3.

[0023] The control circuit 255 may be coupled to the first variable current source 510 and the second variable current source 520. The amplifier circuit 200 may have a plurality of gain modes. The control circuit 255 may control the first variable current source 510 and the second variable current source 520 so that in each gain mode, the first reference current IREF1 is related to the operating current ILNA, and the second reference current IREF2 is related to the operating current ILNA.

[0024] Figure 2In the embodiment, the first reference current IREF1 and the operating current ILNA change synchronously and may be positively correlated, and the second reference current IREF2 and the operating current ILNA change synchronously and may be positively correlated. For example, the operating current ILNA may be K times the first reference current IREF1, which may be expressed as ILNA=IREF1*K; and the operating current ILNA may be K1 times the second reference current IREF2, which may be expressed as ILNA=IREF2*K1. Parameters K and K1 may be constants.

[0025] Figure 2 In the embodiment, the width / length ratio (W / L ratio) of the second transistor T2 may be K times the width / length ratio of the first transistor T1, and correspondingly, the operating current ILNA may be K times the first reference current IREF1 (ILNA=IREF1*K). The width / length ratio of the third transistor T3 may be K1 times the width / length ratio of the fourth transistor T4, and correspondingly, the operating current ILNA may be K1 times the second reference current IREF2 (ILNA=IREF2*K1).

[0026] When performing transistor layout, the ratio of the sizes of the transistors may be adjusted so that the operating current ILNA and the first reference current IREF1 have a predetermined ratio, and the operating current ILNA and the second reference current IREF2 have a predetermined ratio.

[0027] like Figure 2 As shown, the first input terminal of the operational amplifier 130 may be coupled to the second terminal of the fourth transistor T4, the second input terminal of the operational amplifier 130 may be coupled to the first terminal of the first transistor T1, and the output terminal of the operational amplifier 130 may be coupled to the control terminal of the first transistor T1 and the control terminal of the second transistor T2. The second input terminal of the operational amplifier 130 may have a first voltage VDS1, the first terminal of the second transistor T2 may have a second voltage VDS2, and the first input terminal of the operational amplifier 130 may have a third voltage VDS3. The first voltage VDS1, the second voltage VDS2, and the third voltage VDS3 may be equal.

[0028] Figure 2In the embodiment, by setting the second variable current source 520, the second end of the fourth transistor T4 can have a floating potential. For example, in an embodiment using a metal oxide semiconductor transistor, the voltage (for example, the third voltage VDS3) of the second end (for example, the source end) of the fourth transistor T4 can change with the gate-source voltage of the transistor in the second variable current source 520. In addition, the first transistor T1 and the second transistor T2 can have the same process variation direction, that is, they are located at the same or adjacent process / voltage / temperature (PVT) process corner. The third transistor T3 and the fourth transistor T4 can have the same process variation direction, that is, they are located at the same or adjacent process corner.

[0029] The electrical characteristics of the operational amplifier 130 are high input resistance and low output resistance, so the operational amplifier 130 can lock the voltage of the first end (e.g., drain end) of the first transistor T1 and the second transistor T2, and can use feedback to control the voltage of the control end (e.g., gate end) of the first transistor T1 and the second transistor T2. When receiving the first reference current IREF1, a first voltage VDS1 is generated at the first end of the first transistor T1, and the fourth transistor T4 driven by the second reference current IREF2 can provide a third voltage VDS3 at the second end (e.g., source end) of the fourth transistor T4. The operational amplifier 130 can control the control end (e.g., gate end) of the first transistor T1 and the second transistor T2 to lock the voltage of the first end of the first transistor T1 and the second transistor T2, so that the first voltage VDS1, the second voltage VDS2 and the third voltage VDS3 are equal, which can be expressed as VDS1=VDS2=VDS3. By maintaining the first voltage VDS1 , the second voltage VDS2 , and the third voltage VDS3 substantially equal, the influence of the transistor bias current variation caused by the process critical angle of process / voltage / temperature (PVT) can be reduced.

[0030] Figure 1 and Figure 2 In the embodiment, the first reference current IREF1 may have N stages, the second reference current IREF2 may have M stages, and each of the amplifier circuit 100 and the amplifier circuit 200 may have L gain modes. N, M, and L are integers, N, M, and L may be equal (expressed as N=M=L), and N, M, and L are greater than or equal to two. The first reference current IREF1 and the second reference current IREF2 may be adjusted synchronously corresponding to the L gain modes, so that the amplifier circuit 100 and the amplifier circuit 200 can reduce the influence of the transistor bias current change on the process critical angle of PVT even in different gain modes.

[0031] For example, if M=N=L=7 and K=K1=10, the first reference current IREF1 may be one of 350 μA, 450 μA, 550 μA, 600 μA, 650 μA, 700 μA and 750 μA, for a total of seven stages. Similarly, the second reference current IREF2 may be one of 350 μA, 450 μA, 550 μA, 600 μA, 650 μA, 700 μA and 750 μA, for a total of seven stages. The operating current ILNA may be one of 3.5 mA, 4.5 mA, 5.5 mA, 6 mA, 6.5 mA, 7 mA and 7.5 mA, for a total of seven stages. In this example, each of the amplifier circuit 100 and the amplifier circuit 200 may have seven gain modes, but this is only an example and the embodiment is not limited thereto.

[0032] In the multiple gain modes of the amplifier circuits 100 and 200 , the operating current ILNA may be K times the first reference current IREF1 (ILNA=IREF1*K), and the operating current ILNA may be K1 times the second reference current IREF2 (ILNA=IREF2*K1), where K and K1 may be constant values.

[0033] Figure 3 FIG. 3 is a schematic diagram of a circuit 300 in an embodiment. The circuit 300 may be Figure 1 The amplifier circuit 100 or Figure 2 The local circuit of the amplifier circuit 200. Figure 3 As shown, the first variable current source 510 may include a first switch array A1, and the second variable current source 520 may include a second switch array A2. The first switch array A1 and the second switch array A2 may be controlled by the control circuit 255 to generate a first reference current IREF1 and a second reference current IREF2, respectively.

[0034] The switch 310 may be the main switch of the first switch array A1 and the second switch array A2. When the switch 310 is turned off, the current values ​​of the first reference current IREF1 and the second reference current IREF2 may be approximately zero. The switch 315 may be the main switch of the second switch array A2. When the switch 315 is turned off, the current value of the second reference current IREF2 may be approximately zero. Figure 3 The sub-reference voltage Vd and the resistor unit R can generate a sub-reference current Id (which can be expressed as Id=Vd / R). The sub-reference current Id (e.g., 200 μA) can be amplified by a current mirror to generate a first-stage current value (e.g., 350 μA) of the first reference current IREF1 and the second reference current IREF2.

[0035] The first switch array A1 may further include a sub-reference transistor Td and a sub-reference mirror transistor Tm0, and the second switch array A2 may further include a sub-reference mirror transistor Tm1. The sub-reference transistor Td is coupled to and controlled by the switch 310, and outputs a sub-reference current Id according to the sub-reference voltage Vd. The sub-reference mirror transistor Tm0 is coupled to and controlled by the switch 310, and the sub-reference mirror transistor Tm1 is coupled to the sub-reference mirror transistor Tm0 and the switch 315. The sub-reference mirror transistor Tm0 and the sub-reference mirror transistor Tm1 are used to generate a reference mirror current Im0 according to the sub-reference current Id.

[0036] The circuit 300 may further include an operational amplifier 305. The operational amplifier 305 may include a first input terminal, a second input terminal, and an output terminal. The operational amplifier 130 may be a differential amplifier, the first input terminal may be a negative input terminal for receiving a voltage Vd, the second input terminal may be a positive input terminal for locking a sub-reference voltage Vd, and the output terminal may output a control voltage Vc to the switch 310.

[0037] Figure 3 The control signal Sc can be used to control the first switch array A1 and the second switch array A2. The current values ​​of the first reference current IREF1 and the second reference current IREF2 corresponding to the multiple stages will be described later.

[0038] Figure 4 is a schematic diagram of a first switch array A1 of a first variable current source 510 in an embodiment. The first switch array A1 may include first transistors T11 to N-th transistors T1N and first switches SW11 to N-th switches SW1N. The first switch SW11 is Figure 3 The first transistor T11 to the N-th transistor T1N are respectively controlled by the first switch SW11 to the N-th switch SW1N to be enabled or disabled, and are used to generate the first sub-mirror current Im11 to the N-th sub-mirror current Im1N respectively. The first switch SW11 to the N-th switch SW1N are controlled by the control signal Sc of the control circuit 255. The sum of the first sub-mirror current Im11 to the N-th sub-mirror current Im1N is the first reference current IREF1.

[0039] Each transistor from the first transistor T11 to the Nth transistor T1N may include a first end, a second end and a control end. Each switch from the first switch SW11 to the Nth switch SW1N may include a first end and a second end. The first end of the i-th transistor T1i may be coupled to the first end of the (i+1)th transistor T1(i+1). The control end of the i-th transistor T1i may be coupled to the first end of the i-th switch SW1i. The control end of the (i+1)th transistor T1(i+1) may be coupled to the second end of the i-th switch SW1i. The second end of the i-th switch SW1i may be coupled to the first end of the (i+1)th switch SW1(i+1). The second end of the i-th transistor T1i may be coupled to the second end of the (i+1)th transistor T1(i+1) and is used to output a first reference current IREF1. The above-mentioned N and i are integers greater than 0, and i <N。

[0040] Figure 4 When the first transistor T11 is enabled, the second transistor T12 to the Nth transistor T1N are disabled, and the first transistor T11 is used to generate the first sub-mirror current Im11 according to the sub-reference current Id. The first reference current IREF1 may have a first current value (ie, the value of the first sub-mirror current Im11, for example, 350 μA).

[0041] When the first transistor T11 and the second transistor T12 are enabled, the third transistor T13 to the Nth transistor T1N are disabled, and the first transistor T11 to the second transistor T12 are used to generate the first sub-mirror current Im11 to the second sub-mirror current Im12 according to the sub-reference current Id. The first reference current IREF1 may have a second current value (i.e., the sum of the first sub-mirror current Im11 to the second sub-mirror current Im12, for example, 450 μA).

[0042] Similarly, when the first transistor T11 to the N-th transistor T1N are all enabled, the first transistor T11 to the N-th transistor T1N are respectively used to generate the first sub-mirror current Im11 to the N-th sub-mirror current Im1N according to the sub-reference current Id. The first reference current IREF1 may have an N-th current value (i.e., the sum of the first sub-mirror current Im11 to the N-th sub-mirror current Im1N, for example, 750 μA).

[0043] Therefore, the first reference current IREF1 may have N stages, and the first reference current IREF1 may be adjusted to one of the N current values, thereby achieving more precise control.

[0044] Figure 5FIG. 2 is a schematic diagram of a second switch array A2 of a second variable current source 520 in an embodiment. The second switch array A2 may include first to M-th transistors T21 to T2M, and first to M-th switches SW21 to SW2M. The first switch SW21 is the switch 315 in FIG. 3 . The first to M-th transistors T21 to T2M are respectively controlled by the first to M-th switches SW21 to SW2M to be enabled or disabled, so as to respectively generate the first sub-mirror current Im21 to the M-th sub-mirror current Im2M. The first to M-th switches SW21 to SW2M are controlled by the control signal Sc of the control circuit 255. The sum of the first to M-th sub-mirror current Im21 to the M-th sub-mirror current Im2M is the second reference current IREF2.

[0045] Each transistor from the first transistor T21 to the Mth transistor T1M may have a first end, a second end and a control end. Each switch from the first switch SW21 to the Mth switch SW2M may have a first end and a second end. The first end of the jth transistor T2j may be coupled to the first end of the (j+1)th transistor T2(j+1). The control end of the jth transistor T2j may be coupled to the second end of the jth switch SW2j. The second end of the jth transistor T2j may be coupled to the second end of the (j+1)th transistor T2(j+1) and used to output the second reference current IREF2. The second end of the jth switch SW2j may be coupled to the first end of the (j+1)th switch SW2(j+1). M and j are integers greater than 0, j <M。

[0046] Figure 5 When the first transistor T21 is enabled, the second transistor T22 to the Mth transistor T2M are disabled, and the first transistor T11 is used to generate the first sub-mirror current Im21 according to the mirror current Im0. The second reference current IREF2 may have a first current value (ie, the value of the first sub-mirror current Im21, for example, 350 μA).

[0047] When the first transistor T21 and the second transistor T22 are enabled, the third transistor T23 to the Mth transistor T2M are disabled, and the first transistor T21 to the second transistor T22 are respectively used to generate the first sub-mirror current Im21 to the second sub-mirror current Im22 according to the mirror current Im0. The second reference current IREF2 may have a second current value (i.e., the sum of the first sub-mirror current Im21 to the second sub-mirror current Im22, for example, 450 μA).

[0048] By analogy, when the first transistor T21 to the M-th transistor T2M are all enabled, the first transistor T21 to the M-th transistor T2M are respectively used to generate the first sub-mirror current Im21 to the M-th sub-mirror current Im2M according to the mirror current Im0. The second reference current IREF2 may have the M-th current value (that is, the sum of the first sub-mirror current Im21 to the M-th sub-mirror current Im2M, for example, 750 μA).

[0049] Therefore, the second reference current IREF2 may have M stages, and the second reference current IREF2 may be adjusted to one of M current values, thereby achieving more precise control.

[0050] In this embodiment, the sub-reference transistor Td and the sub-reference mirror transistor Tm0 of the first switch array A1 have a matching layout with the first transistor T11 to the N-th transistor T1N. The sub-reference mirror transistor Tm1 of the second switch array A2 has a matching layout with the first transistor T21 to the M-th transistor T2M. The matching layout is, for example, such that the currents flowing through the related transistors have the same direction.

[0051] Figure 4 The first switch array A1 and Figure 5 The second switch array A2 can be controlled by Figure 2 The control circuit 255 makes the first transistor T11 to the Nth transistor T1N of the first switch array A1 and the first transistor T21 to the Mth transistor T2M of the second switch array A2 have the same enable or disable state. Figure 5 The second switch array A2 may be controlled by a control signal generated by the control circuit 255. According to an embodiment, the control signal may be a digital signal. For example, Figure 3 The control signal Sc can be used to control the first switch array A1 and the second switch array A2. According to another embodiment, the first control signal can be used to control the first switch array A1, and the second control signal can be used to control the second switch array A2, wherein the first control signal and the second control signal can be two related but different control signals.

[0052] Figure 6 2 is a schematic diagram showing that the first switch array A1 controls the first reference current IREF1 so that the first reference current IREF1 has current values ​​in seven stages in an embodiment. Figure 6 In, it can correspond to Figure 4 An embodiment of N=7. Figure 6 As shown, when the first transistor T11 is enabled and the second transistor T12 to the seventh transistor T17 are disabled, the first reference current IREF1 may have a first current value (eg, 350 μA). Figure 1 and Figure 2 The operating current ILNA may be K times of the first current value, for example, 10 times, that is, 3.5 mA.

[0053] When the first transistor T11 and the second transistor T12 are enabled, and the third transistor T13 to the seventh transistor T17 are disabled, the first reference current IREF1 may have a second current value (eg, 450 μA). Figure 1 and Figure 2 The operating current ILNA may be K times of the first current value, for example, 10 times, that is, 4.5 mA.

[0054] When the first transistor T11, the second transistor T12 and the third transistor T13 are enabled, and the fourth transistor T14 to the seventh transistor T17 are disabled, the first reference current IREF1 may have a third current value (eg, 550 μA). Figure 1 and Figure 2 The operating current ILNA may be K times of the first current value, for example, 10 times, that is, 5.5 mA.

[0055] When the first transistor T11, the second transistor T12, the third transistor T13 and the fourth transistor T14 are enabled, and the fifth transistor T15 to the seventh transistor T17 are disabled, the first reference current IREF1 may have a fourth current value (eg, 600 μA). Figure 1 and Figure 2 The operating current ILNA may be K times of the first current value, for example, 10 times, that is, 6 mA.

[0056] When the first transistor T11, the second transistor T12, the third transistor T13, the fourth transistor T14 and the fifth transistor T15 are enabled, and the sixth transistor T16 to the seventh transistor T17 are disabled, the first reference current IREF1 may have a fifth current value (eg, 650 μA). Figure 1 and Figure 2 The operating current ILNA may be K times of the first current value, for example, 10 times, that is, 6.5 mA.

[0057] When the first transistor T11, the second transistor T12, the third transistor T13, the fourth transistor T14, the fifth transistor T15 and the sixth transistor T16 are enabled, and the seventh transistor T17 is disabled, the first reference current IREF1 may have a sixth current value (eg, 700 μA). Figure 1 and Figure 2 The operating current ILNA may be K times of the first current value, for example, 10 times, that is, 7 mA.

[0058] When the first transistor T11, the second transistor T12, the third transistor T13, the fourth transistor T14, the fifth transistor T15, the sixth transistor T16 and the seventh transistor T17 are enabled, the first reference current IREF1 may have a seventh current value (eg, 750 μA). Figure 1 and Figure 2 The operating current ILNA may be K times of the first current value, for example, 10 times, that is, 7.5 mA.

[0059] Figure 6 In the embodiment, the switch SW1d and the transistor T1d may be dummy elements, which may be selectively used or not used, or may be selectively omitted. That is, each of the first switch array A1 and the second switch array A2 may be provided with a dummy switch and a dummy transistor to provide better electrical characteristics.

[0060] The first switch array A1 and the second switch array A2 can be controlled synchronously. For example, when the first switch array A1 provides the first reference current IREF1 (eg, 350 μA) of the first stage S1, the second switch array A2 can provide the second reference current IREF2 (eg, 350 μA) of the first stage S1.

[0061] When the first switch array A1 provides the first reference current IREF1 (eg, 450 μA) of the second stage S2 , the second switch array A2 may provide the second reference current IREF2 (eg, 450 μA) of the second stage S2 .

[0062] When the first switch array A1 provides the first reference current IREF1 (eg, 550 μA) of the third stage S3 , the second switch array A2 may provide the second reference current IREF2 (eg, 550 μA) of the third stage S3 .

[0063] Similarly, when the first switch array A1 provides the first reference current IREF1 (eg, 750 μA) of the seventh stage S7 , the second switch array A2 can provide the second reference current IREF2 (eg, 750 μA) of the seventh stage S7 .

[0064] Figure 6In the embodiment, the expected value of the working current ILNA of the first stage S1 is 3.5 mA, but the actual simulation value is 3.51 mA. The expected value of the working current ILNA of the second stage S3 is 4.5 mA, but the actual simulation value is 4.49 mA. The expected value of the working current ILNA of the third stage S3 is 5.5 mA, but the actual simulation value is 5.46 mA. The expected value of the working current ILNA of the fourth stage S4 is 6.0 mA, but the actual simulation value is 5.97 mA. The expected value of the working current ILNA of the fifth stage S5 is 6.5 mA, but the actual simulation value is 6.48 mA. The expected value of the working current ILNA of the sixth stage S6 is 7.0 mA, but the actual simulation value is 6.98 mA. The expected value of the working current ILNA of the seventh stage S1 is 7.5 mA, but the actual simulation value is 7.49 mA.

[0065] Figure 6 In the embodiment, the error between the predicted value and the actual simulated value of the working current ILNA is within an acceptable range. Therefore, by controlling the first switch array A1 and the second switch array A2, the first reference current IREF1 and the second reference current IREF can be precisely and synchronously adjusted, thereby precisely adjusting the working current ILNA.

[0066] Figure 7 Schematic diagram of a switch in an embodiment. Figures 3 to 5In the embodiment, each of the switches 310, 315, the first switch SW11 to the Nth switch SW1N, and the first switch SW21 to the Mth switch SW2M may include a first terminal (1), a second terminal (2), and a switch transistor TS1 coupled between the first terminal (1) and the second terminal (2). The switch transistor TS1 is controlled by the control circuit 255 (for example, by receiving the first control signal Sc(1)) to be turned on or off so that the voltage of the second terminal (2) is the same as or different from that of the first terminal (1), thereby enabling or disabling the corresponding first transistor T11 to the Nth transistor T1N and the first transistor T21 to the Mth transistor T2M. In one embodiment, the switch may further include a third terminal (3) coupled to the reference voltage terminal V6, and a switch transistor TS2 coupled between the second terminal (2) and the third terminal (3), the switch transistor TS1 and the switch transistor TS2 are simultaneously controlled by the control circuit 255 (for example, receiving the first control signal Sc(1) and the second control signal Sc(2) respectively) to be turned on or off, and the switch transistor TS1 and the switch transistor TS2 have opposite on / off states, so as to respectively make the voltage of the second terminal (2) the same as one of the first terminal (1) or the third terminal (3), thereby enabling or disabling the corresponding first transistor T11 to the Nth transistor T1N, and the first transistor T21 to the Mth transistor T2M. For example, when the switch transistor TS1 is turned on and the switch transistor TS2 is turned off, the voltage of the second terminal (2) is the same as the first terminal (1), and the corresponding one of the first transistor T11 to the Nth transistor T1N, and the first transistor T21 to the Mth transistor T2M is enabled. When the switch transistor TS1 is turned off and the switch transistor TS2 is turned on, the voltage of the second terminal (2) is the same as the voltage of the first terminal (1) (that is, both are the control voltage Vc), and the corresponding first transistor T11 to the Nth transistor T1N and the first transistor T21 to the Mth transistor T2M are disabled. Figure 3 and Figure 4 For example, when the switch transistor TS1 is turned on and the switch transistor TS2 is turned off, the voltages at the first end (1) and the first end (2) of the switch 310 and the first switch SW11 to the Nth switch SW1N are all the voltage of the reference voltage end V5; when the switch transistor TS2 is turned on and the switch transistor TS1 is turned off, the voltages at the first end (1) and the first end (2) of the switch 310 and the first switch SW11 to the Nth switch SW1N are all the voltage of the reference voltage end V6.

[0067] In summary, by using the amplifier circuits 100 and 200 provided in the embodiment, two reference currents that change synchronously with the working current are used, so that the working current ILNA can be accurately K times the first reference current IREF1, and the working current ILNA can be accurately K1 times the second reference current IREF2. In addition, by using the first switch array A1 and the second switch array A2 of the embodiment, each of the first reference current IREF1 and the second reference current IREF can be adjusted in multiple stages and can have a plurality of current values. Therefore, the stability, accuracy and controllability of the amplifier circuit of the embodiment can be effectively improved.

[0068] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should fall within the scope of the present invention.

Claims

1. An amplifier circuit, characterized in that: include: An amplifier, for receiving a working current, comprising a first end for receiving an input signal, and a second end for outputting the amplified input signal; a first mirror branch circuit coupled to the amplifier; a second mirror branch circuit coupled to the amplifier; A first variable current source, coupled to the first mirror branch circuit, for generating a first reference current; a second variable current source, coupled to the second mirror branch circuit, for generating a second reference current; as well as An operational amplifier, comprising a first input terminal coupled to the second mirror branch circuit, a second input terminal coupled to the first mirror branch circuit, and an output terminal coupled to the amplifier; The amplifier circuit has a plurality of gain modes, the first reference current is related to the operating current, and the second reference current is related to the operating current.

2. The amplifier circuit according to claim 1, characterized in that: The first reference current is positively correlated with the operating current, and the second reference current is positively correlated with the operating current.

3. The amplifier circuit according to claim 1, characterized in that: The amplifier includes a node, the second input terminal of the operational amplifier has a first voltage, the node of the amplifier has a second voltage, the first input terminal of the operational amplifier has a third voltage, and the first voltage, the second voltage and the third voltage are equal.

4. The amplifier circuit according to claim 1, characterized in that: in: The first variable current source includes a first switch array; The second variable current source includes a second switch array; and The first switch array and the second switch array are controlled by a control circuit to output the first reference current and the second reference current respectively.

5. An amplifier circuit, characterized in that: include: an input terminal, used to receive an input signal; an output terminal, used to output the amplified input signal; a first transistor, comprising: a first terminal, used for receiving a first reference current; a second terminal coupled to a first reference voltage terminal; and A control terminal; a second transistor comprising: a first end; a second terminal coupled to the first reference voltage terminal; and a control terminal coupled to the input terminal and the control terminal of the first transistor; a third transistor comprising: A first terminal coupled to the output terminal and configured to receive a working current; a second terminal coupled to the first terminal of the second transistor; and A control terminal; a fourth transistor comprising: a first terminal, used for receiving a second reference current; a second end; and a control terminal coupled to the control terminal of the third transistor; a first variable current source, used to generate the first reference current; a second variable current source coupled to the second terminal of the fourth transistor to generate the second reference current; an operational amplifier including a first input terminal coupled between the fourth transistor and the second variable current source, a second input terminal coupled between the first transistor and the first variable current source, and an output terminal coupled between the first transistor and the second transistor; and a control circuit coupled to the first variable current source and the second variable current source; Wherein, the amplifier circuit has a plurality of gain modes; The control circuit controls the first variable current source and the second variable current source so that in each gain mode, the first reference current is related to the operating current, and the second reference current is related to the operating current.

6. The amplifier circuit according to claim 5, characterized in that: The first reference current is positively correlated with the operating current, and the second reference current is positively correlated with the operating current.

7. The amplifier circuit according to claim 5, characterized in that: The first input terminal of the operational amplifier is coupled to the second terminal of the fourth transistor, the second input terminal of the operational amplifier is coupled to the first terminal of the first transistor, the second terminal of the operational amplifier has a first voltage, the first terminal of the second transistor has a second voltage, the first terminal of the operational amplifier has a third voltage, and the first voltage, the second voltage and the third voltage are equal.

8. The amplifier circuit according to any one of claims 1 to 7, characterized in that: in: The first reference current has N stages, the second reference current has M stages, and the amplifier circuit has L gain modes; as well as N, M and L are integers, N, M and L are equal, and N, M and L are greater than or equal to two.

9. The amplifier circuit according to claim 8, characterized in that: The first reference current and the second reference current are adjusted corresponding to the plurality of gain modes.

10. The amplifier circuit according to claim 8, characterized in that: In each of the L gain modes, the operating current is K times the first reference current, and the operating current is K1 times the second reference current, wherein K and K1 are constant values.

11. The amplifier circuit according to any one of claims 1 to 7, characterized in that: The amplifier circuit has a first gain mode and a second gain mode. In the first gain mode and the second gain mode, the operating current is K times the first reference current, and the operating current is K1 times the second reference current, wherein K and K1 are constants.

12. The amplifier circuit according to claim 5, characterized in that: in: The first variable current source includes a first switch array; The second variable current source includes a second switch array; and The first switch array and the second switch array are controlled by the control circuit to output the first reference current and the second reference current respectively.

13. The amplifier circuit according to claim 12, characterized in that: The first switch array includes a first transistor to an N-th transistor, and a first switch to an N-th switch, wherein: The first transistor to the N-th transistor are respectively controlled by the first switch to the N-th switch to be enabled or disabled, so as to respectively generate a first sub-mirror current to an N-th sub-mirror current; The first switch to the Nth switch are controlled by the control circuit; and N is an integer greater than 1.

14. The amplifier circuit according to claim 13, characterized in that: in: Each of the first transistor to the Nth transistor has a first terminal, a second terminal and a control terminal; Each of the first switch to the Nth switch has a first end and a second end; A first terminal of an i-th transistor is coupled to a first terminal of an (i+1)-th transistor; A control terminal of the i-th transistor is coupled to a second terminal of an i-th switch; A second terminal of the i-th transistor is coupled to a second terminal of the (i+1)-th transistor; A second terminal of the i-th switch is coupled to a first terminal of an (i+1)-th switch; and N and i are integers greater than 1, i <N。 15. The amplifier circuit according to claim 13, characterized in that: The second switch array includes a first transistor to an M-th transistor and a first switch to an M-th switch, wherein: The first transistor to the Mth transistor are respectively controlled by the first switch to the Mth switch to be enabled or disabled, so as to respectively generate a first sub-mirror current to an Mth sub-mirror current; The first switch to the Mth switch are controlled by the control circuit; and M is an integer greater than 1.

16. The amplifier circuit according to claim 15, characterized in that: in: Each of the first transistor to the Mth transistor has a first terminal, a second terminal and a control terminal; Each of the first switch to the Mth switch has a first end and a second end; A first terminal of a j-th transistor is coupled to a first terminal of a j+1-th transistor; A control terminal of the j-th transistor is coupled to a second terminal of a j-th switch; A second terminal of the j-th transistor is coupled to a second terminal of the j+1-th transistor; A second terminal of the j-th switch is coupled to a first terminal of a j+1-th switch; and M and j are integers greater than 1, j <M。 17. The amplifier circuit according to claim 15, characterized in that: The first transistor to the Nth transistor of the first switch array and the first transistor to the Mth transistor of the second switch array have the same enable or disable state respectively.

18. The amplifier circuit according to claim 15, characterized in that: Wherein each switch from the first switch to the Nth switch of the first switch array and each switch from the first switch to the Mth switch of the second switch array has: a first end and a second end; a third terminal coupled to a second reference voltage terminal; a first switch transistor coupled between the first terminal and the second terminal; and a second switch transistor coupled between the second terminal and the third terminal; The first switch transistor and the second switch transistor are controlled by the control circuit and have opposite on / off states.

19. The amplifier circuit according to claim 15, characterized in that: in: The first switch array further includes: a sub-reference transistor, coupled to and controlled by the first switch of the first switch array, for outputting a sub-reference current according to a sub-reference voltage; a first sub-reference mirror transistor, coupled to and controlled by the first switch of the first switch array, for generating a first reference mirror current according to the sub-reference current; and The first transistor to the N-th transistor of the first switch array are used to generate the first sub-mirror current to an N-th sub-mirror current respectively according to the sub-reference current; and The second switch array further includes: a second sub-reference mirror transistor coupled between the first sub-reference mirror transistor and the first switch of the second switch array, for receiving the first reference mirror current; and The first transistor to the Mth transistor of the second switch array are used to generate the first sub-mirror current to the Mth sub-mirror current respectively according to the first reference mirror current.

20. The amplifier circuit according to claim 19, characterized in that: in: The sub-reference transistor, the first sub-reference mirror transistor, and the first transistor to the Nth transistor of the first switch array have a matching layout; and The second sub-reference mirror transistor of the second switch array has a matching layout with the first transistor to the Mth transistor.

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