Trigger control method based on FPGA parallel broadband DBI architecture

Abstract

The invention discloses a trigger control method based on an FPGA parallel broadband DBI architecture. The FPGA parallel broadband DBI architecture comprises a multiplexer, two sub-band decomposition filter banks, eight sub-band acquisition modules, a processing card A and a processing card B, the trigger control method comprises the following steps: S1, after an input signal passes through a multiplexer, respectively inputting the input signal into two sub-band decomposition filter banks; each sub-band decomposition filter group decomposes an input signal into four sub-band signals, and each sub-band signal corresponds to one sub-band acquisition module; s2, each sub-band signal enters a processing board through a corresponding sub-band acquisition module; s3, monitoring the trigger states of all sub-band paths in real time; and S4, if each sub-band acquisition module generates a trigger signal, the rear-stage processing board specifically controls the read-write control of the front-stage sub-band acquisition module. Any channel is selected as a trigger source, the input waveform can be correctly triggered and stably displayed, and the waveform can be stably triggered according to the preset trigger condition.

Description

Technical Field

[0001] The invention belongs to the technical field of broadband high-speed data acquisition and broadband high-speed digital oscilloscopes, and relates to a trigger control method based on FPGA parallel broadband DBI architecture. Background Art

[0002] The acquisition system architecture of the Digital Bandwidth Interleaved (DBI) sampling technology is widely used in the fields of broadband high-speed data acquisition and broadband high-speed digital oscilloscope technology. The traditional DBI acquisition system multi-channel trigger architecture is a similar solution in which multiple channels are managed on one processing board. Four channels correspond to four sub-bands, and all four channels are on one processing board. There is no switching of bandwidth acquisition modes, and no transmission interaction between channels needs to be processed. It is simple and direct to determine the trigger source.

[0003] When parallel processing boards and parallel multi-channel architectures are required, and accurate trigger response is required when switching between full-bandwidth and half-bandwidth modes, the trigger control of the DBI sampling architecture will become more complicated, and there will be inter-board signal transmission between multiple FPGA and multi-processing boards. If the signal transmission is unstable or the trigger control is inaccurate, the spliced ​​waveform data will be distorted, and the collected waveform cannot be displayed stably. Currently, there is no processing solution for mutual transmission, synchronization, and optimization of effective trigger channels and effective trigger sub-bands corresponding to multiple channels of parallel multi-FPGA and multi-processing boards, and there is no trigger solution for accurate judgment and response of triggers for sub-band multiplexing under bandwidth channel acquisition mode switching. In addition, because the storage read and write enable signals and trigger signals in the DBI sampling architecture of parallel processing boards and parallel multi-channels need to be transmitted between each FPGA, if asynchrony or metastable state occurs during the signal transmission process, it will cause waveform distortion or shaking. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a trigger control method based on FPGA parallel broadband DBI architecture. By selecting any channel as the trigger source, the input waveform can be correctly triggered and stably displayed, and the waveform can be stably triggered according to the preset trigger conditions.

[0005] The objective of the present invention is achieved through the following technical scheme: a trigger control method based on FPGA parallel broadband DBI architecture, the FPGA parallel DBI architecture includes a multiplexer, 2 sub-band decomposition filter groups, 8 sub-band acquisition modules, a processing board A and a processing board B; each sub-band acquisition module includes an ADC acquisition card and an FPGA acquisition card; the trigger control method includes: S1. After the input signal passes through the multiplexer, it is input to two sub-band analysis filter banks respectively; each sub-band analysis filter bank decomposes the input signal into four sub-band signals, each sub-band signal corresponds to a sub-band acquisition module; S2. The four sub-band signals decomposed by the first sub-band decomposition filter group pass through the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and enter the processing board A; the four sub-band signals decomposed by the second sub-band decomposition filter group pass through the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and enter the processing board B; S3. Each FPGA acquisition card of each sub-band acquisition module is equipped with an independent trigger detection and judgment subsystem for real-time monitoring of the trigger status of all sub-band channels; for the input signal, the FPGA acquisition card of each sub-band acquisition module detects the generation of a trigger signal that meets the user's preset trigger condition, and the trigger flag signal is activated, confirming that a trigger event has occurred in the sub-band acquisition module at this moment; S4. If a trigger signal is generated by each sub-band acquisition module, the generated trigger signal will be sent to the post-processing board. The post-processing board will collect the trigger signals of all sub-band acquisition modules at the front end at the same time, and make channel selection judgment on the trigger according to the channel acquisition mode and trigger source preset by the user, select a valid trigger signal, and then generate a synchronization signal group sync_group to perform read and write control on the sub-band acquisition module corresponding to the post-processing board.

[0006] Preferably, the post-processing board refers to processing board A or processing board B, and both processing board A and processing board B are FPGA processing boards.

[0007] Preferably, the processing board A or the processing board B includes a trigger communication synchronization processing module, a trigger channel selection and multi-sub-band trigger judgment module and a trigger signal control processing module.

[0008] Preferably, step S4 comprises: S401 triggers the communication synchronization processing module, synchronously receives the trigger flag signal of each sub-band acquisition module, and transmits it to the trigger channel selection and multi-sub-band trigger judgment module; S402. Trigger channel selection and multi-subband trigger judgment module for selecting a valid trigger flag signal to be sent to the trigger signal control processing module; (1) The trigger channel selection and multi-subband trigger judgment module divides the channels according to the channel acquisition mode; the channel acquisition mode includes a full bandwidth mode of 80 GSPS and a half bandwidth mode of 40 GSPS; Assume that the 8 sub-band signals are recorded as sub-band 1 to sub-band 8; If the channel acquisition mode is full bandwidth mode 80GSPS, then: Sub-bands 1 to 4 are combined into one channel; Sub-bands 5 to 8 are combined into two channels; If the channel acquisition mode is half-bandwidth 40GSPS, then: Sub-bands 1 and 2 are combined into one channel; Sub-bands 3 and 4 are combined into two channels; Sub-bands 5 and 6 are combined into three channels; Sub-bands 7 and 8 are combined into four channels; (2) The trigger channel selection and multi-sub-band trigger judgment module receives the channel acquisition mode and trigger source set by the user, and determines the sub-band for which the trigger flag signal is valid: If the channel acquisition mode set by the user is the full bandwidth mode 80GSPS and the trigger source is one channel, the trigger flag signals of sub-bands 1 to 4 are valid; If the channel acquisition mode set by the user is the full bandwidth mode 80GSPS and the trigger source is two channels, the trigger flag signals of sub-bands 5 to 8 are valid; If the channel acquisition mode set by the user is half-bandwidth 40GSPS and the trigger source is one channel, the trigger flag signals of sub-bands 1 and 2 are valid; If the channel acquisition mode set by the user is half-bandwidth 40GSPS and the trigger source is two channels, the trigger flag signals of sub-bands 3 and 4 are valid; If the channel acquisition mode set by the user is half-bandwidth 40GSPS and the trigger source is three channels, the trigger flag signals of sub-bands 5 and 6 are valid; If the channel acquisition mode set by the user is half-bandwidth 40GSPS and the trigger source is four channels, the trigger flag signals of sub-bands 7 and 8 are valid; (3) The trigger channel selection and multi-sub-band trigger judgment module transmits the valid trigger flag signal to the trigger signal control processing module when there is a valid trigger flag signal in the trigger flag signals of each sub-band acquisition module; S403. After receiving a valid trigger flag signal, the trigger signal control processing module generates a synchronization control signal group sync_group to perform read and write control on the sub-band acquisition module corresponding to the post-processing board.

[0009] Preferably, in step S4, when the channel acquisition mode is the full bandwidth mode 80GSPS and the trigger source is one channel, the post-processing board that finally receives the valid trigger signal is processing board A; When the channel acquisition mode is half-bandwidth 40GSPS and the trigger source is one channel or two channels, the post-processing board that finally receives the valid trigger signal is processing board A; At this time, the synchronous control signal group sync_group generated by the processing board A needs to be synchronously transmitted to the processing board B; the processing boards A and B control the corresponding sub-band acquisition modules according to the same synchronous control signal group sync_group.

[0010] Preferably, in step S4, when the channel acquisition mode is the full bandwidth mode 80GSPS and the trigger source is two channels, the post-processing board that finally receives the valid trigger signal is the processing board B; When the channel acquisition mode is half-bandwidth 40GSPS and the trigger source is three-channel or four-channel, the post-processing board that finally receives the valid trigger signal is processing board B; At this time, the synchronous control signal group sync_group generated by the processing board B needs to be synchronously transmitted to the processing board A; the processing boards A and B control the corresponding sub-band acquisition modules according to the same synchronous control signal group sync_group.

[0011] Preferably, the synchronization control signal group sync_group includes 4 identical control signals, each of which is a FIFO storage reset signal, a write enable signal or a read enable signal in the FPGA acquisition card.

[0012] Preferably, in step S403, after receiving a valid trigger flag signal, the trigger signal control processing module generates a synchronization control signal group sync_group, and then needs to perform transmission synchronization control. After the transmission synchronization control is completed, the sub-band acquisition module corresponding to the post-processing board is read and written; The process of transmission synchronization control is as follows: A1. The post-processing board sends test data to the FPGA acquisition card of each corresponding sub-band acquisition module, and the test data includes a test sequence and a sending time; A2. The FPGA acquisition card of each sub-band acquisition module has the same test sequence as that of the post-processing board stored locally. Before receiving the test data, the FPGA acquisition card first delays the test data through the delay module, then receives it and times the receiving time. The transmission delay is calculated based on the timing result and the sending time of the test sequence, and the received test sequence is compared with the locally stored test sequence: If the test sequence received by each sub-band acquisition module is the same as the test sequence stored locally, proceed to step A3; If there is a sub-band acquisition module whose received test sequence is different from the locally stored test sequence, it is considered that a metastable state has occurred, and the process returns to step A1; A3. The FPGA acquisition card of each sub-band acquisition module transmits the calculated transmission delay to the host computer, and the host computer adjusts the delay module to ensure that the transmission delay between the post-processing board and the FPGA acquisition card of each sub-band acquisition module is the same. At this time, the transmission synchronization control is completed; A4. The post-processing board sends a synchronization control signal group sync_group to the FPGA acquisition card of the corresponding sub-band acquisition module to realize read and write control.

[0013] The beneficial effects of the present invention are as follows: 1. The present invention can select any channel as a trigger source in different bandwidth modes and channel modes, can trigger correctly, and can simultaneously associate other channels to trigger together.

[0014] 2. The present invention solves the problem of trigger jitter caused by metastable state that may occur during the transmission of storage control signals between multiple sub-bands, or the problem that a stable trigger point cannot be found and the waveform shakes severely; or the waveform flashes suddenly after a while, or multiple channels cannot be stably associated with the trigger, and even the waveform after the multi-sub-band waveform data is spliced ​​is seriously distorted. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the overall structure of the present invention; Figure 2 Trigger synchronization processing block diagram for multi-subband multi-FPGA parallel DBI architecture. DETAILED DESCRIPTION

[0016] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0017] The present invention selects a certain channel as the trigger source, which not only can stably trigger the trigger source channel, but also can synchronously trigger other channels. From the user application level, by selecting any channel as the trigger source, the input waveform can be correctly triggered and stably displayed; Considering that in the existing scheme, the selected trigger source channel does not input the waveform, but other channels input the waveform, it should not be triggered at this time. There was a phenomenon of channel error triggering before, which is likely to be the error in the judgment of the effective trigger sub-band to be discussed below; it should not be triggered but it is triggering the refresh waveform. Or, the channel source can be triggered stably, while other channels can be triggered, but they are unstable and shake in a small range; or, waveforms are input to channels 1 and 3, but not to channels 2 and 4, and it can be triggered when 2 or 4 is selected, but not when 3 is selected; at the same time, the present invention can respond to input signals in the 20GHZ frequency band range, and can stably trigger waveforms according to preset trigger conditions.

[0018] Edge triggering is the most basic and important triggering mode in the acquisition trigger system of a digital oscilloscope. Here we use edge triggering to illustrate the scheme of our acquisition trigger system. Other triggering modes, such as pulse width triggering, runt triggering, slope triggering, and other triggering knowledge can be changed to set the trigger conditions. The entire system divides the 20GHz frequency bandwidth into four frequency sub-bands based on the DBI (digital bandwidth alternating) sampling technology. The sampling rate of each frequency sub-band is 20GSPS and the frequency bandwidth is 5GHz, corresponding to a set of ADC+FPGA acquisition arrays. The single sub-band implements the ADC sampling array based on the TI (time alternating) sampling technology, corresponding to an FPGA acquisition board.

[0019] like Figure 1 As shown, a trigger control method based on FPGA parallel broadband DBI architecture, the FPGA parallel DBI architecture includes a multiplexer, 2 sub-band decomposition filter groups, 8 sub-band acquisition modules, a processing board A and a processing board B; each sub-band acquisition module includes an ADC acquisition card and an FPGA acquisition card; the trigger control method includes: S1. After the input signal passes through the multiplexer, it is input to two sub-band analysis filter banks respectively; each sub-band analysis filter bank decomposes the input signal into four sub-band signals, each sub-band signal corresponds to a sub-band acquisition module; S2. The four sub-band signals decomposed by the first sub-band decomposition filter group pass through the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and enter the processing board A; the four sub-band signals decomposed by the second sub-band decomposition filter group pass through the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and enter the processing board B; In order to respond to all input signals within the full bandwidth of 20GHZ and identify the trigger points in the waveform within the full bandwidth frequency band to ensure that the waveform information of interest within the full bandwidth can be captured, we decompose the signal sub-band into four sub-bands and collect and trigger the data of each sub-band respectively; The entire system achieves a maximum sampling rate of 80Gsps and a frequency bandwidth of 20Ghz. It can correctly collect all input signals, trigger and capture target signals, store them, and then display them.

[0020] like Figure 1 As shown, after the signal enters and exits any channel, it enters the sub-band decomposition filter bank through the multiplexer selection. The sub-band decomposition filter bank decomposes the signal into four sub-band signals, corresponding to 0-5GHz, 5-10GHz, 10-15GHz, and 15-20GHz respectively; each sub-band corresponds to a group of ADC+FPGA sub-band acquisition modules with a sampling rate of 20GSPS; The maximum sampling rate of the entire system is 80GSPS. After the FPGA corresponding to each sub-band acquisition module receives the 20GSPS sampling data output by the ADC, it caches the data for subsequent signal processing and performs trigger judgment on the data to capture trigger events.

[0021] S3. Each FPGA acquisition card of each sub-band acquisition module is equipped with an independent trigger detection and judgment subsystem for real-time monitoring of the trigger status of all sub-band channels; for the input signal, the FPGA acquisition card of each sub-band acquisition module detects the generation of a trigger signal that meets the user's preset trigger condition, and the trigger flag signal is activated, confirming that a trigger event has occurred in the sub-band acquisition module at this moment; S4. If a trigger signal is generated by each sub-band acquisition module, the generated trigger signal will be sent to the post-processing board. The post-processing board will collect the trigger signals of all sub-band acquisition modules at the front end at the same time, and make channel selection judgment on the trigger according to the channel acquisition mode and trigger source preset by the user, select a valid trigger signal, and then generate a synchronization signal group sync_group to perform read and write control on the sub-band acquisition module corresponding to the post-processing board.

[0022] Different acquisition channel modes, 80GSPS and 40GSPS acquisition channel modes, have different sub-band combinations and different effective trigger options. The four sub-band acquisition modules at the front end generate four trigger signal paths, namely ACQ_TRIG1, ACQ_TRIG2, ACQ_TRIG3, ACQ_TRIG4. The four sub-band trigger signals are input into the multi-sub-band trigger selection and judgment module. The trigger channel and the multi-sub-band trigger selection and judgment module will select a valid trigger signal according to the channel mode and trigger source currently selected by the user, and are used to generate and output the final first-level trigger signal trig_out. Classification: 80GSPS sampling mode, bandwidth 20GHZ, four sub-bands combined into one channel, two channels in total The 1234 sub-bands are combined into one channel; the trigger signals of sub-bands 1, 2, 3, and 4 are the effective sub-band trigger signals of one channel; The 5678 sub-bands are combined into three channels; the trigger signals of sub-bands 5, 6, 7, and 8 are the effective sub-band trigger signals of the three channels; 40GSPS adoption mode, frequency bandwidth 10GHZ, two sub-bands combined into one channel, a total of four channels Sub-bands 1 and 2 are combined into one channel, and the trigger signal of sub-bands 1 and 2 is the effective sub-band trigger signal of channel one; Sub-bands 3 and 4 are combined into two channels, and the trigger signal of sub-bands 3 and 4 is the effective sub-band trigger signal of channel two; Sub-bands 5 and 6 are combined into three channels, and the trigger signals of sub-bands 5 and 6 are the effective sub-band trigger signals of the three channels; Sub-bands 7 and 8 are combined into four channels, and the trigger signals of sub-bands 7 and 8 are the effective sub-band trigger signals of the four channels; like Figure 2 As shown, the two processing boards receive the trigger signals ACQ_TRIG1, ACQ_TRIG2, ACQ_TRIG3, ACQ_TRIG4 and the trigger position signals trig_loct1, trig_loct2, trig_loct3, trig_loct4 sent by the four acquisition cards at the front end of each of them respectively; after the trigger signal is processed by the trigger channel selection and the multi-sub-band trigger selection judgment, a valid trigger signal is generated, and then the trigger signal control processing module generates a read and write enable signal for the front-stage storage FIFO, and the storage read and write control signal generates a synchronous 8-way read and write enable synchronization signal group, which is synchronously sent to each ADC+FPGA sub-band acquisition module of the front stage, thereby controlling the data access of each sub-band; it can also be seen from the figure that the trigger signal is transmitted through multiple boards and distributed to 8 acquisition cards. Each transmission link will have different delays, instability, transmission metastable state and other problems. This leads to waveform asynchrony, which in turn leads to waveform data errors in the subsequent multi-sub-band data splicing, or trigger instability and other problems.

[0023] A multi-sub-band synchronous transmission method is specially designed to ensure synchronous control and stable transmission of signals between multiple sub-bands, thereby achieving stable triggering of the waveform.

[0024] After the software is sent to start acquisition, a reset signal is sent first, and then write enable is sent to start storage. Write enable is sent to processing board A through PCIE. On the one hand, the processing board sends the start write enable to the storage read and write control signal generation module of processing board A and processing board B, and on the other hand, it is sent to the trigger signal control processing module to control the trigger functions such as pre-triggering, post-triggering, trigger release, and read enable generation. The FIFO storage read signal generated by the trigger signal control processing module is sent to the storage read and write control signal generation module. The storage read / write control signal generation module generates the FIFO storage reset and read / write synchronization control signal group of the front-stage acquisition card according to the received reset, write enable and read enable signals, sync_groupx, x=1,2,3,4; this signal group includes: FIFO storage reset, write enable and read enable. Sync_groupx is sent to the front 4 acquisition cards at the same time, and the B board will also receive a group of sync_groupx, and then synchronously copy 4 copies, which are also sent to the corresponding front-stage 4 acquisition cards of the B board; the sync_groupx of the B board and the sync_groupx of the A board are synchronous with the same source.

[0025] The sync_groupx generated by the storage read / write control signal generation module of AB will be sent to their respective signal synchronization sending modules at the same time; the signal synchronization sending module mainly completes the cross-clock domain synchronization transmission of the signal and the synchronous transmission control between the acquisition card; Before officially transmitting signals, configure to send test signals and enter test mode; During the test, the control signal receiving module will receive the pattern sequence from the sending module, send it to the IDEALY module for delay, and then perform timing and transmission delay calculation. The storage control signal synchronization within a single acquisition board is achieved by comparing the received signal and the local signal. On this basis, all acquisition boards in the acquisition system are processed in the same way, and finally the obtained groups of synchronization flag signals sync_status are sent to the host computer for multi-channel board synchronization determination. The FPGA acquisition card of each sub-band acquisition module transmits the calculated transmission delay to the host computer, and the host computer adjusts the delay module to ensure that the transmission delay between the post-processing board and the FPGA acquisition card of each sub-band acquisition module is the same. At this time, the transmission synchronization control is completed; Each acquisition board simultaneously receives the storage control signal and the trigger position synchronization signal sent by the processing board, which includes the storage control signal group and the trigger fine positioning signal.

[0026] The processing board receives the trigger signal and trigger positioning signal from eight acquisition boards at the same time. The trigger signal goes through the above synchronous transmission control process; the trigger positioning signal needs to be processed from parallel to serial before transmission, and then sent back to each acquisition card through the signal synchronous transmission module. The acquisition card stores and obtains the same accurate trigger position, which is convenient for the subsequent software to calculate the data reading position according to the trigger position.

[0027] The present invention is more complex in the selection and judgment of multi-sub-band and multi-channel, especially the interaction and combination control of multi-acquisition boards and multi-processing boards; on the one hand, the control logic is relatively complex, and on the other hand, the transmission synchronization is relatively troublesome; but there is also an advantage that the FPGA resources and processing capacity of a single processing board cannot bear the data transmission and signal processing of too many acquisition cards at the front end; multiple processing boards can reduce the requirements of each processing board on chip performance resources, and the parallel processing speed will be faster. At the same time, it can provide a method for realizing data acquisition, processing, and trigger control of more channels in the future; adopting the parallel DBI multi-sub-band solution, in the absence of a higher sampling rate and bandwidth ADC, a high-speed high-bandwidth acquisition system with a higher sampling rate and higher bandwidth can be realized by using a low-bandwidth, low-sampling rate ADC. The trigger control of this architecture is also relatively complex. After the implementation of this solution, the high-speed high-bandwidth acquisition system can stably acquire the trigger waveform. Otherwise, if the trigger control is unstable, the spliced ​​waveform data may be distorted, and the acquired waveform cannot be stably displayed, not to mention the stable display of multi-channel waveforms, which is a very important requirement for high-bandwidth and high-sampling rate oscilloscopes.

[0028] The above is a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A trigger control method based on FPGA parallel broadband DBI architecture, characterized in that: The FPGA-based parallel DBI architecture includes a multiplexer, two sub-band decomposition filter banks, eight sub-band acquisition modules, a processing board A and a processing board B; each sub-band acquisition module includes an ADC acquisition card and an FPGA acquisition card; the trigger control method includes: S1. After the input signal passes through the multiplexer, it is input to two sub-band analysis filter banks respectively; each sub-band analysis filter bank decomposes the input signal into four sub-band signals, each sub-band signal corresponds to a sub-band acquisition module; S2. The four sub-band signals decomposed by the first sub-band decomposition filter group pass through the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and enter the processing board A; the four sub-band signals decomposed by the second sub-band decomposition filter group pass through the ADC acquisition card and FPGA acquisition card of the corresponding sub-band acquisition module and enter the processing board B; S3. Each FPGA acquisition card of each sub-band acquisition module is equipped with an independent trigger detection and judgment subsystem for real-time monitoring of the trigger status of all sub-band channels; for the input signal, the FPGA acquisition card of each sub-band acquisition module detects the generation of a trigger signal that meets the user's preset trigger condition, and the trigger flag signal is activated, confirming that a trigger event has occurred in the sub-band acquisition module at this moment; S4. If a trigger signal is generated by each sub-band acquisition module, the generated trigger signal will be sent to the post-processing board. The post-processing board will collect the trigger signals of all sub-band acquisition modules at the front end at the same time, and make channel selection judgment on the trigger according to the channel acquisition mode and trigger source preset by the user, select a valid trigger signal, and then generate a synchronization signal group sync_group to perform read and write control on the sub-band acquisition module corresponding to the post-processing board.

2. The trigger control method based on FPGA parallel broadband DBI architecture according to claim 1, characterized in that: The post-processing board refers to processing board A or processing board B, and both processing board A and processing board B are FPGA processing boards.

3. The trigger control method based on FPGA parallel broadband DBI architecture according to claim 1, characterized in that: The processing board A or the processing board B includes a trigger communication synchronization processing module, a trigger channel selection and multi-sub-band trigger judgment module and a trigger signal control processing module.

4. The trigger control method based on FPGA parallel broadband DBI architecture according to claim 3 is characterized in that: The step S4 comprises: S401 triggers the communication synchronization processing module, synchronously receives the trigger flag signal of each sub-band acquisition module, and transmits it to the trigger channel selection and multi-sub-band trigger judgment module; S402. Trigger channel selection and multi-subband trigger judgment module for selecting a valid trigger flag signal to be sent to the trigger signal control processing module; (1) The trigger channel selection and multi-subband trigger judgment module divides the channels according to the channel acquisition mode; the channel acquisition mode includes a full bandwidth mode of 80 GSPS and a half bandwidth mode of 40 GSPS; Assume that the 8 sub-band signals are recorded as sub-band 1 to sub-band 8; If the channel acquisition mode is full bandwidth mode 80GSPS, then: Sub-bands 1 to 4 are combined into one channel; Sub-bands 5 to 8 are combined into two channels; If the channel acquisition mode is half-bandwidth 40GSPS, then: Sub-bands 1 and 2 are combined into one channel; Sub-bands 3 and 4 are combined into two channels; Sub-bands 5 and 6 are combined into three channels; Sub-bands 7 and 8 are combined into four channels; (2) The trigger channel selection and multi-sub-band trigger judgment module receives the channel acquisition mode and trigger source set by the user, and determines the sub-band for which the trigger flag signal is valid: If the channel acquisition mode set by the user is the full bandwidth mode 80GSPS and the trigger source is one channel, the trigger flag signals of sub-bands 1 to 4 are valid; If the channel acquisition mode set by the user is the full bandwidth mode 80GSPS and the trigger source is two channels, the trigger flag signals of sub-bands 5 to 8 are valid; If the channel acquisition mode set by the user is half-bandwidth 40GSPS and the trigger source is one channel, the trigger flag signals of sub-bands 1 and 2 are valid; If the channel acquisition mode set by the user is half-bandwidth 40GSPS and the trigger source is two channels, the trigger flag signals of sub-bands 3 and 4 are valid; If the channel acquisition mode set by the user is half-bandwidth 40GSPS and the trigger source is three channels, the trigger flag signals of sub-bands 5 and 6 are valid; If the channel acquisition mode set by the user is half-bandwidth 40GSPS and the trigger source is four channels, the trigger flag signals of sub-bands 7 and 8 are valid; (3) The trigger channel selection and multi-sub-band trigger judgment module transmits the valid trigger flag signal to the trigger signal control processing module when there is a valid trigger flag signal in the trigger flag signals of each sub-band acquisition module; S403. After receiving a valid trigger flag signal, the trigger signal control processing module generates a synchronization control signal group sync_group to perform read and write control on the sub-band acquisition module corresponding to the post-processing board.

5. The trigger control method based on FPGA parallel broadband DBI architecture according to claim 4, characterized in that: In step S4, when the channel acquisition mode is the full bandwidth mode 80GSPS and the trigger source is one channel, the post-processing board that finally receives the valid trigger signal is processing board A; When the channel acquisition mode is half-bandwidth 40GSPS and the trigger source is one channel or two channels, the post-processing board that finally receives the valid trigger signal is processing board A; At this time, the synchronous control signal group sync_group generated by the processing board A needs to be synchronously transmitted to the processing board B; the processing boards A and B control the corresponding sub-band acquisition modules according to the same synchronous control signal group sync_group.

6. The trigger control method based on FPGA parallel broadband DBI architecture according to claim 4, characterized in that: In step S4, when the channel acquisition mode is the full bandwidth mode 80GSPS and the trigger source is two channels, the post-processing board that finally receives the valid trigger signal is the processing board B; When the channel acquisition mode is half-bandwidth 40GSPS and the trigger source is three-channel or four-channel, the post-processing board that finally receives the valid trigger signal is processing board B; At this time, the synchronous control signal group sync_group generated by the processing board B needs to be synchronously transmitted to the processing board A; the processing boards A and B control the corresponding sub-band acquisition modules according to the same synchronous control signal group sync_group.

7. A trigger control method based on FPGA parallel broadband DBI architecture according to claim 5 or 6, characterized in that: The synchronization control signal group sync_group includes 4 identical control signals, each of which is a FIFO storage reset signal, a write enable signal or a read enable signal in the FPGA acquisition card.

8. The trigger control method based on FPGA parallel broadband DBI architecture according to claim 4, characterized in that: In step S403, after receiving a valid trigger flag signal, the trigger signal control processing module generates a synchronization control signal group sync_group, and needs to perform transmission synchronization control. After the transmission synchronization control is completed, the sub-band acquisition module corresponding to the post-processing board is read and written; The process of transmission synchronization control is as follows: A1. The post-processing board sends test data to the FPGA acquisition card of each corresponding sub-band acquisition module, and the test data includes a test sequence and a sending time; A2. The FPGA acquisition card of each sub-band acquisition module has the same test sequence as that of the post-processing board stored locally. Before receiving the test data, the FPGA acquisition card first delays the test data through the delay module, then receives it and times the receiving time. The transmission delay is calculated based on the timing result and the sending time of the test sequence, and the received test sequence is compared with the locally stored test sequence: If the test sequence received by each sub-band acquisition module is the same as the test sequence stored locally, proceed to step A3; If there is a sub-band acquisition module whose received test sequence is different from the locally stored test sequence, it is considered that a metastable state has occurred, and the process returns to step A1; A3. The FPGA acquisition card of each sub-band acquisition module transmits the calculated transmission delay to the host computer, and the host computer adjusts the delay module to ensure that the transmission delay between the post-processing board and the FPGA acquisition card of each sub-band acquisition module is the same. At this time, the transmission synchronization control is completed; A4. The post-processing board sends a synchronization control signal group sync_group to the FPGA acquisition card of the corresponding sub-band acquisition module to realize read and write control.

Images