Long-distance multi-channel synchronous clock transmission device

Abstract

The invention discloses a long-distance multi-channel synchronous clock transmission device, and relates to the technical field of electronic communication. The device comprises a main power dividing circuit and two clock transmission modules connected with the main power dividing circuit. The clock transmission module comprises a sub power division circuit and n output branches connected with the sub power division circuit, and n is a positive integer; the output branch comprises at least one low noise amplifier, a filter circuit and a matching adjusting circuit which are connected in sequence. Therefore, long-distance and high-power synchronous transmission of multiple paths of clock signals is realized.

Description

Technical Field

[0001] The present application relates to the field of electronic communication technology, and in particular to a long-distance multi-channel synchronous clock transmission device. Background Art

[0002] In modern digital circuit systems, clock signals play a vital role. They not only provide synchronization references for various components in the system, but are also essential to ensure the correct transmission and processing of data. At present, the well-known clock signal transmission methods include: LVDS (low voltage differential signal), LVPECL (low voltage positive emitter coupled logic), CML (current mode logic) and LVCMOS (low voltage complementary metal oxide semiconductor). Although these clock signal transmission methods have the characteristics of low power consumption, strong anti-interference ability, simple interface and high-speed transmission, they also have some fatal disadvantages.

[0003] First, although these clock signal transmission methods can achieve low power output, the output power is single, and in the scenario of long-distance transmission, the power is attenuated during the transmission process, resulting in the transmission power being unable to meet the input level requirements of the subsequent circuit. In addition, the frequency of the output clock signal is limited by the operating frequency of the clock driver chip, and the operating frequency of the existing clock driver chip is relatively low, making it impossible to achieve high-frequency clock drive.

[0004] Secondly, the output of high-frequency clock signals is often in the form of differential signals. Since differential signals are double-ended outputs, they are more inconvenient for long-distance transmission.

[0005] Finally, although the interfaces of these clock signal transmission methods are simple, the clock signal transmission process of the digital circuit system usually involves the synchronous transmission of multiple clock signals. The number of channels for clock signal transmission currently depends on the number of output channels of the clock driver chip, so the number of output channels is limited. Summary of the invention

[0006] The main purpose of the present application is to provide a long-distance multi-channel synchronous clock transmission device to achieve long-distance, high-power synchronous transmission of multi-channel clock signals.

[0007] To achieve the above-mentioned object, the present application provides a long-distance multi-channel synchronous clock transmission device, comprising a main power division circuit and two clock transmission modules connected to the main power division circuit;

[0008] The clock transmission module includes a sub-power division circuit and n output branches connected to the sub-power division circuit, where n is a positive integer;

[0009] The output branch includes at least one low noise amplifier, a filter circuit and a matching adjustment circuit which are connected in sequence.

[0010] Optionally, the two clock transmission modules are respectively a low-frequency clock transmission module and a high-frequency clock transmission module, the sub-power division circuit of the low-frequency clock transmission module is a low-frequency power division circuit, and the sub-power division circuit of the high-frequency clock transmission module is a high-frequency power division circuit.

[0011] Optionally, the high-frequency clock transmission module further includes a PLL phase-locked loop, one end of the PLL phase-locked loop is connected to the main power divider, and the other end of the PLL phase-locked loop is connected to the high-frequency power division circuit.

[0012] Optionally, n is a multiple of 2, and the low-frequency power division circuit includes n / 2 low-frequency sub-power division units, and the low-frequency sub-power division units include a first capacitor, a first inductor, a second inductor, a first resistor, a second capacitor and a third capacitor; one end of the first capacitor is connected to the output end of the main power division circuit to form a first node, and the other end of the first capacitor is grounded; one end of the first inductor is connected to the first node, the other end of the first inductor is connected to one end of the first resistor to form a second node, one end of the second capacitor is connected to the second node, and the other end of the second capacitor is grounded; one end of the second inductor is connected to the first node, the other end of the second inductor is connected to the other end of the first resistor to form a third node, one end of the third capacitor is connected to the third node, and the other end of the third capacitor is grounded.

[0013] Optionally, the inductance values ​​of the first inductor and the second inductor are set according to a target frequency, and the target frequency is a required frequency of a load.

[0014] Optionally, the high-frequency power division circuit includes a plurality of cascaded power dividers.

[0015] Optionally, the matching adjustment circuit includes a second resistor, a third resistor, a fourth resistor and a fourth capacitor; one end of the second resistor is connected to the filtering circuit to form a fourth node, the other end of the second resistor is connected to one end of the fourth capacitor to form a fifth node, and the other end of the fourth capacitor is connected to the output interface; one end of the third resistor is connected to the fourth node, the other end of the third resistor is grounded to form a sixth node; one end of the fourth resistor is connected to the fifth node, and the other end of the fourth resistor is connected to the sixth node.

[0016] Optionally, the resistance values ​​of the second resistor, the third resistor and the fourth resistor are determined according to the gain and target power of the low noise amplifier, and the target power is the required power of the load.

[0017] Optionally, the number and gain of the low noise amplifiers are determined according to the length and attenuation of the transmission cables of the long-distance multi-channel synchronous clock transmission device.

[0018] Optionally, the low noise amplifier, the PLL phase-locked loop, the low-frequency power division circuit and the high-frequency power division circuit are single-port.

[0019] The long-distance multi-channel synchronous clock transmission device of the present application replaces the traditional clock driving chip with a main power division circuit, a sub-power division circuit and a low-noise amplifier, so that the clock signal is amplified by the low-noise amplifier during long-distance transmission, thereby preventing the power attenuation of the clock signal and achieving stable long-distance transmission; secondly, multi-channel synchronous transmission of the clock signal is achieved through the main power division circuit, the sub-power division circuit and the n output branches of the two clock transmission modules; finally, the power of the last output clock signal is adjusted by the matching adjustment circuit, so that the power of the clock signal is more in line with the input level requirement of the subsequent circuit, thereby achieving high-power transmission of the clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of a long-distance multi-channel synchronous clock transmission device according to an embodiment of the present application;

[0021] Figure 2 is a schematic structural diagram of a low-frequency sub-power division unit in an embodiment of the present application;

[0022] Figure 3 It is a structural schematic diagram of a high-frequency power division circuit of an example of the present application;

[0023] Figure 4 It is a schematic diagram of the structure of the high-frequency power division circuit of an embodiment of the present application.

[0024] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] In modern digital circuit systems, clock signals play a vital role. They not only provide synchronization references for various components in the system, but are also essential to ensure the correct transmission and processing of data. With the increasing complexity of electronic devices and the increasing performance requirements, the quality of clock signals directly affects the stability and efficiency of the entire system. Therefore, designing efficient and reliable clock signal transmission devices has become a key challenge.

[0027] At present, several standard clock signal output types are widely used in the industry, including LVDS (low voltage differential signal), LVPECL (low voltage positive emitter coupled logic), CML (current mode logic) and LVCMOS (low voltage complementary metal oxide semiconductor). These technologies have achieved advantages such as low power consumption, strong anti-interference ability, simple interface design and high-speed data transmission to varying degrees. However, they also have some inherent limitations, which limit their application in wider or higher-level scenarios.

[0028] The above-mentioned clock signal transmission methods are mainly realized through clock driver chips. While these clock signal output methods achieve low power consumption, their output power is fixed and single. In some long-distance transmission scenarios, the power of the clock signal is attenuated during the transmission process, resulting in the output clock signal power being unable to meet the input level requirements of the subsequent circuit. In addition, the output frequency of these clock signal output methods is generally low because it is limited by the operating frequency of the clock driver chip, and therefore overly dependent on the performance of the clock driver chip. The operating frequencies of the existing clock driver chips on the market are all low, resulting in the above-mentioned clock signal output methods being unable to achieve high-frequency clock drive in some system circuits.

[0029] Secondly, the output of high-frequency clock signals is often in the form of differential signals. Compared with single-ended signals, differential signals require one more line and increase the area of ​​PCB. The requirements for routing on the PCB board are more stringent, and the symmetry of the two lines is very high, otherwise the noise suppression effect will be reduced, and the test will be more cumbersome than the test of single-ended signals. In addition, since the high-frequency clock signal is a differential double-ended output, it is more unfavorable for the clock signal to be transmitted over long distances through RF cables during system assembly.

[0030] Finally, although the interfaces of LVDS, LVPECL, CML, LVCMOS and other output methods are simple, a complete digital circuit system usually involves multiple clock signals, and the number of output channels of the above output methods depends entirely on the number of output channels of the clock driver chip. Therefore, the number of output channels of the clock signal is limited. In addition, since the output signal type of the clock driver chip is a square wave, it will generate very large harmonic components, and the nonlinear distortion of the clock signal is serious, which may even cause the normal operation of the system.

[0031] In summary, the traditional clock signal transmission device has certain limitations in design. With the update and iteration of electronic technology, the traditional clock circuit is far from meeting the working requirements of some digital circuit systems.

[0032] Based on this, an embodiment of the present application provides a long-distance multi-channel synchronous clock transmission device. By replacing the traditional clock driver chip with a main power division circuit, a sub-power division circuit and a low-noise amplifier, the inherent disadvantages of the transmission method with a clock driver chip are solved. The transmission of multiple clock signals is realized by the main power division circuit and the sub-power division circuit, and the number of transmission channels can be determined by the sub-power division circuit, and the number of transmission channels will not be limited; by setting a low-noise amplifier on each output branch, long-distance transmission of the clock signal is realized; by setting a high-frequency clock transmission module, the transmission of high-frequency clock signals can be realized; by setting a matching adjustment circuit on each output branch, the power of the final output clock signal is more in line with the input level requirements of the subsequent circuit.

[0033] Figure 1 Schematic diagram of a long-distance multi-channel synchronous clock transmission device according to an embodiment of the present application. Figure 1 As shown, the long-distance multi-channel synchronous clock transmission device may include a main power division circuit 100 and two clock transmission modules connected to the main power division circuit 100; the clock transmission module includes a sub-power division circuit and n output branches connected to the sub-power division circuit, where n is a positive integer; the output branch includes at least one low-noise amplifier, a filtering circuit, and a matching adjustment circuit connected in sequence.

[0034] In this embodiment, the clock signal is input into the long-distance multi-channel synchronous clock transmission device. First, the main power division circuit 100 adopts a symmetrical design to divide the clock signal into two clock signals with the same power, and the two clock signals are respectively input into two clock transmission modules. Taking a clock transmission module as an example, the clock signal is further divided into n clock signals with the same power through the sub-power division circuit of the clock transmission module; after the clock signal is divided into n clock signals with the same power by the sub-power division circuit, each clock signal passes through an amplifier, a low noise device, a filter circuit, and a matching adjustment circuit.

[0035] Among them, the low noise amplifier can amplify the clock signal to compensate for the attenuation of the clock signal power during the transmission process; the filter circuit can filter out the harmonics, stray and broadband noise of the clock signal, optimize the quality of the output clock signal, and make the clock signal output with high performance; finally, the matching adjustment circuit can realize the amplification or attenuation control of the clock signal output power, so as to meet the different power requirements of the load end. Finally, the output of any clock transmission module can be selected as the output of the entire long-distance multi-channel synchronous clock transmission device.

[0036] It should be noted that the number of low noise amplifiers can be determined according to the length of the transmission distance. If the transmission distance is long, more low noise amplifiers can be set; if the transmission distance is short, the number of low noise amplifiers can be appropriately reduced.

[0037] In some embodiments, the two clock transmission modules are a low-frequency clock transmission module 200 and a high-frequency clock transmission module 300, respectively. The sub-power division circuit of the low-frequency clock transmission module 200 is a low-frequency power division circuit, and the sub-power division circuit of the high-frequency clock transmission module 300 is a high-frequency power division circuit.

[0038] In this embodiment, the low-frequency clock transmission module 200 is used to transmit a low-frequency clock signal, that is, the low-frequency clock transmission module 200 ultimately outputs a low-frequency clock signal. The high-frequency clock transmission module 300 is used to transmit a high-frequency clock signal, that is, the high-frequency clock transmission module 300 ultimately outputs a high-frequency clock signal. Specifically, after the clock signal is input, the main power division circuit 100 divides the clock signal into two parts, and directly passes through the following steps: Figure 1 The low-frequency clock transmission module 200 shown in the figure directly divides, amplifies, filters, and matches the clock signal to output it as a high-stability, low-noise low-frequency reference clock. Figure 1 The high-frequency clock transmission module 300 shown in the figure directly performs power division, amplification, filtering and matching output on the clock signal. Most of the traditional clock signals are low-frequency clock signals of about 10MHz, 100MHz, 200MHz and 500MHz, while this high-frequency clock transmission module 300 can generate high-frequency clock signals ranging from 10MHz to as high as 10 GHz, which can cover a wider range of application scenarios.

[0039] Similarly, the sub-power division circuit of the low-frequency clock transmission module 200 can be a low-frequency power division circuit, which can be composed of simple devices. The sub-power division circuit of the high-frequency clock transmission module 300 can be a high-frequency power division circuit, which can be composed of multiple high-frequency power dividers.

[0040] In practical applications, it can be determined first whether the subsequent load end needs a low-frequency clock signal or a high-frequency clock signal. If the subsequent load end needs a low-frequency clock signal, the output of the low-frequency clock transmission module 200 is used as the output of the entire device; if the subsequent load end needs a high-frequency clock signal, the output of the high-frequency clock transmission module 300 is used as the output of the entire device.

[0041] In some implementations, the high-frequency clock transmission module 300 further includes a PLL phase-locked loop, one end of the PLL phase-locked loop is connected to the main power divider, and the other end of the PLL phase-locked loop is connected to the high-frequency power divider circuit.

[0042] Continue to refer Figure 1 In this embodiment, the high-frequency clock transmission module 300 also includes a PLL phase-locked loop, which is connected between the main power divider and the high-frequency power divider circuit. The PLL phase-locked loop can be controlled by VCO oscillation and FPGA chip. The high-frequency clock transmission module 300 serves as the reference frequency of the PLL phase-locked loop. Through the VCO oscillation and the configuration control of the PLL phase-locked loop chip by the FPGA chip, the low-frequency clock signal can be converted into a high-frequency clock signal.

[0043] It should be noted that the PLL phase-locked loop is a feedback control system that achieves synchronization with a reference signal by adjusting the frequency and phase of the output signal. The process of the PLL phase-locked loop converting a low-frequency clock signal into a high-frequency clock signal is as follows: First, set the appropriate division ratio and set a programmable divider inside the PLL, which can divide the low-frequency clock signal output by the VCO into a higher-frequency clock signal and feed it back to the phase detector. For example, if you want to convert a 10MHz reference clock to a 100MHz output clock, you can set a divider with a division ratio of 1 / 10 in the feedback path. At the beginning, the output frequency of the VCO may be different from the target frequency. The phase detector continuously monitors the phase difference between the feedback signal (the VCO output after the division) and the reference signal, and adjusts the control voltage of the VCO through the charge pump and loop filter until the phase and frequency of the two signals are consistent. At this point, the PLL has been "locked". Once the PLL enters the locked state, the VCO will run at a ratio higher than the reference frequency set by the divider. Continuing with the above example, if the division ratio is 1 / 10, the actual output frequency of the VCO will be 10 times the reference frequency, which means that the frequency is doubled from 10MHz to 100MHz.

[0044] The low-frequency power division circuit, high-frequency power division circuit, low-noise amplifier, filter circuit and matching adjustment circuit are introduced in detail below.

[0045] In some implementations, n is a multiple of 2, and the low-frequency power division circuit includes n / 2 low-frequency sub-power division units. Figure 2 Schematic diagram of the structure of the low-frequency sub-power division unit in the embodiment of the present application. Figure 2 As shown, the low-frequency sub-power division unit includes a first capacitor C1, a first inductor L1, a second inductor L2, a first resistor R1, a second capacitor C2 and a third capacitor C3.

[0046] Among them, one end of the first capacitor C1 is connected to the output end of the main power division circuit 100 to form a first node N1, and the other end of the first capacitor C1 is grounded; one end of the first inductor L1 is connected to the first node N1, the other end of the first inductor L1 is connected to one end of the first resistor R1 to form a second node N2, one end of the second capacitor C2 is connected to the second node N2, and the other end of the second capacitor C2 is grounded; one end of the second inductor L2 is connected to the first node N1, the other end of the second inductor L2 is connected to the other end of the first resistor R1 to form a third node N3, one end of the third capacitor C3 is connected to the third node N3, and the other end of the third capacitor C3 is grounded.

[0047] In this embodiment, the low-frequency power division circuit is composed of n / 2 low-frequency sub-power division units. Because each low-frequency sub-power division unit can divide the clock signal into two clock signals with the same power, if the output branch is n, then the low-frequency sub-power division units are n / 2, and each low-frequency sub-power division unit is combined and connected in a cascade manner. For example, if the output branch is 4, then the low-frequency sub-power division units are 2. Therefore, by cascading the low-frequency sub-power division units, rapid expansion is achieved to achieve the required number of channels.

[0048] This embodiment uses ordinary LC resistors and capacitors to build a low-frequency sub-power division unit. The input clock signal passes through two identical inductors (i.e., the first inductor L1 and the second inductor L2), and combines the matching of the differential first resistor R1 and the filtering of the second capacitor C2 and the third capacitor C3 to divide the clock signal. The low-frequency sub-power division unit adopts a symmetrical design and outputs two clock signals with the same power, that is, it realizes the function of 1-to-2. The low-frequency sub-power division unit is a power division circuit for 100M clock signals. The advantages of this power division circuit are simple implementation, low cost and good economy.

[0049] In some embodiments, the inductance values ​​of the first inductor L1 and the second inductor L2 can be set according to a target frequency, which is a required frequency of the load. Specifically, the inductance values ​​of the first inductor L1 and the second inductor L2 can be adjusted according to the target frequency required by the subsequent load end.

[0050] Figure 3 FIG. 1 is a schematic diagram of a high frequency power splitter circuit according to an example of the present application. Figure 3 As shown, in some embodiments, the high frequency power division circuit includes a plurality of cascaded power dividers.

[0051] Specifically, the selection of the power divider in the high-frequency power division circuit can be based on the frequency selection. The power divider of the corresponding frequency can be selected according to the target frequency required by the subsequent load end. If it is necessary to realize the transmission of multiple high-frequency clock signals, these power dividers can be cascaded.

[0052] The power divider can support high-frequency clock signals to pass through. Figure 3 The high-frequency power division circuit composed of the power divider in the example can support the transmission of clock signals in the 2.8GHz-7.4GHz frequency band, and has good amplitude balance and phase balance performance. The multi-channel clock signals after power division by the high-frequency power division circuit have high amplitude and phase consistency.

[0053] The high-frequency clock signal adopts the design of PLL phase-locked loop, combined with the existing PLL phase-locked loop technology level, which can achieve frequency output from low frequency to more than tens of GHz. According to actual needs, the PLL phase-locked loop of the corresponding frequency band is selected, and the PLL phase-locked loop integrates a frequency divider, which has the ability to output high-frequency and low-frequency clocks. Through this solution, high-frequency, low-frequency and even more frequency clock signals can be output simultaneously.

[0054] It can be understood that after the clock signal passes through the power divider, its power will gradually decrease as the number of output channels increases. In order to ensure that multiple clock signal outputs can be achieved while ensuring that the power of the output clock signal is not affected, a low-noise amplifier is provided in each output branch in the embodiment of the present application, and the low-noise amplifier is provided after the power divider.

[0055] In this embodiment, the low noise amplifier can be a currently available low noise amplifier. The structure of the low noise amplifier can be composed of an input matching network, a noise suppression network, an amplifier stage, an output matching network, a bias circuit, a package and a shield, etc., which will not be described in detail here.

[0056] In some embodiments, the number and gain of the low noise amplifiers are determined according to the length and attenuation of the transmission cable of the long-distance multi-channel synchronous clock transmission device. Specifically, as the transmission distance increases, the clock signal will experience more attenuation, which not only reduces the amplitude of the clock signal, but also may introduce additional noise, thereby affecting the quality of the clock signal.

[0057] In order to maintain the stability and integrity of the clock signal during transmission, the number of low-noise amplifiers needs to be adjusted according to the actual situation. Generally, after the clock signal passes through a certain length of cable, if the clock signal level is detected to be close to the noise floor, you should consider adding a low-noise amplifier. For particularly long transmission paths, the segmented amplification method can be used. That is, the entire transmission path is divided into several shorter sections, and a low-noise amplifier is placed between each section for signal amplification. This can not only effectively compensate for the attenuation caused by the cable, but also avoid the nonlinear distortion problem caused by excessive amplification of a single low-noise amplifier.

[0058] The clock signal can be amplified by a low-noise amplifier. A low-noise amplifier with a corresponding frequency band and gain is designed separately on each channel to improve the power and performance of the clock signal. The gain and number of low-noise amplifiers can be selected according to the length and attenuation of the transmission cable. If the transmission attenuation is large, a larger gain or multiple low-noise amplifiers can be used to achieve a larger gain. The design of this low-noise amplifier can ensure a larger clock signal output power while the circuit outputs multiple channels, which is convenient for long-distance transmission and can easily meet the input power requirements of the subsequent circuit.

[0059] Furthermore, the clock signal output by the low-noise amplifier is filtered by a single-point filtering circuit. The filtering circuit can select a suitable filter according to the frequency type and power of the clock signal, thereby filtering out the harmonics, spurious and broadband noise of the clock signal, optimizing the quality of the output clock signal, and ensuring high-performance output even when the clock signal has high power.

[0060] Furthermore, after the filter circuit outputs the filtered clock signal, the matching adjustment circuit is used to adjust the power of the clock signal, so that the output clock signal power can be flexibly adjusted according to the requirements of the subsequent load end, making the long-distance multi-channel synchronous clock transmission device of the embodiment of the present application more widely applicable. The matching adjustment circuit can use a digitally controlled attenuator or a π-type or T-type attenuator designed with resistors to attenuate and adjust the power of the clock signal.

[0061] Figure 4 Schematic diagram of the structure of the high-frequency power splitter circuit of the embodiment of the present application. Figure 4 As shown, in some implementations, the matching adjustment circuit includes a second resistor R2, a third resistor R3, a fourth resistor R4, and a fourth capacitor C4.

[0062] Among them, one end of the second resistor R2 is connected to the filtering circuit to form a fourth node N4, the other end of the second resistor R2 is connected to one end of the fourth capacitor C4 to form a fifth node N5, and the other end of the fourth capacitor C4 is connected to the output interface J10; one end of the third resistor R3 is connected to the fourth node N4, and the other end of the third resistor R3 is grounded to form a sixth node N6; one end of the fourth resistor R4 is connected to the fifth node N5, and the other end of the fourth resistor R4 is connected to the sixth node N6.

[0063] In some implementations, the resistance values ​​of the second resistor R2 , the third resistor R3 , and the fourth resistor R4 are determined according to the gain of the low noise amplifier and the target power, where the target power is the required power of the load.

[0064] In this embodiment, a matching adjustment circuit is introduced into each output branch, and a π-type network is built by using discrete components such as resistors and capacitors. By selecting appropriate resistance values ​​for the second resistor R2, the third resistor R3, and the fourth resistor R4, impedance matching and amplitude attenuation adjustment can be achieved. The attenuation value and impedance matching value can be calculated by connecting resistors in series and in parallel. Combined with the gain of the low-noise amplifier, the clock output power can be amplified or attenuated to meet the design requirements of different power requirements at the load end.

[0065] Specifically, assume that the input impedance is Zin, the output impedance is Zout, and the goal is to match Zin to Zout. For a π-type network, impedance matching can be achieved by selecting appropriate resistance values. For a π-type network, the input impedance Zin can be calculated using the following formula:

[0066]

[0067] Where jw is the angular frequency expressed as a complex number.

[0068] The adjustment principle of the matching adjustment circuit is: select the appropriate second resistor R2 and fourth resistor R4 so that the input impedance Zin is close to the required impedance value (for example, 50Ω); the fourth capacitor C4 connected in parallel is used to compensate for the impedance change at high frequency to ensure good matching in a wide frequency band. By adjusting the resistance value of the third resistor R3, the attenuation degree of the output voltage can be controlled. For example, if the output voltage of the output branch is expected to be half of the input voltage, the resistance value of the third resistor R3 can be the resistance value of the fourth resistor R4.

[0069] Furthermore, in some implementations, the low noise amplifier, the PLL phase-locked loop, the low frequency power division circuit, and the high frequency power division circuit are single ports.

[0070] It is understandable that in traditional circuits, clock signals generally exist in the form of differential signals. The reason is that differential signals transmit signals through two lines and transmit two signals with opposite phases at the same time, which can largely eliminate the influence of external noise on the signal, reduce common-mode interference, and improve the stability and accuracy of the clock signal. In addition, differential signals can more accurately control the timing relationship between various circuit modules. Since differential signals can reduce errors and delays in the signal transmission process, the overall performance of the entire system can be improved. However, differential signals need to be symmetrical and equal in length, and the winding is complex. They are easily interfered in long-distance transmission and are inconvenient for long-distance transmission. PCB differential cable transmission has certain advantages in short-distance single modules, but its disadvantages are more obvious for system-level board-to-board transmission scenarios or long-distance transmission scenarios.

[0071] Therefore, in each output branch, the low noise amplifier, PLL phase-locked loop, power divider, etc. that can be selected are all single-port, so the clock signal is designed as single-ended input and single-ended output. This design can not only simplify the circuit of the PCB board, but also facilitate transmission through RF cables. RF cables have good impedance characteristics and shielding effectiveness. The transmission frequency of the clock transmitted by RF cables is higher than that of PCB differential transmission, and it is easy to achieve low-loss transmission of signals above tens of GHz. It can also achieve the advantages of differential transmission anti-interference on PCB, and can eliminate some disadvantages of differential transmission. In this way, the disadvantages of excessive power attenuation caused by long-distance winding and transmission of PCB can be reduced, and electromagnetic shielding is taken into account. The use of RF cable transmission greatly reduces the transmission link receiving external interference and external radiation interference.

[0072] Therefore, by using the main power division circuit 100, the sub-power division circuit and the low-noise amplifier to replace the traditional clock driving chip, the inherent disadvantages of the transmission method with the clock driving chip are solved. The main power division circuit 100 and the sub-power division circuit are used to realize the transmission of multiple clock signals, and the number of transmission channels can be determined by the sub-power division circuit, and the number of transmission channels is not limited; by setting a low-noise amplifier on each output branch, the long-distance transmission of the clock signal is realized; by setting a high-frequency clock transmission module, the transmission of high-frequency clock signals can be realized; by setting a matching adjustment circuit on each output branch, the power of the final output clock signal is more in line with the requirements of the input level of the subsequent circuit.

[0073] The long-distance multi-channel synchronous clock transmission device of the embodiment of the present application solves the drawbacks of the traditional clock output channel being limited, low frequency, high harmonic spurious, fixed power, large transmission attenuation, and difficulty in designing the transmission PCB routing. With the rapid development of modern electronic technology, the signal bandwidth and sampling rate are getting larger and larger, and the demand for high-frequency and high-bandwidth acquisition clocks is increasing. The embodiment of the present application breaks through the limitations of traditional clock driver chips and can be widely used in the fields of homologous frequency conversion, high-speed acquisition, radar, communication, electronic countermeasures, etc.

[0074] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A long-distance multi-channel synchronous clock transmission device, characterized in that: It includes a main power division circuit and two clock transmission modules connected to the main power division circuit; The clock transmission module includes a sub-power division circuit and n output branches connected to the sub-power division circuit, where n is a positive integer; The output branch includes at least one low noise amplifier, a filter circuit and a matching adjustment circuit which are connected in sequence.

2. The long-distance multi-channel synchronous clock transmission device according to claim 1, characterized in that: The two clock transmission modules are respectively a low-frequency clock transmission module and a high-frequency clock transmission module. The sub-power division circuit of the low-frequency clock transmission module is a low-frequency power division circuit, and the sub-power division circuit of the high-frequency clock transmission module is a high-frequency power division circuit.

3. The long-distance multi-channel synchronous clock transmission device according to claim 2, characterized in that: The high-frequency clock transmission module also includes a PLL phase-locked loop, one end of the PLL phase-locked loop is connected to the main power divider, and the other end of the PLL phase-locked loop is connected to the high-frequency power division circuit.

4. The long-distance multi-channel synchronous clock transmission device according to claim 2, characterized in that: The n is a multiple of 2, the low-frequency power division circuit includes n / 2 low-frequency sub-power division units, and the low-frequency sub-power division unit includes a first capacitor, a first inductor, a second inductor, a first resistor, a second capacitor, and a third capacitor; One end of the first capacitor is connected to the output end of the main power dividing circuit to form a first node, and the other end of the first capacitor is grounded; One end of the first inductor is connected to the first node, the other end of the first inductor is connected to one end of the first resistor to form a second node, one end of the second capacitor is connected to the second node, and the other end of the second capacitor is grounded; One end of the second inductor is connected to the first node, the other end of the second inductor is connected to the other end of the first resistor to form a third node, one end of the third capacitor is connected to the third node, and the other end of the third capacitor is grounded.

5. The long-distance multi-channel synchronous clock transmission device according to claim 4, characterized in that: The inductance values ​​of the first inductor and the second inductor are set according to a target frequency, and the target frequency is a required frequency of a load.

6. The long-distance multi-channel synchronous clock transmission device according to claim 2, characterized in that: The high-frequency power division circuit includes a plurality of cascaded power dividers.

7. The long-distance multi-channel synchronous clock transmission device according to claim 1, characterized in that: The matching adjustment circuit includes a second resistor, a third resistor, a fourth resistor and a fourth capacitor; One end of the second resistor is connected to the filter circuit to form a fourth node, the other end of the second resistor is connected to one end of the fourth capacitor to form a fifth node, and the other end of the fourth capacitor is connected to the output interface; One end of the third resistor is connected to the fourth node, and the other end of the third resistor is grounded to form a sixth node; One end of the fourth resistor is connected to the fifth node, and the other end of the fourth resistor is connected to the sixth node.

8. The long-distance multi-channel synchronous clock transmission device according to claim 7, characterized in that: The resistance values ​​of the second resistor, the third resistor and the fourth resistor are determined according to the gain and target power of the low noise amplifier, and the target power is the required power of the load.

9. The long-distance multi-channel synchronous clock transmission device according to any one of claims 1 to 8, characterized in that: The number and gain of the low noise amplifiers are determined according to the length and attenuation of the transmission cables of the long-distance multi-channel synchronous clock transmission device.

10. The long-distance multi-channel synchronous clock transmission device according to claim 3, characterized in that: The low noise amplifier, the PLL phase-locked loop, the low-frequency power division circuit and the high-frequency power division circuit are single-port.

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