A server low-speed logic signal control system, method and storage medium

Abstract

The application discloses a kind of server low-speed logic signal control system, method and storage medium, comprising: main controller is used when monitoring power-on timing signal, obtains preset power control sequence;According to the timing enable signal corresponding to first power to be powered on of power control sequence generation;The timing enable signal corresponding to first power to be powered on is pushed to the timing signal bus between main controller and each slave controller;Slave controller is used for listening timing enable signal from timing signal bus, obtains power control sequence;Main controller and slave controller are also used for listening current power to be powered on from timing signal bus according to power control sequence;When determining that power-on control needs to be carried out, current power to be powered on is powered on control;When each power is powered on and completes, low-speed logic control is carried out according to the low-speed logic signal of current area received by the application.Shorten the line distance, reduce the complexity of mainboard line, shorten the time-consuming of evaluation optimization.

Description

Technical Field

[0001] This invention relates to the field of circuit board design technology, and in particular to a server low-speed logic signal control system, method, computer-readable storage medium, and computer program product. Background Technology

[0002] Servers require a controller to power on / off the central processing unit (CPU) and to perform low-speed logic control on peripheral cards. The low-speed signals throughout the server are largely similar across different manufacturers, with a single server motherboard containing nearly a thousand low-speed signals.

[0003] Due to layout limitations, a large number of low-speed signals inevitably pass through high-speed signal areas. In order to avoid high-speed signal lines and ensure the signal integrity of high-speed signal lines, it is necessary to route low-speed signal lines around the path and inevitably perform hole-punching and layer-changing processing, which greatly increases the line distance and further increases the complexity of the motherboard. Excessive hole-punching breaks up the power plane and greatly increases the evaluation and optimization time when processing the CPU power supply current.

[0004] In summary, effectively addressing the issues of long circuit distances, high motherboard circuit complexity, and time-consuming power supply current evaluation and optimization in current server low-speed logic signal control methods is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a server low-speed logic signal control system, which significantly shortens the line distance, reduces the complexity of the motherboard circuitry, and shortens the evaluation and optimization time when the central processing unit power supply is flowing. Another purpose of this invention is to provide a server low-speed logic signal control method, a computer-readable storage medium, and a computer program product.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] A server low-speed logic signal control system, comprising:

[0008] The main controller is used to acquire a preset power control sequence when a power-on timing signal is detected; generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence; push the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller and each slave controller; listen to the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that the current power supply to be powered on needs to be powered on, power on the current power supply to be powered on is performed; when all power supplies have been powered on, low-speed logic control is performed according to the received low-speed logic signal of the current area.

[0009] The controller is configured to listen to the timing enable signal from the timing signal bus and obtain the power control sequence; listen to the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that the current power supply to be powered on needs to be powered on, power on the current power supply to be powered on is performed; when all power supplies have been powered on, low-speed logic control is performed according to the received low-speed logic signal of the current region.

[0010] In one specific embodiment of the present invention, the main controller is specifically configured to control the current power supply to power on when it is determined that power-on enable control is required for the current power supply to be powered on; and to generate the identification information of the current power supply to be powered on when it is determined that identification information of the current power supply to be powered on needs to be generated, and to push the identification information of the current power supply to be powered on to the timing signal bus.

[0011] The slave controller is specifically configured to control the current power supply to power on when it is determined that power-on enable control is required; and to generate the identification information of the current power supply when it is determined that identification information of the current power supply needs to be generated, and push the identification information of the current power supply to the timing signal bus.

[0012] In one specific embodiment of the present invention, the main controller is specifically used to perform low-speed logic control through the integrated circuit bus between the main controller and each slave controller according to the received low-speed logic signal of the current area when all power supplies have been powered on; and to transmit the received functional signals that need to be responded to in a timely manner through the timing signal bus.

[0013] The slave controller is specifically used to perform low-speed logic control through the integrated circuit bus between the master controller and each slave controller based on the received low-speed logic signal of the current area when all power supplies have been powered on; and to transmit the received functional signals that require timely response through the timing signal bus.

[0014] A method for controlling low-speed logic signals in a server, comprising:

[0015] When the power-on timing signal is detected, the preset power control sequence is obtained;

[0016] The main controller generates a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and pushes the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller and each slave controller.

[0017] The master controller and each slave controller listen to the current power supply to be powered on from the timing signal bus according to the power control sequence;

[0018] When the main controller or each slave controller determines that power-on control needs to be performed on the power supply to be powered on, power-on control is performed on the power supply to be powered on.

[0019] When all power supplies have been powered on, the main controller and each slave controller perform low-speed logic control based on the received low-speed logic signals.

[0020] In one specific embodiment of the present invention, the deployment process of the timing signal bus is further included, the deployment process of the timing signal bus comprising:

[0021] Get the total number of power supplies to be powered on;

[0022] The number of timing signal buses between each pair of the master controller and each slave controller is determined based on the total number of power supplies.

[0023] The timing signal buses between the master controller and each slave controller are deployed according to the number of timing signal buses.

[0024] In one specific embodiment of the present invention, determining the number of timing signal buses between each pair of the master controller and each slave controller based on the total number of power supplies includes:

[0025] Obtain the lowest power of 2 that is greater than or equal to the total number of power supplies;

[0026] The lowest power of 2, which is greater than or equal to the total number of power supplies, is determined as the number of timing signal buses between each pair of the master controller and each slave controller.

[0027] In one specific embodiment of the present invention, when the main controller or each slave controller determines that power-on control of the current power supply to be powered on is required, power-on control of the current power supply to be powered on includes:

[0028] When the main controller or each slave controller determines that power-on enable control needs to be performed on the current power supply to be powered on, the controller controls the current power supply to be powered on.

[0029] When the master controller or each slave controller determines that the identification information of the current power supply to be powered on needs to be generated, the identification information of the current power supply to be powered on is generated and pushed to the timing signal bus.

[0030] In one specific embodiment of the present invention, the main controller and each slave controller perform low-speed logic control based on the received low-speed logic signal, including:

[0031] The master controller and each slave controller perform low-speed logic control through the integrated circuit bus between the master controller and each slave controller based on the received low-speed logic signals of the current region, and transmit the received functional signals that require timely response through the timing signal bus.

[0032] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the server low-speed logic signal control method described above.

[0033] A computer program product includes a computer program that, when executed by a processor, implements the steps of the server low-speed logic signal control method described above.

[0034] The server low-speed logic signal control system provided by this invention includes: a main controller, configured to acquire a preset power control sequence when a power-on timing signal is detected; generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence; push the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller and each slave controller; listen to the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that power-on control is required for the current power supply to be powered on, perform power-on control for the current power supply to be powered on; and when all power supplies have been powered on, perform low-speed logic control according to the received low-speed logic signal of the current region; and a slave controller, configured to listen to the timing enable signal from the timing signal bus and acquire the power control sequence; listen to the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that power-on control is required for the current power supply to be powered on, perform power-on control for the current power supply to be powered on; and when all power supplies have been powered on, perform low-speed logic control according to the received low-speed logic signal of the current region.

[0035] The beneficial effects of this invention are that by setting up multiple controllers, low-speed logic signals from different regions are connected to the corresponding controllers nearby. The main controller and each slave controller control the power supply to be powered on according to the acquired power control sequence and the current power supply to be powered on as detected from the timing signal bus. When all power supplies have been powered on, low-speed logic control is performed according to the received low-speed logic signals of the current region. This significantly shortens the line distance, reduces the complexity of the motherboard wiring, and greatly simplifies the wiring work of the server motherboard. It also avoids excessive drilling and shortens the evaluation and optimization time when the central processing unit power supply is powered on.

[0036] Accordingly, the present invention also provides a server low-speed logic signal control method, a computer-readable storage medium, and a computer program product corresponding to the above-mentioned server low-speed logic signal control method, which have the above-mentioned technical effects, and will not be elaborated here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a structural block diagram of a server low-speed logic signal control system in related technologies;

[0039] Figure 2 This is a block diagram of another server low-speed logic signal control system in related technologies.

[0040] Figure 3 This is a structural block diagram of a server low-speed logic signal control system according to an embodiment of the present invention;

[0041] Figure 4 This is a structural block diagram of another server low-speed logic signal control system in an embodiment of the present invention;

[0042] Figure 5 This is a flowchart illustrating an implementation method for controlling low-speed logic signals in a server according to an embodiment of the present invention.

[0043] Figure 6 This is a structural block diagram of a server low-speed logic signal control device according to an embodiment of the present invention.

[0044] The attached figures are labeled as follows:

[0045] 1-Master controller, 2-Slave controller. Detailed Implementation

[0046] Currently, server architecture generally consists of three main parts: a central processing unit, a baseboard management controller (BMC), and a complex programmable logic device (CPLD).

[0047] See Figure 1 , Figure 1 This is a block diagram of a low-speed logic signal control system for a server in related technologies. The central processing unit (CPU) is the core component of the server. The baseboard management controller (BDC) is a server-specific module that provides monitoring of temperature, voltage, fan speed, and bus speed, and offers a management interface for remote server management. Complex programmable logic devices (CPLDs) primarily control the power-on and power-off of the CPU and the low-speed logic of some peripheral boards.

[0048] See Figure 2 , Figure 2 This is a block diagram of another server low-speed logic signal control system in related technologies. Figure 2 The main layout of the server motherboard printed circuit board (PCB) is shown. The layouts are similar across different manufacturers. A single motherboard has nearly a thousand low-speed signals, and many of these low-speed signals need to be ultimately aggregated to the baseboard management controller and complex programmable logic devices.

[0049] Due to layout limitations, a large number of low-speed signals inevitably pass through high-speed signal areas. In order to avoid high-speed signal lines and ensure the signal integrity of high-speed signal lines, low-speed signal lines have to be routed around the path and inevitably require vias and layer changes. A single low-speed signal line requires multiple vias, which significantly increases the line distance and thus the complexity of the motherboard. At the same time, too many vias also break up the power plane, which significantly increases the evaluation and optimization time when processing the CPU power supply current.

[0050] Therefore, the server low-speed logic signal control system provided in this application significantly shortens the line distance, reduces the complexity of the motherboard circuitry, and shortens the evaluation and optimization time when the central processing unit power supply is flowing.

[0051] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] See Figure 3 , Figure 3 This is a structural block diagram of a server low-speed logic signal control system according to an embodiment of the present invention. The system may include:

[0053] The main controller 1 is used to acquire a preset power control sequence when a power-on timing signal is detected; generate a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence; push the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller 1 and each slave controller 2; listen to the current power supply to be powered on from the timing signal bus according to the power control sequence; when it is determined that the current power supply to be powered on needs to be powered on, it performs power-on control on the current power supply to be powered on; when all power supplies have been powered on, it performs low-speed logic control according to the received low-speed logic signal of the current area.

[0054] Controller 2 is used to listen to timing enable signals from the timing signal bus and obtain the power control sequence; according to the power control sequence, it listens to the current power supply to be powered on from the timing signal bus; when it is determined that the current power supply to be powered on needs to be powered on, it performs power-on control on the current power supply to be powered on; when all power supplies have been powered on, it performs low-speed logic control according to the received low-speed logic signal of the current area.

[0055] This invention provides a server low-speed logic signal control system, which includes a master controller 1 and a slave controller 2. The power supplies in the server need to be powered on and off according to a specific control sequence, and this control sequence is pre-set.

[0056] When the main controller 1 detects the power-on timing signal, it obtains the preset power control sequence, generates the timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and pushes the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller 1 and each slave controller 2, thereby controlling the first power supply to be powered on to be powered on, and enabling each slave controller 2 in the system to also obtain the specific power supply that is currently being powered on.

[0057] In the system, the timing enable (EN) signals of each power supply and the identification information generation signal (pwrgd) of the power supply to be powered are randomly distributed in different controllers. Slave controller 2 is used to listen for the timing enable signal from the timing signal bus and obtain the power control sequence. Master controller 1 and slave controller 2 listen for the power supply to be powered from the timing signal bus according to the power control sequence. When they determine that they need to control the power supply to be powered, they perform power-on control on the power supply to be powered. Master controller 1 and each slave controller 2 perform low-speed logic control on a certain area of ​​the server motherboard. When all power supplies have been powered on, they perform low-speed logic control according to the received low-speed logic signal of the current area. By grouping the low-speed logic signals of different areas according to the convenience of wiring, each low-speed logic signal line can be connected nearby, effectively solving the drawbacks of routing low-speed signals throughout the entire circuit board, greatly simplifying the circuit board wiring work, reducing the development difficulty for layout engineers, effectively improving the power integrity of high-speed signals, and enhancing the stability of the motherboard.

[0058] Low-speed logic signals refer to signals that transmit relatively slowly in digital circuits. Generally, low-speed logic signals typically have frequencies below a few kilohertz, low transmission rates, and relatively long rise and fall times. These signals are commonly found in simpler electronic devices, low-power applications, and some control systems. Compared to high-speed logic signals, low-speed logic signals have lower transmission delays and power consumption, and are also easier to process and analyze.

[0059] The main controller 1 can be any controller selected from multiple controllers. When an anomaly is detected in either the main controller 1 or any of the slave controllers 2, the controller closest to the anomaly is selected to take over the power-on control and low-speed logic control tasks, following the principle of proximity. Furthermore, when there are multiple closest controllers, the power-on control and low-speed logic control tasks can be distributed to the nearest controllers according to a load balancing strategy. Alternatively, the controller with the lowest current load can be selected from the nearest controllers to handle the corresponding power-on control and low-speed logic control tasks. By selecting the controller to replace the anomaly based on proximity, the wiring distance is shortened, the motherboard wiring complexity is reduced, and the server motherboard cabling is simplified. By selecting the controller to replace the anomaly based on load balancing, the resources of each controller are fully utilized, avoiding the allocation of too many tasks to any single controller and extending the controller's lifespan.

[0060] The master controller and each slave controller can be specifically configured as complex programmable logic devices, thereby making full use of the advantages of complex programmable logic devices such as high flexibility, high integration, low power consumption, good programmability and high reliability.

[0061] As can be seen from the above technical solution, by setting up multiple controllers, the low-speed logic signals of different areas are connected to the corresponding controllers nearby. The main controller and each slave controller control the power supply to be powered on according to the acquired power control sequence and the power supply to be powered on currently monitored from the timing signal bus. When all power supplies have been powered on, low-speed logic control is performed according to the received low-speed logic signals of the current area. This significantly shortens the line distance, reduces the complexity of the motherboard wiring, and greatly simplifies the wiring work of the server motherboard. It also avoids excessive drilling and shortens the evaluation and optimization time when the central processing unit power supply is powered on.

[0062] It should be noted that, based on the above embodiments, the present invention also provides corresponding improvements. In subsequent embodiments, steps identical or corresponding to those in the above embodiments can be referenced interchangeably, and their respective beneficial effects can also be referred to each other. These improvements will not be elaborated upon in the following improved embodiments.

[0063] In one specific embodiment of the present invention, the main controller 1 is specifically used to control the current power supply to power on when it is determined that power-on enable control is required; and to generate the identification information of the current power supply to power on when it is determined that identification information of the current power supply to power on needs to be generated, and to push the identification information of the current power supply to power on to the timing signal bus.

[0064] Controller 2 is specifically used to control the current power supply to power on when it is determined that power-on enable control is required; and to generate the identification information of the current power supply when it is determined that identification information of the current power supply needs to be generated, and push the identification information of the current power supply to the timing signal bus.

[0065] The master controller 1 and slave controller 2 are specifically used to control the power supply to be powered on when it is determined that power-on enable control is required, thereby enabling power-on control of the power supplies assigned to them for power-on control. When it is determined that identification information for the power supply to be powered on needs to be generated, the master controller 1 and slave controller 2 generate the identification information and push it to the timing signal bus. This allows the controllers responsible for powering on the power supply to perform power-on enable control based on the detected identification information. This significantly reduces the timing delay of interactions between controllers and improves the efficiency of low-speed logic signal control in the server.

[0066] In one specific embodiment of the present invention, the main controller 1 is specifically used to perform low-speed logic control through the integrated circuit bus between the main controller 1 and each slave controller 2 according to the received low-speed logic signal of the current area when all power supplies have been powered on; and to transmit the received functional signals that need to be responded to in a timely manner through the timing signal bus.

[0067] Slave controller 2 is specifically used to perform low-speed logic control through the integrated circuit bus between master controller 1 and each slave controller 2 based on the received low-speed logic signal of the current area when all power supplies have been powered on; and to transmit the received functional signals that need to be responded to in a timely manner through the timing signal bus.

[0068] The master controller 1 and slave controller 2 provided in this embodiment of the invention are specifically used to perform low-speed logic control based on the received low-speed logic signals of the current region through the inter-integrated circuit (I2C) bus between the master controller 1 and each slave controller 2 when all power supplies have been powered on. Data transmission between controllers with low real-time requirements is achieved by utilizing the inter-integrated circuit bus between each pair of master controller 1 and each slave controller 2. The master controller 1 and slave controller 2 transmit received functional signals requiring timely response through a timing signal bus, thereby achieving effective multiplexing of the timing signal bus.

[0069] See Figure 4 , Figure 4 This is a block diagram of another server low-speed logic signal control system in an embodiment of the present invention. Four complex programmable logic devices (CPLs) are used to manage the low-speed logic signals in segments. Data transmission between the CPLs is achieved using a 2+N+2 configuration. The first 2 represents the I2C bus between the CPLs, N represents the timing signal bus used to transmit timing signals or custom functions, and the second 2 represents a function selection pin. N, as a timing signal or custom function selection pin, can be set to 00 (N as a timing signal, executing power-on timing), 11 (N as a timing signal, executing power-down timing), 01 (N as custom function 1), and 10 (N as custom function 2). This completes the low-speed logic signal link design for the entire motherboard, allowing all low-speed signal lines to be connected locally, reducing the development difficulty for layout engineers and improving the stability of the motherboard.

[0070] See Figure 5 , Figure 5 This is a flowchart illustrating an implementation of a server low-speed logic signal control method according to an embodiment of the present invention. The method may include the following steps:

[0071] S501: When a power-on timing signal is detected, the preset power control sequence is obtained.

[0072] S502: The master controller generates the timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and pushes the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the master controller and each slave controller.

[0073] S503: The master controller and each slave controller listen to the current power supply to be powered on from the timing signal bus according to the power control sequence.

[0074] S504: When the main controller or each slave controller determines that the power supply to be powered on needs to be powered on, the power supply to be powered on is powered on.

[0075] S505: When all power supplies have been powered on, the main controller and each slave controller perform low-speed logic control based on the received low-speed logic signals.

[0076] As can be seen from the above technical solution, by setting up multiple controllers, the low-speed logic signals of different areas are connected to the corresponding controllers nearby. The main controller and each slave controller control the power supply to be powered on according to the acquired power control sequence and the power supply to be powered on currently monitored from the timing signal bus. When all power supplies have been powered on, low-speed logic control is performed according to the received low-speed logic signals of the current area. This significantly shortens the line distance, reduces the complexity of the motherboard wiring, and greatly simplifies the wiring work of the server motherboard. It also avoids excessive drilling and shortens the evaluation and optimization time when the central processing unit power supply is powered on.

[0077] In one specific embodiment of the present invention, a deployment process for a timing signal bus is also included, which comprises:

[0078] Get the total number of power supplies to be powered on;

[0079] The number of timing signal buses between each pair of the master controller and each slave controller is determined based on the total number of power supplies.

[0080] The timing signal buses between the master controller and each slave controller are deployed according to the number of timing signal buses.

[0081] When deploying the timing signal bus, the total number of power supplies to be powered on is obtained. Based on the total number of power supplies, the number of timing signal buses between each pair of the master controller and each slave controller is determined. The timing signal buses between each pair of the master controller and each slave controller are then deployed based on the number of timing signal buses. By determining the number of timing signal buses between the master controller and each slave controller based on the total number of power supplies to be powered on, the accurate transmission of timing signals is ensured, while avoiding the setting of too many redundant timing signal buses, thus reducing the complexity of the motherboard circuitry.

[0082] In one specific embodiment of the present invention, determining the number of timing signal buses between each pair of the master controller and each slave controller based on the total number of power supplies includes:

[0083] Get the lowest power of 2 that is greater than or equal to the total number of power supplies;

[0084] The number of timing signal buses between each pair of the master controller and each slave controller is determined by the lowest power of 2, which is greater than or equal to the total number of power supplies.

[0085] Obtain the lowest power of 2 greater than or equal to the total number of power supplies. Determine the number of timing signal buses between each pair of the master controller and each slave controller using the lowest power of 2. By determining the number of timing signal buses between each pair of the master controller and each slave controller using the lowest power of 2, accurate timing signal transmission is ensured, while avoiding excessive redundant timing signal buses, thus reducing the complexity of the motherboard circuitry.

[0086] See Table 1, which is a table showing the correspondence between the total number of power supplies and the number of timing signal buses in an embodiment of the present invention.

[0087] Table 1

[0088]

[0089] In one specific embodiment of the present invention, when the main controller or each slave controller determines that power-on control of the current power supply to be powered on is required, power-on control of the current power supply to be powered on includes:

[0090] When the main controller or each slave controller determines that the power supply to be powered on needs to be enabled, it controls the power supply to be powered on.

[0091] When the master controller or each slave controller determines that the identification information of the power supply to be powered on needs to be generated, the identification information of the power supply to be powered on is generated and pushed to the timing signal bus.

[0092] In one specific embodiment of the present invention, low-speed logic control is performed using a master controller and each slave controller based on received low-speed logic signals, including:

[0093] The master controller and each slave controller use the low-speed logic signals received from the current region to perform low-speed logic control through the integrated circuit bus between the master controller and each slave controller, and transmit the received functional signals that need to be responded to in a timely manner through the timing signal bus.

[0094] Corresponding to the above method embodiments, the present invention also provides a server low-speed logic signal control device, and the server low-speed logic signal control device described below can be referred to in correspondence with the server low-speed logic signal control method described above.

[0095] See Figure 6 , Figure 6 This is a structural block diagram of a server low-speed logic signal control device according to an embodiment of the present invention. The device may include:

[0096] The power control sequence acquisition module 61 is used to acquire a preset power control sequence when a power-on timing signal is detected.

[0097] The timing enable signal push module 62 is used to generate the timing enable signal corresponding to the first power supply to be powered on according to the power control sequence by the main controller, and push the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller and each slave controller.

[0098] The power supply monitoring module 63 is used to monitor the current power supply to be powered on from the timing signal bus according to the power control sequence by the main controller and each slave controller.

[0099] The power-on control module 64 is used to power on the power supply when the main controller or each slave controller determines that power-on control is required for the power supply to be powered on.

[0100] The low-speed logic control module 65 is used to perform low-speed logic control based on the received low-speed logic signals by the main controller and each slave controller when all power supplies have been powered on.

[0101] As can be seen from the above technical solution, by setting up multiple controllers, the low-speed logic signals of different areas are connected to the corresponding controllers nearby. The main controller and each slave controller control the power supply to be powered on according to the acquired power control sequence and the power supply to be powered on currently monitored from the timing signal bus. When all power supplies have been powered on, low-speed logic control is performed according to the received low-speed logic signals of the current area. This significantly shortens the line distance, reduces the complexity of the motherboard wiring, and greatly simplifies the wiring work of the server motherboard. It also avoids excessive drilling and shortens the evaluation and optimization time when the central processing unit power supply is powered on.

[0102] In one specific embodiment of the present invention, the device may further include:

[0103] The total number of power supplies acquisition module is used to obtain the total number of power supplies to be powered on.

[0104] The timing signal bus quantity determination module is used to determine the number of timing signal buses between each pair of the master controller and each slave controller based on the total number of power supplies.

[0105] The timing signal bus deployment module is used to deploy the timing signal bus between the master controller and each slave controller according to the number of timing signal buses.

[0106] In one specific embodiment of the present invention, the timing signal bus quantity determination module includes:

[0107] The lowest power acquisition submodule is used to obtain the lowest power of 2 that is greater than or equal to the total number of power supplies;

[0108] The timing signal bus quantity determination submodule is used to determine the number of timing signal buses between each pair of the master controller and each slave controller by using the lowest power of 2, which is greater than or equal to the total number of power supplies.

[0109] In one specific embodiment of the present invention, the power-on control module 64 includes:

[0110] The power-on control submodule is used to control the power supply to power on when the main controller or each slave controller determines that power-on enable control is required for the power supply to be powered on.

[0111] The identification information push submodule is used to generate the identification information of the power supply to be powered on when the master controller or each slave controller determines that the identification information of the power supply to be powered on needs to be generated, and push the identification information of the power supply to be powered on to the timing signal bus.

[0112] In one specific embodiment of the present invention, the low-speed logic control module 65 is specifically a module that uses the main controller and each slave controller to perform low-speed logic control through the integrated circuit bus between the main controller and each slave controller based on the received low-speed logic signal of the current region, and transmits the received functional signals that need to be responded to in a timely manner through the timing signal bus.

[0113] Corresponding to the above method embodiments, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the following steps:

[0114] When a power-on timing signal is detected, the preset power control sequence is obtained; the master controller generates a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and pushes the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the master controller and each slave controller; the master controller and each slave controller listen to the current power supply to be powered on from the timing signal bus according to the power control sequence; when the master controller or each slave controller determines that the current power supply to be powered on needs to be powered on, the power supply to be powered on is powered on; when all power supplies have been powered on, the master controller and each slave controller perform low-speed logic control according to the received low-speed logic signal.

[0115] The computer-readable storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0116] For a description of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments; the present invention will not be described in detail here.

[0117] Corresponding to the above method embodiments, the present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the server low-speed logic signal control method described above.

[0118] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods, computer-readable storage media, and computer program products disclosed in the embodiments are described simply because they correspond to the systems disclosed in the embodiments; relevant details can be found in the system section.

[0119] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A server low-speed logic signal control system, characterized in that, include: The main controller (1) is used to obtain the preset power control sequence when the power-on timing signal is detected; Generate the timing enable signal corresponding to the first power supply to be powered on according to the power control sequence; push the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller (1) and each slave controller (2); According to the power control sequence, the system listens for the current power supply to be powered on from the timing signal bus; when it is determined that the current power supply to be powered on needs to be powered on, the system performs power-on control on the current power supply to be powered on; when all power supplies have been powered on, the system performs low-speed logic control according to the received low-speed logic signal of the current region. The controller (2) is used to listen to the timing enable signal from the timing signal bus and obtain the power control sequence; According to the power control sequence, the system listens for the current power supply to be powered on from the timing signal bus; when it is determined that the current power supply to be powered on needs to be powered on, the system performs power-on control on the current power supply to be powered on; when all power supplies have been powered on, the system performs low-speed logic control according to the received low-speed logic signal of the current region. Among them, the main controller (1) is any controller selected from multiple controllers; when any controller in the main controller (1) or any of the slave controllers (2) is detected to be abnormal, the controller closest to the abnormal controller is selected according to the principle of proximity to take over the abnormal controller to perform the corresponding power-on control and low-speed logic control. When there are multiple controllers closest to the abnormal controller, the power-on control task and low-speed logic control task of the abnormal controller are assigned to each controller closest to the abnormal controller according to the load balancing strategy.

2. The server low-speed logic signal control system according to claim 1, characterized in that, The main controller (1) is specifically used to control the current power supply to power on when it is determined that power-on enable control is required for the current power supply to be powered on; and to generate the identification information of the current power supply to be powered on when it is determined that identification information of the current power supply to be powered on is required, and to push the identification information of the current power supply to be powered on to the timing signal bus. The slave controller (2) is specifically used to control the current power supply to power on when it is determined that power-on enable control is required; and to generate the identification information of the current power supply when it is determined that identification information of the current power supply needs to be generated, and to push the identification information of the current power supply to the timing signal bus.

3. The server low-speed logic signal control system according to claim 1 or 2, characterized in that, The main controller (1) is specifically used to perform low-speed logic control through the integrated circuit bus between the main controller (1) and each slave controller (2) based on the received low-speed logic signal of the current area when all power supplies have been powered on; and to transmit the received functional signals that need to be responded to in a timely manner through the timing signal bus. The slave controller (2) is specifically used to perform low-speed logic control through the integrated circuit bus between the master controller (1) and each slave controller (2) based on the received low-speed logic signal of the current area when all power supplies are powered on; and to transmit the received functional signals that need to be responded to in a timely manner through the timing signal bus.

4. A method for controlling low-speed logic signals in a server, characterized in that, include: When the power-on timing signal is detected, the preset power control sequence is obtained; The main controller generates a timing enable signal corresponding to the first power supply to be powered on according to the power control sequence, and pushes the timing enable signal corresponding to the first power supply to be powered on to the timing signal bus between the main controller and each slave controller. The master controller and each slave controller listen to the current power supply to be powered on from the timing signal bus according to the power control sequence; When the main controller or each slave controller determines that power-on control needs to be performed on the power supply to be powered on, power-on control is performed on the power supply to be powered on. When all power supplies have been powered on, the main controller and each slave controller perform low-speed logic control based on the received low-speed logic signals. Among them, the main controller (1) is any controller selected from multiple controllers; when any controller in the main controller (1) or any of the slave controllers (2) is detected to be abnormal, the controller closest to the abnormal controller is selected according to the principle of proximity to take over the abnormal controller to perform the corresponding power-on control and low-speed logic control. When there are multiple controllers closest to the abnormal controller, the power-on control task and low-speed logic control task of the abnormal controller are assigned to each controller closest to the abnormal controller according to the load balancing strategy.

5. The server low-speed logic signal control method according to claim 4, characterized in that, It also includes the deployment process of the timing signal bus, which includes: Get the total number of power supplies to be powered on; The number of timing signal buses between each pair of the master controller and each slave controller is determined based on the total number of power supplies. The timing signal buses between the master controller and each slave controller are deployed according to the number of timing signal buses.

6. The server low-speed logic signal control method according to claim 5, characterized in that, The number of timing signal buses between each pair of the master controller and each slave controller is determined based on the total number of power supplies, including: Obtain the lowest power of 2 that is greater than or equal to the total number of power supplies; The lowest power of 2, which is greater than or equal to the total number of power supplies, is determined as the number of timing signal buses between each pair of the master controller and each slave controller.

7. The server low-speed logic signal control method according to claim 4, characterized in that, When the main controller or each slave controller determines that power-on control is required for the power supply to be powered on, power-on control is performed on the power supply to be powered on, including: When the main controller or each slave controller determines that power-on enable control needs to be performed on the current power supply to be powered on, the controller controls the current power supply to be powered on. When the master controller or each slave controller determines that the identification information of the current power supply to be powered on needs to be generated, the identification information of the current power supply to be powered on is generated and pushed to the timing signal bus.

8. The server low-speed logic signal control method according to claim 4, characterized in that, The main controller and each slave controller perform low-speed logic control based on the received low-speed logic signals, including: The master controller and each slave controller perform low-speed logic control through the integrated circuit bus between the master controller and each slave controller based on the received low-speed logic signals of the current region, and transmit the received functional signals that require timely response through the timing signal bus.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the server low-speed logic signal control method as described in any one of claims 4 to 8.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the server low-speed logic signal control method as described in any one of claims 4 to 8.

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