Method and system for improving utilization efficiency of DRAM in SSD and storage medium

Abstract

The invention discloses a method and system for improving the utilization efficiency of a DRAM in an SSD and a storage medium, and belongs to the technical field of solid state disks. The method comprises the following steps of: exposing a DRAM (Dynamic Random Access Memory) in an SSD (Solid State Disk) to a host in a virtual memory manner, and storing an FTL (Flash Transfer Layer) by using the DRAM in the virtual The SSD processes missing page interruption of the virtual memory, counts the number of times of missing page interruption, and detects whether memory shortage exists in the use of the DRAM in the disk or not; if the internal memory of the DRAM in the disk is insufficient, triggering missing page interruption and notifying the host to make the host decide whether to reduce the internal memory; and the host informs the SSD of how much memory needs to be used through a command, and if the DRAM in the disk still cannot meet the requirement, the SSD reduces the memory use quantity of the FTL and negotiates the use quantity of the DRAM in the disk by the host. According to the method and the device, the idle DRAM in the SSD can be utilized to the maximum extent, resource waste is avoided, the bottleneck existing in the system is effectively solved, and the system performance is not influenced when the idle DRAM is efficiently utilized.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state disks, and in particular to a method, system and storage medium for improving DRAM utilization efficiency in an SSD disk. Background Art

[0002] In order to ensure performance, existing enterprise-level large-capacity SSDs are equipped with a large amount of DRAM to store the entire FTL mapping table. However, in many scenarios, not all mapping table entries are frequently accessed, resulting in a lot of DRAM being idle most of the time.

[0003] Solid State Disk (SSD), also known as solid state drive, is a hard disk made of solid-state electronic storage chip array. SSD consists of a controller and electronic storage chip (FLASH chip).

[0004] SSD provides random access based on LBA (logical block address). However, due to the characteristics of nand flash chips, each nand flash block only accepts sequential append writes. Therefore, when the application writes in a random manner, it needs to go through a mapping module (Flash Translate Layer, FTL) to convert the random LBA into the sequential address corresponding to the nand flash, namely FBA (Flash Block Address).

[0005] The mapping relationship between LBA and FBA is recorded in a mapping table. Since reading or writing requires accessing the mapping table first, in order to avoid the access to the mapping table becoming a performance bottleneck, in current enterprise-level high-performance SSDs, the entire mapping table is accessed in DRAM. For large-capacity disks, the mapping table will occupy a large amount of DRAM. For example, if each 4K LBA corresponds to a 4-byte table entry, the mapping table will occupy 4G of DRAM.

[0006] However, in many host scenarios, not all mapping table entries are frequently accessed: 1) Many business scenarios tend to focus on some hot data. In this case, only part of the DRAM is frequently accessed, and the remaining DRAM is idle most of the time. 2) Some host business scenarios are computationally intensive and have higher requirements for DRAM. If the host is not configured with enough DRAM, the overall business performance will be reduced. Even if the disk performance is guaranteed, the overall performance cannot meet the demand. If the idle DRAM of the disk can be used, there may be no need to add new DRAM.

[0007] Currently, NVMe SSD provides CMB, which can expose the DRAM in the disk to the host through PCIe BAR. However, the DRAM exposed to the host is the DRAM outside the mapping table. The mapping table still occupies the same size of DRAM. The DRAM corresponding to CMB is the newly added DRAM, and the idle DRAM in the mapping table is still not used. Summary of the invention

[0008] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a method, system and storage medium for improving the utilization efficiency of DRAM in an SSD disk.

[0009] The object of the present invention is achieved through the following technical solutions: The first aspect of the present invention provides: a method for improving the utilization efficiency of DRAM in an SSD disk, comprising the following steps: SSD exposes the DRAM in the disk to the host in the form of virtual memory, and also uses DRAM to store FTL in the form of virtual memory. When FTL accesses the FTL virtual memory space, it first searches the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it directly accesses it. If not, a page fault interrupt is generated and the page fault interrupt processing flow is executed. The SSD processes the page fault interrupts of the virtual memory and counts the number of page fault interrupts to detect whether there is a shortage of DRAM in the disk. If there is a shortage of DRAM in the disk, the host is notified by sending an interrupt to the host, allowing the host to decide whether to reduce the memory. The host tells the SSD how much memory to use through commands. If the DRAM in the disk still cannot meet the demand, the SSD reduces the amount of memory used by the FTL. The SSD continues to detect the DRAM in the disk. If there is memory shortage or idle memory again, the SSD increases the number of FTLs used according to the situation or notifies the host by sending an interrupt to the host, and negotiates the host's use of the DRAM in the disk again.

[0010] Preferably, the page fault interrupt processing flow includes the following steps: Determine whether there is idle physical DRAM. If so, allocate idle physical DRAM. If not, determine whether the virtual memory address is frequently accessed. If not, access the data on the nand. If it is frequently accessed, find out the physical DRAM to be eliminated based on the LRU principle. Determine whether the data on the physical DRAM needs to be saved to nand. If necessary, save it to nand and update the nand address of the original module page table; then query the nand address corresponding to the virtual memory address and load the data to the physical DRAM; then allocate the physical DRAM to the module page table corresponding to the virtual memory address; If the data on the physical DRAM does not need to be saved to the nand, the nand address corresponding to the virtual memory address is directly queried to load the data into the physical DRAM; then the physical DRAM is allocated to the module page table corresponding to the virtual memory address.

[0011] Preferably, when the SSD is powered on, the CMB page table is configured in the CMB page table address register. When the host accesses the CMB subsequently, the PCIe module passes the address to the NVME module. The NVMe module queries the CMB page table content through CPTR. When there is physical DRAM in the page table, the physical DRAM address is taken out and the physical DRAM is accessed. If there is no physical DRAM in the page table, a page fault interrupt is triggered and the page fault interrupt processing flow is entered.

[0012] Preferably, the SSD negotiates with the host to use the physical DRAM including the following steps: When the SSD detects that the physical DRAM is idle beyond the preset value or the number of page fault interrupts exceeds the preset number, the SSD counts the total virtual memory usage of the FTL, and subtracts the total virtual memory usage of the FTL from the total physical DRAM to obtain the available amount; The SSD triggers an interrupt to inform the host of the total amount and available amount of physical DRAM on the SSD; The host determines how many CMBs to use based on the total amount of physical DRAM and available capacity of the SSD, and informs the SSD of the CMB usage; After the SSD receives the CMB usage, if the CMB usage is greater than the available amount, it compresses the physical DRAM that can be used by the FTL and allocates the freed physical DRAM to the CMB. The SSD subtracts the host's CMB usage from the total physical DRAM and provides the remaining physical DRAM to the FTL. The FTL's virtual memory is set according to the remaining physical DRAM to avoid frequent page fault interrupts. When the virtual memory address cannot send the entire mapping table, the FTL dynamically loads and saves part of the mapping table.

[0013] The second aspect of the present invention provides: a system for improving the utilization efficiency of DRAM in an SSD disk, which is used to implement any of the above methods for improving the utilization efficiency of DRAM in an SSD disk, comprising: The virtual memory module is used to use the SSD to expose the DRAM in the disk to the host in the form of virtual memory, and also use the DRAM to store FTL in the form of virtual memory. When FTL accesses the FTL virtual memory space, it first searches the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it directly accesses it. If not, a page fault interrupt is generated and the page fault interrupt processing flow is executed. The page fault interrupt processing module is used to use the SSD to process the page fault interrupt of the virtual memory, count the number of page fault interrupts, and detect whether there is a shortage of DRAM in the disk; if the DRAM in the disk is short of memory, the host is notified by sending an interrupt to the host, so that the host can decide whether to reduce the memory; The memory negotiation module is used to inform the SSD how much memory is needed through commands. If the DRAM in the disk still cannot meet the demand, the SSD reduces the amount of memory used by the FTL. The SSD continues to detect the DRAM in the disk. If there is memory shortage or idle memory again, the SSD increases the amount of FTL used or notifies the host by sending an interrupt to the host, and negotiates again the amount of DRAM used by the host.

[0014] The third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned methods for improving the utilization efficiency of DRAM in an SSD disk is implemented.

[0015] The beneficial effects of the present invention are: 1) Through the present invention, the idle DRAM inside the SSD can be utilized to the maximum extent, avoiding resource waste and effectively solving the bottleneck of the system. Moreover, when the idle DRAM is efficiently utilized, the system performance is not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of a method for improving the utilization efficiency of DRAM in an SSD disk; Figure 2 This is a schematic diagram of the virtual memory mechanism of SSD; Figure 3 This is a flow chart of page fault interrupt processing; Figure 4 This is a schematic diagram of the hardware address translation framework; Figure 5 Flowchart for negotiating DRAM usage between an SSD and a host. DETAILED DESCRIPTION

[0017] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0018] First, the professional terminology of the present invention is explained: SSD: Solid State Disk (Solid State Drive), also known as solid-state drive, is a hard disk made of an array of solid-state electronic storage chips.

[0019] nand: nand flash chip, solid-state electronic storage chip, flash medium used to store data.

[0020] LBA: Logical Block Address. The host side abstracts the SSD into a continuous logical block address and accesses it randomly.

[0021] FBA: Flash Block Address, the address used by the nand flash block.

[0022] FTL: Flash Translation Layer, a module used to convert LBA to FBA.

[0023] CMB: Controller Memory Buffer. CMB allows the SSD controller to map internal memory to the host, allowing the host to directly access the memory.

[0024] BAR: Base Address Register, a set of registers of PCIe devices, used to map the address space inside the PCIe device.

[0025] See also Figure 1-Figure 5 The first aspect of the present invention provides: a method for improving the utilization efficiency of DRAM in an SSD disk, comprising the following steps: SSD exposes the DRAM in the disk to the host in the form of virtual memory, and also uses DRAM to store FTL in the form of virtual memory. When FTL accesses the FTL virtual memory space, it first searches the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it directly accesses it. If not, a page fault interrupt is generated and the page fault interrupt processing flow is executed. The SSD processes the page fault interrupts of the virtual memory and counts the number of page fault interrupts to detect whether there is a shortage of DRAM in the disk. If there is a shortage of DRAM in the disk, the host is notified by sending an interrupt to the host, allowing the host to decide whether to reduce the memory. The host tells the SSD how much memory to use through commands. If the DRAM in the disk still cannot meet the demand, the SSD reduces the amount of memory used by the FTL. The SSD continues to detect the DRAM in the disk. If there is memory shortage or idle memory again, the SSD increases the number of FTLs used according to the situation or notifies the host by sending an interrupt to the host, and negotiates the host's use of the DRAM in the disk again.

[0026] In this embodiment, the DRAM in the disk is exposed to the host so that the host can use the DRAM, and dynamically allocate the DRAM in the disk according to the access situation of the mapping table and the host's use of the DRAM in the disk, so that the utilization rate of the DRAM in the disk reaches the optimal level, and the situation of insufficient DRAM in the host can be effectively alleviated. Figure 2 As shown in the figure, the virtual memory mechanism is used to expose the idle DRAM in the disk to the host, and provide the physical DRAM in the disk to the FTL of the SSD and the host in the form of virtual memory. The criterion for judging idle memory is the memory that has not been accessed in the past certain period of time. Assuming that there is 4G DRAM in the disk, the host and FTL can each use independent 4G memory space. But they all use virtual memory space. The virtual memory space of the FTL is mapped to the physical DRAM through the FTL page table, and the virtual memory space of the host is exposed to the host in the form of CMB. The virtual memory space of the host is mapped to the physical DRAM on the disk through the CMB page table.

[0027] In some embodiments, the page fault interrupt processing process includes the following steps: Determine whether there is idle physical DRAM. If so, allocate idle physical DRAM. If not, determine whether the virtual memory address is frequently accessed. If not, access the data on the nand. If it is frequently accessed, find out the physical DRAM to be eliminated based on the LRU principle. Determine whether the data on the physical DRAM needs to be saved to nand. If necessary, save it to nand and update the nand address of the original module page table; then query the nand address corresponding to the virtual memory address and load the data to the physical DRAM; then allocate the physical DRAM to the module page table corresponding to the virtual memory address; If the data on the physical DRAM does not need to be saved to the nand, the nand address corresponding to the virtual memory address is directly queried to load the data into the physical DRAM; then the physical DRAM is allocated to the module page table corresponding to the virtual memory address.

[0028] In this embodiment, if Figure 3 As shown, the page fault interrupt program will try to allocate new idle DRAM memory to the module page table. If there is no idle physical DRAM, the page fault interrupt program will perform the following processing according to the access frequency of the virtual address and the current physical DRAM usage: 1. If the virtual address is frequently accessed, the corresponding physical DRAM is selected for elimination according to the LRU principle, and the physical DRAM is allocated to the module page table.

[0029] 2. If the virtual address is not frequently accessed, directly access the data to nand. If it is a read operation, read the data on nand according to the nand address in the module page table and return it. If it is a write operation, save the data to nand and update the nand address to the module page table.

[0030] The process of eliminating physical memory is as follows: 1. If the data on the physical memory has not been saved to NAND, save the data to NAND and change the original module page table entry corresponding to the physical memory to the saved NAND address.

[0031] 2. If the nand address corresponding to the virtual address is valid, the data needs to be loaded from the nand address corresponding to the virtual address into the physical DRAM, and then the physical DRAM is allocated to the module page table.

[0032] In some embodiments, when the SSD is powered on, the CMB page table is configured into the CMB page table address register. When the host accesses the CMB subsequently, the PCIe module passes the address to the NVME module. The NVMe module queries the CMB page table content through the CPTR. When there is physical DRAM in the page table, the physical DRAM address is taken out and the physical DRAM is accessed. If there is no physical DRAM in the page table, a page fault interrupt is triggered and the page fault interrupt processing flow is entered.

[0033] In this embodiment, the traditional NVMe CMB function allows the host to access the CMB and directly access the on-disk memory through the NVMe master control without going through the SSD master control CPU. However, after the introduction of the virtual memory mechanism, it is necessary to first query the virtual memory page table, then find the physical DRAM, access the data, and also handle the scenario where the virtual memory does not correspond to the physical DRAM. Therefore, the CMB mechanism must be modified, and the SSD master control CPU must intervene. However, when the virtual memory can correspond to the physical DRAM, the SSD master control CPU intervenes in the access path, which will affect the performance of the CMB. In order to solve this problem, Figure 4As shown, the present invention introduces a hardware acceleration module to solve this problem, so that the host can efficiently use idle DRAM without affecting performance. The address conversion function of virtual memory is added to the NVMe hardware module. When the SSD is powered on, the CMB page table is configured to the CMB page table address register (CMBPageTableRegister, CPTR). When the host accesses the CMB later, when the PCIe module passes the address to the NVME module, the NVMe module queries the CMB page table content through CPTR. When there is physical DRAM in the page table, the physical DRAM address is taken out and the physical DRAM is accessed. If there is no physical DRAM in the page table, a page fault interrupt is triggered and the page fault interrupt processing flow is entered.

[0034] In some embodiments, the SSD negotiates with the host to use the physical DRAM including the following steps: When the SSD detects that the physical DRAM is idle beyond the preset value or the number of page fault interrupts exceeds the preset number, the SSD counts the total virtual memory usage of the FTL, and subtracts the total virtual memory usage of the FTL from the total physical DRAM to obtain the available amount; The SSD triggers an interrupt to inform the host of the total amount and available amount of physical DRAM of the SSD; The host determines how many CMBs to use based on the total amount of physical DRAM and available capacity of the SSD, and informs the SSD of the CMB usage; After the SSD receives the CMB usage, if the CMB usage is greater than the available amount, it compresses the physical DRAM that can be used by the FTL and allocates the freed physical DRAM to the CMB. The SSD subtracts the host's CMB usage from the total physical DRAM and provides the remaining physical DRAM to the FTL. The FTL's virtual memory is set according to the remaining physical DRAM to avoid frequent page fault interrupts. When the virtual memory address cannot send the entire mapping table, the FTL dynamically loads and saves part of the mapping table.

[0035] In this embodiment, when both CMB and FTL need to frequently access a large amount of physical memory, physical DRAM may be insufficient. In this scenario, the SSD will frequently enter page fault interrupts, affecting performance. When physical DRAM is insufficient, the SSD needs to negotiate with the host to use physical DRAM and agree on how to divide and share the DRAM in the disk so that the DRAM in the disk can be fully used with the highest efficiency. The negotiation process is as follows: Figure 5 shown.

[0036] The second aspect of the present invention provides: a system for improving the utilization efficiency of DRAM in an SSD disk, which is used to implement any of the above methods for improving the utilization efficiency of DRAM in an SSD disk, comprising: The virtual memory module is used to use the SSD to expose the DRAM in the disk to the host in the form of virtual memory, and also use the DRAM to store FTL in the form of virtual memory. When FTL accesses the FTL virtual memory space, it first searches the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it directly accesses it. If not, a page fault interrupt is generated and the page fault interrupt processing flow is executed. The page fault interrupt processing module is used to use the SSD to process the page fault interrupt of the virtual memory, count the number of page fault interrupts, and detect whether there is a shortage of DRAM in the disk; if the DRAM in the disk is short of memory, the host is notified by sending an interrupt to the host, so that the host can decide whether to reduce the memory; The memory negotiation module is used to inform the SSD how much memory is needed through commands. If the DRAM in the disk still cannot meet the demand, the SSD reduces the amount of memory used by the FTL. The SSD continues to detect the DRAM in the disk. If there is memory shortage or idle memory again, the SSD increases the amount of FTL used or notifies the host by sending an interrupt to the host, and negotiates again the amount of DRAM used by the host.

[0037] In this embodiment, the system for improving the utilization efficiency of DRAM in the SSD disk also includes: 1. Virtual memory page table: This page table is used to manage the mapping of virtual memory and physical memory, and its page table mapping format is consistent with the existing CPU page table format with MMU. Modules such as FTL that require the CPU to complete memory access can directly use the virtual memory function of the CPU. 2. Virtual memory nand page table: This page table is used to manage the mapping of virtual addresses and nand addresses. This page table is mainly used by the page fault interrupt function. As mentioned above, when directly operating nand or eliminating physical DRAM, it is necessary to search and update the page table. 3. Physical DRAM management module: This module is used to manage the usage of physical DRAM and the mapping relationship between physical DRAM and virtual memory. When physical DRAM needs to be eliminated, the module needs to find the eliminated physical DRAM according to the LRU principle, and find the virtual address originally corresponding to the eliminated physical DRAM and modify it.

[0038] The third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned methods for improving the utilization efficiency of DRAM in an SSD disk is implemented.

[0039] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A method for improving the utilization efficiency of DRAM in an SSD disk, characterized by: The following steps are involved: SSD exposes the DRAM in the disk to the host in the form of virtual memory, and also uses DRAM to store FTL in the form of virtual memory. When FTL accesses the FTL virtual memory space, it first searches the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it directly accesses it. If not, a page fault interrupt is generated and the page fault interrupt processing flow is executed. The SSD processes the page fault interrupts of the virtual memory and counts the number of page fault interrupts to detect whether there is a shortage of DRAM in the disk. If there is a shortage of DRAM in the disk, the host is notified by sending an interrupt to the host, allowing the host to decide whether to reduce the memory. The host tells the SSD how much memory to use through commands. If the DRAM in the disk still cannot meet the demand, the SSD reduces the amount of memory used by the FTL. The SSD continues to detect the DRAM in the disk. If there is memory shortage or idle memory again, the SSD increases the number of FTLs used according to the situation or notifies the host by sending an interrupt to the host, and negotiates the host's use of the DRAM in the disk again.

2. The method for improving the utilization efficiency of DRAM in an SSD disk according to claim 1, characterized in that: The page fault interrupt processing flow includes the following steps: Determine whether there is idle physical DRAM. If so, allocate idle physical DRAM. If not, determine whether the virtual memory address is frequently accessed. If not, access the data on the nand. If it is frequently accessed, find out the physical DRAM to be eliminated based on the LRU principle. Determine whether the data on the physical DRAM needs to be saved to nand. If necessary, save it to nand and update the nand address of the original module page table; then query the nand address corresponding to the virtual memory address and load the data to the physical DRAM; then allocate the physical DRAM to the module page table corresponding to the virtual memory address; If the data on the physical DRAM does not need to be saved to the nand, the nand address corresponding to the virtual memory address is directly queried to load the data into the physical DRAM; then the physical DRAM is allocated to the module page table corresponding to the virtual memory address.

3. The method for improving the utilization efficiency of DRAM in an SSD disk according to claim 1, characterized in that: When the SSD is powered on, the CMB page table is configured in the CMB page table address register. When the host accesses the CMB later, the PCIe module passes the address to the NVME module. The NVMe module queries the CMB page table content through CPTR. When there is physical DRAM in the page table, the physical DRAM address is taken out and the physical DRAM is accessed. If there is no physical DRAM in the page table, a page fault interrupt is triggered and the page fault interrupt processing flow is entered.

4. The method for improving the utilization efficiency of DRAM in an SSD disk according to claim 1, characterized in that: The SSD negotiates with the host to use physical DRAM in the following steps: When the SSD detects that the physical DRAM is idle beyond the preset value or the number of page fault interrupts exceeds the preset number, the SSD counts the total virtual memory usage of the FTL, and subtracts the total virtual memory usage of the FTL from the total physical DRAM to obtain the available amount; The SSD triggers an interrupt to inform the host of the total amount and available amount of physical DRAM of the SSD; The host determines how many CMBs to use based on the total amount of physical DRAM and available capacity of the SSD, and informs the SSD of the CMB usage; After the SSD receives the CMB usage, if the CMB usage is greater than the available amount, it compresses the physical DRAM that can be used by the FTL and allocates the freed physical DRAM to the CMB. The SSD subtracts the host's CMB usage from the total physical DRAM and provides the remaining physical DRAM to the FTL. The FTL's virtual memory is set according to the remaining physical DRAM to avoid frequent page fault interrupts. When the virtual memory address cannot send the entire mapping table, the FTL dynamically loads and saves part of the mapping table.

5. A system for improving the utilization efficiency of DRAM in an SSD disk, characterized by: The method for improving the utilization efficiency of DRAM in an SSD disk as claimed in any one of claims 1 to 4 comprises: The virtual memory module is used to use the SSD to expose the DRAM in the disk to the host in the form of virtual memory, and also use the DRAM to store FTL in the form of virtual memory. When FTL accesses the FTL virtual memory space, it first searches the FTL page table according to the virtual memory address. If the FTL page table has a corresponding physical memory address, it directly accesses it. If not, a page fault interrupt is generated and the page fault interrupt processing flow is executed. The page fault interrupt processing module is used to use the SSD to process the page fault interrupt of the virtual memory, count the number of page fault interrupts, and detect whether there is a shortage of DRAM in the disk; if the DRAM in the disk is short of memory, the host is notified by sending an interrupt to the host, so that the host can decide whether to reduce the memory; The memory negotiation module is used to inform the SSD how much memory is needed through commands. If the DRAM in the disk still cannot meet the demand, the SSD reduces the amount of memory used by the FTL. The SSD continues to detect the DRAM in the disk. If there is memory shortage or idle memory again, the SSD increases the amount of FTL used or notifies the host by sending an interrupt to the host, and negotiates again the amount of DRAM used by the host.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by the processor, the method for improving the utilization efficiency of DRAM in an SSD disk as described in any one of claims 1 to 4 is implemented.

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