Register and method for its production

Abstract

The application discloses a register and a preparation method thereof, and belongs to the technical field of semiconductors. The register comprises a signal input end, a signal output end and a clock control signal end, and further comprises a first transistor, a second transistor, a first inverter, a second inverter and a third inverter. In the first transistor and the second transistor, the gate of one is electrically connected with the clock control signal end through the first inverter, the gate of the other is directly electrically connected with the clock control signal end, in addition, the source of the first transistor is electrically connected with the signal input end, the drain of the first transistor is electrically connected with the source of the second transistor through the second inverter, and the drain of the second transistor is electrically connected with the signal output end through the third inverter. The register based on the above-mentioned circuit structure is perfect in function, simple in structure, small in resource consumption, and beneficial to reducing the area of the register.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a register and its fabrication method. Background Technology

[0002] A register is a circuit unit used to latch data in a computing system. Currently, a single register contains a large number of transistors, resulting in high resource consumption and a large area occupied by the register. In addition, traditional registers are based on silicon transistors, and the channel layer material of silicon transistors includes monocrystalline silicon. Although monocrystalline silicon has high mobility, its excessively high growth temperature limits its application in downstream processes. Summary of the Invention

[0003] This application provides a register and its fabrication method, wherein the register is based on a back-end transistor, aiming to reduce the register's resource consumption and area size. Furthermore, the channel layer material of the back-end transistor is a non-monocrystalline silicon material, eliminating dependence on silicon materials and avoiding high temperatures, thus protecting other fabricated film structures and allowing for a more flexible fabrication sequence.

[0004] In a first aspect, this application provides a register including a signal input terminal, a signal output terminal, and a clock control signal terminal. The register further includes a first transistor, a second transistor, a first inverter, a second inverter, and a third inverter. In the first and second transistors, the gate of one is electrically connected to the clock control signal terminal via the first inverter, and the gate of the other is directly electrically connected to the clock control signal terminal. Furthermore, the source of the first transistor is electrically connected to the signal input terminal, the drain of the first transistor is electrically connected to the source of the second transistor via the second inverter, and the drain of the second transistor is electrically connected to the signal output terminal via the third inverter.

[0005] In some embodiments, the first inverter includes a third transistor and a fourth transistor, the gates of the third transistor and the fourth transistor are electrically connected, the source of the third transistor is electrically connected to a first voltage terminal, the source of the fourth transistor is electrically connected to a second voltage terminal, and the drain of the third transistor is electrically connected to the drain of the fourth transistor. The second inverter includes a fifth transistor and a sixth transistor, the gates of the fifth transistor and the sixth transistor are electrically connected, the source of the fifth transistor is electrically connected to the first voltage terminal, the source of the sixth transistor is electrically connected to the second voltage terminal, and the drain of the fifth transistor is electrically connected to the drain of the sixth transistor. The third inverter includes a seventh transistor and an eighth transistor, the gates of the seventh transistor and the eighth transistor are electrically connected, the source of the seventh transistor is electrically connected to the first voltage terminal, the source of the eighth transistor is electrically connected to the second voltage terminal, and the drain of the seventh transistor is electrically connected to the drain of the eighth transistor.

[0006] In some embodiments, the register further includes a substrate, on which the first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, and eighth transistor are discretely arranged.

[0007] In some embodiments, the register further includes a substrate on which the first transistor, the second transistor, the first inverter, the second inverter, and the third inverter are disposed. Each of the first inverter, the second inverter, and the third inverter includes two transistors along a direction perpendicular to the substrate. At least one of the first inverter, the second inverter, and the third inverter is an inverter with a stacked structure, wherein the two transistors in the inverter with the stacked structure are stacked.

[0008] In some embodiments, the first transistor, the second transistor, the first inverter, the second inverter, and the third inverter are arranged discretely on the surface of the substrate.

[0009] In some embodiments, the first inverter, the second inverter, and the third inverter are all inverters with a stacked structure.

[0010] In some embodiments, both the first transistor and the second transistor are N-type transistors.

[0011] On the other hand, this application also provides a method for preparing a register, the register including a signal input terminal, a signal output terminal, and a clock control signal terminal, the preparation method including:

[0012] A first transistor, a second transistor, a first inverter, a second inverter, and a third inverter are formed on a substrate.

[0013] In the first transistor and the second transistor, the gate of one transistor is electrically connected to the clock control signal terminal through the first inverter, and the gate of the other transistor is directly electrically connected to the clock control signal terminal. In addition, the source of the first transistor is electrically connected to the signal input terminal, the drain of the first transistor is electrically connected to the source of the second transistor through the second inverter, and the drain of the second transistor is electrically connected to the signal output terminal through the third inverter.

[0014] In some embodiments, the first inverter includes a third transistor and a fourth transistor, the second inverter includes a fifth transistor and a sixth transistor, and the third inverter includes a seventh transistor and an eighth transistor.

[0015] Forming a first transistor, a second transistor, a first inverter, a second inverter, and a third inverter on a substrate includes:

[0016] The gates of a total of eight transistors are formed, namely the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor;

[0017] An active layer consisting of eight transistors—the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor—is formed.

[0018] The source and drain of a total of eight transistors are formed, namely the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor.

[0019] In some embodiments, at least one of the first inverter, the second inverter, and the third inverter is an inverter with a stacked structure along a direction perpendicular to the substrate, and the inverter with the stacked structure includes a lower transistor and an upper transistor.

[0020] The inverter with the stacked structure described above comprises:

[0021] This forms the source and drain of the transistor below;

[0022] The first active layer is formed to form the lower transistor;

[0023] Forming the common gate of the lower transistor and the upper transistor;

[0024] A second active layer is formed to form the upper transistor, and the second active layer is located on the side of the common gate away from the substrate;

[0025] This forms the source and drain of the transistor above.

[0026] In this embodiment, the register includes a first transistor, a second transistor, a first inverter, a second inverter, and a third inverter. In the first and second transistors, the gate of one is electrically connected to a clock control signal terminal via the first inverter, and the gate of the other is directly electrically connected to the clock control signal terminal. This allows the clock control signal to control one transistor to be on and the other to be off. Furthermore, the source of the first transistor is electrically connected to the signal input terminal, the drain of the first transistor is electrically connected to the source of the second transistor via the second inverter, and the drain of the second transistor is electrically connected to the signal output terminal via the third inverter.

[0027] Within one clock scan cycle, when the first transistor switches from the on state to the off state, the second transistor switches from the off state to the on state. At this time, the gate capacitor of the second inverter latches the signal acquired at the signal input terminal, and the signal output terminal outputs the signal acquired at the signal input terminal at this moment. When the first transistor switches from the off state to the on state, the second transistor switches from the on state to the off state. At this time, the gate capacitor of the third inverter latches the signal before the second transistor's state switch, that is, the signal output terminal continues to hold the signal output before the second transistor's state switch. The above process is repeated until the next clock scan cycle arrives, thereby realizing the function of the register. The register structure provided in this application embodiment is relatively simple, consumes less resources, and is beneficial to reducing the area of ​​the register.

[0028] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0029] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0030] Figure 1 A schematic diagram of the circuit structure of a register provided in an embodiment of this application;

[0031] Figure 2 A schematic diagram of the circuit structure of another register provided in an embodiment of this application;

[0032] Figure 3 The embodiments provided in this application are based on Figure 1 The waveform of the register shown;

[0033] Figure 4 This is a schematic diagram of the circuit structure of an inverter provided in an embodiment of this application;

[0034] Figure 5 This is a partial cross-sectional schematic diagram of a register provided in an embodiment of this application;

[0035] Figure 6 A partial cross-sectional schematic diagram of another register provided in an embodiment of this application;

[0036] Figure 7 A flowchart illustrating a method for preparing a register as provided in this application embodiment;

[0037] Figures 8-11 for Figure 7 The diagram shows the steps of the preparation method.

[0038] Figure 12A flowchart illustrating another method for preparing a register provided in an embodiment of this application;

[0039] Figures 13-20 for Figure 12 The diagram shows the steps of the preparation method. Detailed Implementation

[0040] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0041] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0042] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0043] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0044] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0045] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0046] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0047] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0048] Currently, registers contain a large number of transistors, resulting in high resource consumption and a large area footprint. For example, a typical register is implemented based on latches. A typical D latch includes four NAND gates, each with four transistors. A typical register consists of two D latches and one inverter, with the inverter containing two transistors. Therefore, a typical register contains 34 transistors. This leads to high resource consumption and large area overhead. Furthermore, traditional registers are based on silicon transistors. The channel layer material of silicon transistors is monocrystalline silicon. Although monocrystalline silicon has high mobility, its excessively high growth temperature limits its application in downstream processes.

[0049] To reduce the resource consumption and size of the register, this application provides a register based on a back-end transistor, whose fabrication method allows for a relatively flexible fabrication sequence.

[0050] like Figures 1-2 As shown, Figure 1 This is a schematic diagram of the circuit structure of a register provided in an embodiment of this application. Figure 2 This is a schematic diagram of the circuit structure of another register provided in an embodiment of this application.

[0051] like Figure 1 and Figure 2 As shown, register 10 includes a signal input terminal IN, a signal output terminal OUT, and a clock control signal terminal CLK. The signal input terminal IN is used to receive the signal to be acquired, the signal output terminal OUT is used to output the signal acquired by register 10, and the clock control signal terminal CLK is used to receive a clock scan signal and control the period of the signal acquired by register 10.

[0052] The register 10 also includes a first transistor 11, a second transistor 12, a first inverter 21, a second inverter 22, and a third inverter 23. Among them, the gate G of the first transistor 11 and the second transistor 12 is electrically connected to the clock control signal terminal CLK through the first inverter 21, and the gate G of the other transistor is directly electrically connected to the clock control signal terminal CLK.

[0053] For example, such as Figure 1 As shown, the gate G of the first transistor 11 is electrically connected to the clock control signal terminal CLK through the first inverter 21, and the gate G of the second transistor 12 is directly electrically connected to the clock control signal terminal CLK. Alternatively, as... Figure 2 As shown, the gate G of the second transistor 12 is electrically connected to the clock control signal terminal CLK through the first inverter 21, and the gate G of the first transistor 11 is directly electrically connected to the clock control signal terminal CLK.

[0054] In addition, the source S of the first transistor 11 is electrically connected to the signal input terminal IN, the drain D of the first transistor 11 is electrically connected to the source S of the second transistor 12 through the second inverter 22, and the drain D of the second transistor 12 is electrically connected to the signal output terminal OUT through the third inverter 23.

[0055] by Figure 1 Taking the circuit structure of register 10 as an example, within one scan cycle of the clock scan signal received by the clock control signal terminal CLK, when the clock scan signal is low, under the action of the first inverter 21, the signal received by the gate G of the first transistor 11 is high, the first transistor 11 is turned on, and the signal D collected by the signal input terminal IN is transmitted to node M through the first transistor 11. At this time, the signal of node M is D, and then it is transmitted to node N through the second inverter 22. At this time, the signal of node N is D inverted. At this time, since the signal received by the gate G of the second transistor 12 is low, the second transistor 12 is in the off state. Under the action of the gate capacitance (parasitic capacitance) of the third inverter 23, node P will latch and maintain the signal before the second transistor 12 was turned off, and the corresponding node Q will also maintain the previous signal. That is, at this time, the signal output by the signal output terminal OUT is unrelated to the signal collected by the signal input terminal IN, and the signal output by the signal output terminal OUT still maintains the signal of node Q before the second transistor 12 was turned off.

[0056] When the clock scan signal goes high, under the action of the first inverter 21, the signal received by the gate G of the first transistor 11 is low, the first transistor 11 is turned off, and the signal collected at the signal input terminal IN cannot be transmitted to node M. Furthermore, under the action of the gate capacitance (parasitic capacitance) of the first inverter 11, node M will latch and maintain the signal before the first transistor 11 was turned off; that is, the signal of node M is still D. Correspondingly, node N will also maintain its previous signal; that is, the signal of node N is still D-not. At this time, since the signal received by the gate G of the second transistor 12 is high, the second transistor 12 is turned on, and the signal D-not of node N will be transmitted to node P through the second transistor 12. The signal of node P is D-not. The signal of node P is transmitted to node Q through the third inverter 23, the signal of node Q is D, and the signal of node Q is output through the signal output terminal OUT; that is, the signal output terminal OUT outputs the signal D.

[0057] In other words, when the clock scan signal changes from low to high, node M latches the signal acquired at signal input terminal IN, and the signal output at signal output terminal OUT is the same as the signal acquired at signal input terminal IN at that moment. When the clock scan signal changes from high to low, regardless of whether the signal acquired at signal input terminal IN changes, the second transistor 12 turns off, and the signal output at signal output terminal OUT remains the same as the output signal before the second transistor 12 turned off. That is, at the rising edge of the clock scan signal, register 10 acquires and outputs the signal, and at the falling edge of the clock scan signal, the signal output by register 10 is consistent with the signal acquired at signal input terminal IN at the rising edge of the clock scan signal.

[0058] For example, such as Figure 3 As shown, Figure 3 Provided for embodiments of this application based on Figure 1 The waveform diagram of the register is shown below. The CLK waveform represents the clock scan signal, with one scan cycle being 1ms. The D waveform represents the signal acquired at the IN input terminal, and the Q waveform represents the signal output at the OUT output terminal. A 0 on each waveform indicates a low level, and a 1 indicates a high level. Based on the working principle described above, as... Figure 3 As shown, at the rising edge of the clock scan signal, i.e., the waveform CLK, register 10 acquires the signal, and the signal output by the signal output terminal OUT is the signal D acquired by the signal input terminal IN at this time. At the falling edge, register 10 latches and holds the signal acquired at the rising edge. The above process is repeated until the rising edge of the next clock scan cycle arrives, thus realizing the function of the register.

[0059] Similarly, such as Figure 2Register 10, as shown, acquires the signal at the falling edge of the clock scan signal, and latches the acquired signal while it is still at the rising edge, until the falling edge of the next scan cycle arrives, and then repeats the above process. Further details are omitted here.

[0060] The register 10 provided in this application embodiment has complete functions, a simpler structure compared with related technologies, saves resource consumption, reduces costs, and helps to reduce the area of ​​the register.

[0061] In some embodiments, taking the first inverter 21 as an example, such as Figure 4 As shown, Figure 4 The circuit structure diagram of the inverter provided in this application embodiment is shown. The first inverter 21 includes a third transistor 13 and a fourth transistor 14. The gate G of the third transistor 13 is electrically connected to the gate G of the fourth transistor 14, and the connection serves as the input terminal of the first inverter 21. The source S of the third transistor 13 is electrically connected to a first voltage terminal, and the source S of the fourth transistor 14 is electrically connected to a second voltage terminal. The drain D of the third transistor 13 is electrically connected to the drain D of the fourth transistor 14, and the connection serves as the output terminal of the first inverter 21. The first voltage terminal and the second voltage terminal are respectively the power supply voltage VDD and the ground voltage GND, and they need to match the conductivity types of the third transistor 13 and the fourth transistor 14. For example, Figure 4 The third transistor 13 shown is a P-type transistor, the fourth transistor 14 is an N-type transistor, the first voltage terminal is the power supply voltage VDD, and the second voltage terminal is the ground voltage GND.

[0062] Similarly, the second inverter 22 includes a fifth transistor 15 and a sixth transistor 16. The gate G of the fifth transistor 15 is electrically connected to the gate G of the sixth transistor 16, and the connection serves as the input terminal of the second inverter 22. The source S of the fifth transistor 15 is electrically connected to a first voltage terminal, and the source S of the sixth transistor 16 is electrically connected to a second voltage terminal. The drain D of the fifth transistor 15 is electrically connected to the drain D of the sixth transistor 16, and the connection serves as the output terminal of the second inverter 22.

[0063] The third inverter 23 includes a seventh transistor 17 and an eighth transistor 18. The gate G of the seventh transistor 17 is electrically connected to the gate G of the eighth transistor 18, and the connection between them serves as the input terminal of the third inverter 23. The source S of the seventh transistor 17 is electrically connected to a first voltage terminal, and the source S of the eighth transistor 18 is electrically connected to a second voltage terminal. The source S of the seventh transistor 17 is electrically connected to the drain D of the eighth transistor 18, and the connection between them serves as the output terminal of the third inverter 23.

[0064] In the embodiments of this application, the first inverter 21, the second inverter 22 and the third inverter 23 each include two transistors. Based on this, the register 10 includes 8 transistors, which greatly saves resource consumption, reduces costs and helps to reduce the area of ​​the register 10 compared with the 34 transistors in the related art.

[0065] The register 10 also includes a substrate 101, on which the first transistor 11, the second transistor 12, the first inverter 21, the second inverter 22, and the third inverter 23 are disposed. Furthermore, in some embodiments, the first transistor 11, the second transistor 12, the first inverter 21, the second inverter 22, and the third inverter 23 are arranged discretely on the surface of the substrate 101.

[0066] Exemplary, in some embodiments, such as Figure 5 As shown, Figure 5 This is a partial cross-sectional schematic diagram of a register provided in an embodiment of this application. The first transistor 11, the second transistor 12, the third transistor 13, the fourth transistor 14, the fifth transistor 15, the sixth transistor 16, the seventh transistor 17, and the eighth transistor 18 are all arranged discretely on the surface of the substrate 101. Figure 5 The diagram only shows the partial film structure of the third transistor 13 and the fourth transistor 14.

[0067] That is, in this embodiment, the first inverter 21, the second inverter 22, and the third inverter 23 all adopt a planar structure, and the two transistors included in each inverter are all laid flat on the substrate 101. The eight transistors included in the register 10 are all laid flat on the substrate 101. Based on this, in this embodiment, the area overhead of the register 10 is equivalent to the area occupied by the eight transistors laid flat on the substrate 101.

[0068] Exemplary, in some embodiments, such as Figure 6 As shown, Figure 6 This is a partial cross-sectional schematic diagram of another register provided in an embodiment of this application. At least one of the first inverter 21, the second inverter 22 and the third inverter 23 is an inverter with a stacked structure. An inverter with a stacked structure refers to an inverter in which two transistors are stacked.

[0069] The stacked structure is as follows Figure 6 As shown, taking the third transistor 13 and the fourth transistor 14 of the first inverter 21 as an example, in the direction perpendicular to the substrate 101, the fourth transistor 14 is located above the third transistor 13. That is, on the substrate 101, the area overhead of the first inverter 21 is equivalent to the area occupied by one transistor laid flat on the substrate 101.

[0070] For example, in some embodiments, the first inverter 21, the second inverter 22, and the third inverter 23 are all inverters with a stacked structure. That is, the area overhead of the first inverter 21, the second inverter 22, and the third inverter 23 on the substrate 101 is equivalent to the area occupied by one transistor laid flat on the substrate 101. Based on this, in the embodiments of this application, the area overhead of the register 10 is equivalent to the area occupied by five transistors laid flat on the substrate 101.

[0071] While ensuring the functionality of register 10, this application embodiment further reduces the area overhead and decreases the area size of register 10, which is beneficial for device miniaturization.

[0072] In some embodiments, both the first transistor 11 and the second transistor 12 are N-type transistors. The materials used in N-type transistors include, but are not limited to, wide-bandgap semiconductor materials such as indium gallium zinc oxide. N-type transistors have lower off-state leakage current, preventing the signal latched at node M under the gate capacitance of the second inverter 22 from being affected by the signal acquired at the signal input terminal IN. Similarly, this also prevents the signal latched at node P under the gate capacitance of the third inverter 23 from being affected by the signal from node N, thereby ensuring normal latching function.

[0073] On the other hand, this application also provides a method for preparing a register.

[0074] Based on downstream processes, the register 10 fabricated by the method provided in this application embodiment includes a signal input terminal IN, a signal output terminal OUT, and a clock control signal terminal CLK. The register 10 also includes a substrate 101. The fabrication method includes:

[0075] A first transistor 11, a second transistor 12, a first inverter 21, a second inverter 22, and a third inverter 23 are formed on a substrate 101. For example, both the first transistor 11 and the second transistor 12 are N-type transistors.

[0076] In the first transistor 11 and the second transistor 12, the gate G of one transistor is electrically connected to the clock control signal terminal CLK through the first inverter 21, and the gate G of the other transistor is directly connected to the clock control signal terminal CLK. In addition, the source S of the first transistor 11 is electrically connected to the signal input terminal IN, the drain D of the first transistor 11 is electrically connected to the source S of the second transistor 12 through the second inverter 22, and the drain D of the second transistor 12 is electrically connected to the signal output terminal OUT through the third inverter 23.

[0077] For example, in some embodiments, the first inverter 21 includes a third transistor 13 and a fourth transistor 14, one of which is an N-type transistor and the other is a P-type transistor. The second inverter 22 includes a fifth transistor 15 and a sixth transistor 16, one of which is an N-type transistor and the other is a P-type transistor. The third inverter 23 includes a seventh transistor 17 and an eighth transistor 18, one of which is an N-type transistor and the other is a P-type transistor.

[0078] For example, in some embodiments, the first transistor 11, the second transistor 12, the third transistor 13, the fourth transistor 14, the fifth transistor 15, the sixth transistor 16, the seventh transistor 17, and the eighth transistor 18 are arranged discretely on the surface of the substrate 101.

[0079] Based on this, such as Figure 7 As shown, Figure 7 This application provides a flowchart of a preparation method. Figures 8-11 for Figure 7 The diagrams illustrate the steps of the fabrication method. The steps shown here are explained using the formation of the related structural films for the third transistor 13 and the fourth transistor 14 as an example.

[0080] like Figure 7 As shown, the preparation method includes the following steps S11 to S13:

[0081] Step S11: As Figure 8 As shown, the gates G of a total of eight transistors, namely the first transistor 11, the second transistor 12, the third transistor 13, the fourth transistor 14, the fifth transistor 15, the sixth transistor 16, the seventh transistor 17 and the eighth transistor 18, are formed on the substrate 101.

[0082] After that, as Figure 9 As shown, a dielectric layer 102 is formed, which covers the gates G of eight transistors to isolate and protect the gates G of each transistor.

[0083] Step S12: As Figure 10 As shown, an active layer ACT is formed, consisting of a first transistor 11, a second transistor 12, a third transistor 13, a fourth transistor 14, a fifth transistor 15, a sixth transistor 16, a seventh transistor 17, and an eighth transistor 18.

[0084] The active layer ACT includes the first part ACT11, the second part ACT12, the third part ACT13, the fourth part ACT14, the fifth part ACT15, the sixth part ACT16, the seventh part ACT17, and the eighth part ACT18, which respectively form eight transistors.

[0085] In each inverter, the two transistors have different conduction types, meaning the corresponding active layer ACT has different conduction types. Taking the third transistor 13 and the fourth transistor 14 of the first inverter 21 as examples, when the third transistor 13 is a P-type transistor and the fourth transistor 14 is an N-type transistor, the third part of the active layer ACT, ACT13, has a P-type conduction type, and the fourth part of the active layer ACT, ACT14, has an N-type conduction type. That is, the material of the third part ACT13 includes at least one of P-type oxide semiconductor, P-doped polycrystalline silicon, P-doped amorphous silicon, or a two-dimensional material exhibiting P-type semiconductor characteristics. The material of the fourth part ACT14 includes at least one of N-type oxide semiconductor, N-doped polycrystalline silicon, N-doped amorphous silicon, or a two-dimensional material exhibiting N-type semiconductor characteristics.

[0086] Step S13: As Figure 11 As shown, the source S and drain D of a total of eight transistors are formed, namely the first transistor 11, the second transistor 12, the third transistor 13, the fourth transistor 14, the fifth transistor 15, the sixth transistor 16, the seventh transistor 17 and the eighth transistor 18.

[0087] The source (S) and drain (D) of the above eight transistors can be formed in the same process, and can be achieved through reasonable patterning. Figure 1 or Figure 2 The circuit connections are shown.

[0088] The register 10 prepared by the above method has a planar structure for each inverter, that is, the two transistors of each inverter are laid flat on the substrate 101. Based on this, the area overhead of the register 10 is equivalent to the area of ​​8 transistors laid flat on the substrate 101.

[0089] Since the fabrication method provided in this application embodiment is based on a downstream process, a stacking scheme can be adopted in the fabrication of the inverter.

[0090] For example, in some embodiments, at least one of the first inverter 21, the second inverter 22 and the third inverter 23 is an inverter with a stacked structure along a direction perpendicular to the substrate 101, the inverter with the stacked structure including a lower transistor T1 and an upper transistor T2.

[0091] For example, such as Figure 6 As shown, when the first inverter 21 has a stacked structure, and the stacked structure is such that the third transistor 13 is located below the fourth transistor 14, the lower transistor T1 is the third transistor 13, and the upper transistor T2 is the fourth transistor 14.

[0092] Based on this, such as Figure 12 As shown, Figure 12Another preparation method flowchart is provided for embodiments of this application. Figures 13-20 for Figure 12 The diagram shows the steps of the preparation method.

[0093] like Figure 12 As shown, the preparation method includes the following steps S21 to S25:

[0094] Step S21: As Figure 13 As shown, the source S and drain D of the lower transistor T1 are formed.

[0095] In the process of forming the source S and drain D of the lower transistor T1, the source S and drain D of the first transistor 11 and the source S and drain D of the second transistor 12 can also be formed under the same process.

[0096] Step S22: As Figure 14 As shown, the first active layer ACT11 forms the lower transistor T1.

[0097] The first active layer ACT11 includes a first portion ACT111 for forming the first transistor 11, a second portion ACT112 for forming the second transistor 12, and a lower transistor T1 for forming the first inverter 21 (i.e., Figure 6 The third part of the third transistor 13 shown is ACT113.

[0098] After that, as Figure 15 As shown, a first dielectric layer 102 is formed. The first dielectric layer 102 is used to provide a flat surface to facilitate subsequent processes, and the first dielectric layer 102 plays a protective and insulating role to prevent leakage.

[0099] To achieve the electrical connection between the two transistors inside the inverter, such as Figure 16 As shown, a via V1 is formed penetrating the first dielectric layer 102, exposing the drain D of the underlying transistor T1, facilitating subsequent electrical connection between the drains D of the two transistors within the inverter. After the drains D of the two transistors are electrically connected, they serve as the output terminal of the inverter, connecting to other devices to form... Figure 1 or Figure 2 The circuit structure shown is shown.

[0100] Step S23: As Figure 17 As shown, a common gate G0 is formed for the lower transistor T1 and the upper transistor T2.

[0101] In the process of forming the common gate G0 of the inverter with a stacked structure, the gate G of the first transistor 11 and the gate G of the second transistor 12 can also be formed in the same process.

[0102] After that, as Figure 18 As shown, a second dielectric layer 103 is formed, which covers the common gate G0 and serves to protect and isolate it.

[0103] Step S24: As Figure 19 As shown, a second active layer ACT21 is formed on the side of the common gate G0 away from the substrate 101.

[0104] For example, the second active layer ACT21 includes a fourth portion ACT214 for forming the fourth transistor 14.

[0105] Step S25: As Figure 20 As shown, the source S and drain D of the upper transistor T2 are formed.

[0106] The above preparation method is only illustrated with the example of the first inverter 21 having a stacked structure. It can be understood that when the second inverter 22 and / or the third inverter 23 also have a stacked structure, their preparation method can be carried out with reference to the above preparation method.

[0107] When the first inverter 21, the second inverter 22, and the third inverter 23 all have a stacked structure, based on the above-described fabrication method, the area overhead of each inverter is equivalent to the area of ​​one transistor on the substrate 101. Based on this, the area overhead of the register 10 is equivalent to the area of ​​five transistors on the substrate 101, further reducing the area overhead of the register 10.

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A register, characterized in that, The register is based on a back-end transistor, the channel layer material of which is a non-monocrystalline silicon material, and the register includes a signal input terminal, a signal output terminal, and a clock control signal terminal. The register further includes a first transistor, a second transistor, a first inverter, a second inverter, and a third inverter; In the first transistor and the second transistor, the gate of one transistor is electrically connected to the clock control signal terminal through the first inverter, and the gate of the other transistor is directly electrically connected to the clock control signal terminal; the source of the first transistor is electrically connected to the signal input terminal, and the drain of the first transistor is electrically connected to the source of the second transistor through the second inverter; the drain of the second transistor is electrically connected to the signal output terminal through the third inverter. The first inverter includes a third transistor and a fourth transistor. The gate of the third transistor is electrically connected to the gate of the fourth transistor, the source of the third transistor is electrically connected to a first voltage terminal, the source of the fourth transistor is electrically connected to a second voltage terminal, and the drain of the third transistor is electrically connected to the drain of the fourth transistor. The second inverter includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is electrically connected to the gate of the sixth transistor, the source of the fifth transistor is electrically connected to a first voltage terminal, the source of the sixth transistor is electrically connected to a second voltage terminal, and the drain of the fifth transistor is electrically connected to the drain of the sixth transistor. The third inverter includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is electrically connected to the gate of the eighth transistor. The source of the seventh transistor is electrically connected to a first voltage terminal. The source of the eighth transistor is electrically connected to a second voltage terminal. The drain of the seventh transistor is electrically connected to the drain of the eighth transistor.

2. The register according to claim 1, characterized in that, The register also includes a substrate, on which the first to eighth transistors are discretely arranged.

3. The register according to claim 1, characterized in that, The register further includes a substrate, on which the first transistor, the second transistor, the first inverter, the second inverter, and the third inverter are disposed; The first inverter, the second inverter, and the third inverter each include two transistors along a direction perpendicular to the substrate, and at least one of the first inverter, the second inverter, and the third inverter is an inverter with a stacked structure; The two transistors in the inverter with the stacked structure are stacked.

4. The register according to claim 3, characterized in that, The first transistor, the second transistor, the first inverter, the second inverter, and the third inverter are arranged separately on the surface of the substrate.

5. The register according to claim 3 or 4, characterized in that, The first inverter, the second inverter, and the third inverter are all inverters with a stacked structure.

6. The register according to claim 1, characterized in that, Both the first transistor and the second transistor are N-type transistors.

7. A method for preparing a register, characterized in that, The register is based on a back-end transistor, the channel layer material of which is a non-monocrystalline silicon material, and the register includes a signal input terminal, a signal output terminal, and a clock control signal terminal. The preparation method includes: A first transistor, a second transistor, a first inverter, a second inverter, and a third inverter are formed on a substrate; In this configuration, the gate of one transistor is electrically connected to the clock control signal terminal via the first inverter, and the gate of the other transistor is directly electrically connected to the clock control signal terminal; the source of the first transistor is electrically connected to the signal input terminal, and the drain of the first transistor is electrically connected to the source of the second transistor via the second inverter; the drain of the second transistor is electrically connected to the signal output terminal via the third inverter. The first inverter includes a third transistor and a fourth transistor. The gate of the third transistor is electrically connected to the gate of the fourth transistor, the source of the third transistor is electrically connected to a first voltage terminal, the source of the fourth transistor is electrically connected to a second voltage terminal, and the drain of the third transistor is electrically connected to the drain of the fourth transistor. The second inverter includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is electrically connected to the gate of the sixth transistor, the source of the fifth transistor is electrically connected to a first voltage terminal, the source of the sixth transistor is electrically connected to a second voltage terminal, and the drain of the fifth transistor is electrically connected to the drain of the sixth transistor. The third inverter includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is electrically connected to the gate of the eighth transistor. The source of the seventh transistor is electrically connected to a first voltage terminal. The source of the eighth transistor is electrically connected to a second voltage terminal. The drain of the seventh transistor is electrically connected to the drain of the eighth transistor.

8. The preparation method according to claim 7, characterized in that, The first inverter includes a third transistor and a fourth transistor, the second inverter includes a fifth transistor and a sixth transistor, and the third inverter includes a seventh transistor and an eighth transistor; Forming a first transistor, a second transistor, a first inverter, a second inverter, and a third inverter on a substrate includes: Forming the gates of the first to the eighth transistors; The active layers of the first transistor to the eighth transistor are formed; The source and drain of the first transistor to the eighth transistor are formed.

9. The preparation method according to claim 7, characterized in that, Along a direction perpendicular to the substrate, at least one of the first inverter, the second inverter, and the third inverter is an inverter with a stacked structure, the inverter with the stacked structure comprising a lower transistor and an upper transistor; Forming the inverter with the stacked structure includes: Forming the source and drain of the lower transistor; The first active layer of the underlying transistor is formed; Forming a common gate for the lower transistor and the upper transistor; A second active layer is formed on the side of the common gate away from the substrate; The source and drain of the upper transistor are formed.

Images