Task processing method and network equipment

Abstract

The invention discloses a task processing method and network equipment. The network equipment not only comprises a main processor, but also comprises other coprocessors. When communication is not established between a main processor and a coprocessor in the network equipment, the main processor can apply for a shared memory in a memory, and a synchronization table can be stored. And the main processor reads the idle thread identifier in the synchronization table, determines the target coprocessor where the hard thread corresponding to the idle thread identifier is located, and enables the target coprocessor to process the calculation task of the main processor, so that all or part of operation of the calculation task of the main processor is unloaded to the target coprocessor for processing, and the calculation task of the main processor is processed. The load of the main processor for running the computing task is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of computing task processing, and in particular to a task processing method and network equipment. Background Art

[0002] An optical switch node (OSN) is a device or node used to implement optical signal switching and routing functions in an optical communication system. OSN is the core component of an optical switching network, used to forward optical signals from one port to another to achieve connection and communication between different communication nodes.

[0003] OSN network equipment generally includes a main control board and multiple interface boards. The main control board includes a central processing unit (CPU). The main control board is connected to multiple interface boards. Each interface board has multiple registers for storing the fault status of different module devices. When the CPU runs an alarm task, it can periodically poll all registers of all interface boards through the peripheral component interconnect express (PCIE) bus to read the data of each register. The CPU detects whether the hardware module connected to the interface board corresponding to each register has an abnormal warning by reading the data of each register. Due to the large number of interface boards and registers, when the CPU periodically reads the data of all registers, it will consume a lot of computing power, which seriously affects other task functions running on the CPU. Summary of the invention

[0004] In order to solve the above problems, an embodiment of the present application provides a task processing method, which can offload the tasks processed by the main processor to the coprocessor for processing, thereby reducing the load of the main processor. In addition, the present application also provides a network device corresponding to the task processing method.

[0005] To this end, the following technical solutions are adopted in the embodiments of the present application:

[0006] In a first aspect, an embodiment of the present application provides a task processing method, which is executed by a network device, wherein the network device includes a main processor, a memory and at least one coprocessor, and the method includes: the main processor applies for a first shared memory in the memory, and the first shared memory is used to store a synchronization table; the synchronization table includes at least one thread identifier, and the thread identifier includes a first state and a second state; the first state indicates that a hard thread of the coprocessor is in an idle state; the second state indicates that a hard thread of the coprocessor is in a busy state; the main processor obtains a first thread identifier from the synchronization table, and determines a target coprocessor based on the first thread identifier; the first thread identifier refers to a thread identifier in the first state, and the target coprocessor is the coprocessor where the hard thread corresponding to the first thread identifier is located, and the at least one coprocessor includes the target processor, and the target processor is used to process the computing task of the main processor.

[0007] In this implementation, when the main processor and the coprocessor in the network device do not establish communication, the main processor can apply for a shared memory in the memory to store the synchronization table. The main processor reads the idle thread identifier in the synchronization table, determines the target coprocessor where the hard thread corresponding to the idle thread identifier is located, and lets the target coprocessor process the computing task of the main processor, so as to offload all or part of the computing task of the main processor to the target coprocessor for processing, so as to reduce the load of the main processor running the computing task.

[0008] In one implementation, the method further includes: the main processor converting the state of the first thread identifier from the first state to the second state.

[0009] In this implementation, after the main processor determines the target coprocessor through the hard thread corresponding to the first thread identifier, the state of the first thread identifier can be switched to a busy state to prevent the main processor from preempting the hard thread corresponding to the first thread identifier when processing other computing tasks.

[0010] In one embodiment, the method further includes: the main processor applying for a second shared memory in the memory, the second shared memory being used to store an operation code table, the operation code table recording the computing tasks of the main processor.

[0011] In this embodiment, since there is no communication connection between the main processor and the coprocessor, the main processor can apply for a shared memory in the storage and write the executed task into the opcode table of the shared memory so that the target processor can access the shared memory and obtain the computing task to be executed.

[0012] In one embodiment, the method also includes: when the target coprocessor detects that the state of the first thread identifier is the second state, using the hard thread corresponding to the first thread identifier to access the opcode table, and obtaining the content recorded in the opcode table from the second shared memory; the target coprocessor executes the computing task of the main processor based on the content recorded in the opcode table.

[0013] In this implementation, when the target coprocessor detects that the state of the first thread identifier is busy, it can call the hard thread corresponding to the first thread identifier to obtain the content recorded in the operation code table to realize the transmission of task messages between the main processor and the target coprocessor.

[0014] In one implementation, the method further includes: the target coprocessor converting the state of the first thread identifier from the second state to the first state.

[0015] In this implementation, after completing this task, the target coprocessor may switch the state of the first thread identifier to an idle state, so that the hard thread corresponding to the first thread identifier can execute other tasks.

[0016] In one embodiment, the method also includes: the target coprocessor applies for a third shared memory in the memory, and the third shared memory is used to store a result table; after the target coprocessor executes the computing task of the main processor, the execution result is written into the result table in the third shared memory; the main processor polls the result table in the third shared memory to obtain the execution result.

[0017] In this implementation, since there is no communication connection between the main processor and the target coprocessor, the target coprocessor can apply for a shared memory in the memory and write the comparison result into the result table of the shared memory. After completing the task dispatch, the main processor will periodically poll the result table of the shared memory to read the comparison result and realize the transmission of result messages between the main processor and the target coprocessor.

[0018] In one embodiment, the computing task of the main processor is an alarm task, and the target coprocessor executes the computing task of the main processor based on the content recorded in the operation code table, specifically including: the target coprocessor obtains the transfer data from the memory, and the transfer data is the data stored in other registers of the main processor moved to the memory; the target coprocessor compares the transfer data of the current cycle with the transfer data of the previous cycle to obtain the execution result.

[0019] In one embodiment, before the main processor applies for the first shared memory in the memory, the method also includes: the main processor sends a notification instruction to a designated interface board, the notification instruction instructing the interface board to move data about a designated hardware module to the memory, and the interface board is used to establish a communication connection between the designated hardware module and the main processor.

[0020] In a second aspect, an embodiment of the present application provides a network device, comprising: a main processor, a memory and at least one coprocessor, the main processor applies for a first shared memory in the memory, the first shared memory is used to store a synchronization table; the synchronization table comprises at least one thread identifier, the thread identifier comprises a first state and a second state; the first state indicates that a hard thread of the coprocessor is in an idle state; the second state indicates that a hard thread of the coprocessor is in a busy state; the main processor obtains a first thread identifier from the synchronization table, and determines a target coprocessor based on the first thread identifier; the first thread identifier refers to a thread identifier in the first state, the target coprocessor is the coprocessor where the hard thread corresponding to the first thread identifier is located, and the at least one coprocessor includes the target processor; the target processor is used to process the computing task of the main processor.

[0021] In one implementation, the main processor is further configured to convert the state of the first thread identifier from the first state to the second state.

[0022] In one implementation, the target coprocessor is further used to apply for a second shared memory in the memory, and the second shared memory is used to store an operation code table, and the operation code table records the computing tasks of the main processor.

[0023] In one embodiment, the target coprocessor is further used to, when detecting that the state of the first thread identifier is the second state, access the opcode table using the hard thread corresponding to the first thread identifier, and obtain the content recorded in the opcode table from the second shared memory; the target coprocessor is further used to execute the computing task of the main processor based on the content recorded in the opcode table.

[0024] In one implementation, the target coprocessor is further configured to convert the state of the first thread identifier from the second state to the first state.

[0025] In one embodiment, the target coprocessor is further used to apply for a third shared memory in the memory, and the third shared memory is used to store a result table; the target coprocessor is further used to write the execution result into the result table in the third shared memory after executing the computing task of the main processor; the main processor is further used to poll the result table in the third shared memory to obtain the execution result.

[0026] In one embodiment, the computing task of the main processor is an alarm task, and the target coprocessor is specifically used to obtain the transfer data from the memory, and the transfer data is the data that the main processor moves from other registers to the memory; the target coprocessor is specifically used to compare the transfer data of the current cycle with the transfer data of the previous cycle to obtain the execution result.

[0027] In one embodiment, the main processor is specifically used to send a notification instruction to a specified interface board, wherein the notification instruction instructs the interface board to move data about a specified hardware module to the memory, and the interface board is used to establish a communication connection between the specified hardware module and the main processor.

[0028] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, comprising computer program instructions. When the computer program instructions are executed by a network device, the computing device executes various possible implementations of the first aspect.

[0029] In a fourth aspect, an embodiment of the present application provides a computer program product comprising instructions, characterized in that the computer program product stores instructions, and when the instructions are executed by a network device, the network device implements each possible implementation embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The following is a brief introduction to the drawings required for describing the embodiments or prior art.

[0031] Figure 1 A schematic diagram of the hardware structure of a network device provided in an embodiment of the present application;

[0032] Figure 2 A schematic diagram of the format of the opcode table designed for the CPU provided in the embodiment of the present application;

[0033] Figure 3 A schematic diagram of the software structure of a network device provided in an embodiment of the present application;

[0034] Figure 4 A flowchart of a task processing method between a CPU and an NP provided in an embodiment of the present application;

[0035] Figure 5 A schematic diagram of a workflow of a CPU and NP processing alarm task provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0037] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0038] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first response message and a second response message are used to distinguish different response messages rather than to describe a specific order of the response messages.

[0039] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0040] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0041] In the related art, in order to reduce the computing power occupied by the CPU running the alarm task, the OSN network equipment mainly reduces the computing power occupied by the CPU running the alarm task by reducing the input / output (I / O) of the CPU. For example, the OSN network equipment can run the optical transport network alarm server (OTNAlmSrv) task to reduce repeated queries by centrally processing alarm queries. For another example, the OSN network equipment can run the interrupt polling (IntPoll) task to reduce alarm queries by pruning the traversed interrupt tree based on the interrupt reporting status and the channel activation status. For another example, the OSN network can modify the CPU polling mode to the interrupt notification mode, dynamically adjust the frequency of alarm inspections, and perform alarm queries in a slow cycle when there is no alarm to reduce alarm queries. And other implementation methods, which are not given one by one here.

[0042] However, when the OSN network device of the related art allows the CPU to access all registers one by one through the PCIE bus, the PCIE bus cannot access all registers at the same time, nor can it perform thread switching like I / O operations. When the CPU initiates PCIE access, it sends a request to the PCIE bus and then waits for the peripheral device to return a response. During this period, the CPU may need to enter a waiting state, blocking and waiting for the peripheral device to return data or complete an operation. This means that the CPU will not be able to execute other instructions, thereby reducing the number of instructions per cycle (IPC) of the CPU. Moreover, the OSN network device of the related art allows the CPU to access PCIE devices one by one, which may cause a waste of PCIE bandwidth and cannot use the PCIE burst mode to effectively utilize the PCIE bandwidth.

[0043] In order to solve the problem that the CPU takes up a lot of computing power when running computing tasks, an embodiment of the present application provides a task processing method and a network device. The network device includes not only a main processor, such as a CPU, but also other coprocessors, such as a network processor (NP). The main processor is mainly responsible for processing general computing tasks in the network device. The coprocessor is mainly responsible for processing and forwarding network data packets in the network device. The main processor applies for a first shared memory in the memory. The first shared memory is used to store a synchronization table. The main processor obtains a first thread identifier from the synchronization table and determines the target coprocessor where the hard thread corresponding to the first thread identifier is located. The target coprocessor can execute the computing task of the main processor.

[0044] In the embodiment of the present application, when there is no communication between the main processor and the coprocessor in the network device, the main processor can apply for a shared memory in the memory to store the synchronization table. The main processor reads the idle thread identifier in the synchronization table, determines the target coprocessor where the hard thread corresponding to the idle thread identifier is located, and lets the target coprocessor process the computing task of the main processor, so as to offload all or part of the computing task of the main processor to the coprocessor for processing, so as to reduce the load of the main processor running the computing task.

[0045] The computing tasks of the main processor may be optical transport network (OTN) alarm tasks, OTN+ alarm tasks, performance data collection tasks, etc. The technical solution protected by the present application is described below by taking the alarm task as an example.

[0046] Figure 1 Schematic diagram of the hardware structure of a network device provided in an embodiment of the present application. Figure 1 As shown, the network device 100 is divided from the hardware perspective, including a main control board 110 and at least one interface board 120. The main control board 110 can be connected to at least one interface board 120, so that the main control board 110 can perform read and write operations on the interface board 120. The main control board 110 includes a main processor 111, at least one coprocessor (the target coprocessor is defined as "coprocessor 112"), a memory 113 and a bus 114. The main processor 111 and the coprocessor 112 can be connected to the memory 113 through the bus 114, so that the main processor 111 and the coprocessor 112 can perform read and write operations on the memory 113. Main processor 111 Coprocessor 112 Main control board 110 Main processor 111 Coprocessor 112 Main control board 110 Among them, the network device 100 can be a data communication network device, an optical network device, and other network devices including at least two processors.

[0047] The main control board 110 is one of the core components of the network device 100, which is responsible for managing and coordinating the various parts of the network device 100 to provide control, scheduling and communication functions. The main control board 110 can be responsible for controlling and managing the various functional modules of the network device 100, such as data processing, memory management, power management, temperature control, etc. The main control board 110 can coordinate the various parts of the network device 100 to ensure that the various parts work together, and schedule and allocate resources according to demand. The main control board 110 can provide a communication interface with other devices or networks, such as an Ethernet interface, a serial port, a universal serial bus (USB) interface, etc. The main control board 110 can exchange data, configure and manage with other devices through the communication interface. The main control board 110 can be responsible for the system management functions of the network device 100, such as firmware upgrades, configuration management, fault detection and diagnosis, etc. The main control board 110 collects the status information of the network device 100, performs self-test and fault recovery, and provides relevant alarm information to the operator or the upper management system.

[0048] The main processor 111 is mainly responsible for processing general computing tasks, such as alarm inspection tasks, performance data collection tasks, etc. The main processor 111 can be a CPU, a graphics processing unit (GPU), a data processing unit (DPU), etc. The technical solution protected by this application will be introduced below using the CPU as an example.

[0049] The coprocessor 112 is mainly responsible for processing and forwarding network data packets, and can be responsible for processing some general computing tasks if it has certain computing processing capabilities. The coprocessor 112 can be a processor such as NP, CPU, GPU, DPU, etc. The technical solution protected by this application will be introduced below using NP as an example.

[0050] The memory 113 can store data written by the main processor 111 and the coprocessor 112, as well as programs run by the main processor 111 and the coprocessor 112. The memory 113 can be a magnetic storage medium, such as a floppy disk, a hard disk, a magnetic tape, etc., an optical storage medium, such as a high-density digital video disc (DVD), etc., or a semiconductor storage medium, such as a solid state disk (SSD), etc.

[0051] The bus 114 can establish a communication connection for each device inside the network device 100, so that data, instructions, etc. can be transmitted between the devices. The bus 114 can be a PCIE bus, etc.

[0052] The multiple interface boards 120 are interface board 120-1, interface board 120-2, ..., interface board 120-N. N is a positive integer greater than or equal to 2. The interface board 120 can provide additional functions or interface expansions to increase the functional flexibility and adaptability of the network device 100. The interface board 120 can provide different types of interfaces, such as optical fiber interfaces, cable interfaces, and wireless interfaces, so that different types of interfaces can be coupled with the main control board 110 to achieve a communication connection between the interface board 120 and the main control board 110.

[0053] Each interface board 120 may have a plurality of registers. Each register may store and control status and configuration information related to the interface board 120. The data stored in the register may be used for initialization, configuration and control of the interface board 120. The main control board 110 may communicate with the interface board 120 by reading and writing the registers of the interface board 120 to implement corresponding functions and operations. The interface board 120 may communicate with the hardware module by reading and writing its own registers to implement the main control board 110 to perform corresponding functions and operations on the hardware module.

[0054] Normally, the tasks processed by the main processor 111 in the network device 100 are independent of the tasks processed by the coprocessor 112, so there is no communication connection between the main processor 111 and the coprocessor 112. When the main processor 111 offloads the specified task to the coprocessor 112, a communication connection needs to be established between the main processor 111 and the coprocessor 112 to enable the main processor 111 to control and manage the coprocessor 112 to perform the specified task, thereby reducing the load of the main processor 111.

[0055] In an embodiment of the present application, the main processor 111 can apply for a memory space in the memory 113 through the bus 114 as the first shared memory that can be accessed by both the main processor 111 and the coprocessor 112. The first shared memory can store a synchronization table. The synchronization table is a state table in which the main processor 111 records each hard thread of each coprocessor. The synchronization table includes at least one thread identifier, and each thread identifier corresponds to a hard thread of a coprocessor. The thread identifier includes a first state and a second state. The first state indicates that a hard thread of a coprocessor is in an idle state. The second state indicates that a hard thread of a coprocessor is in a busy state.

[0056] In one example, the synchronization table can be a bitmap, which is a data structure used to represent and operate binary. The bitmap records multiple bits, and one or more bits represent a hard thread of a coprocessor. For example, a bit represents the state of a hard thread of the coprocessor 112. When the bit is at 0, the hard thread corresponding to the bit is in an idle state. When the bit is at 1, the hard thread corresponding to the bit is in a busy state.

[0057] When the main processor 111 sends a computing task to the coprocessor 112, the main processor 111 can select an idle bit from the synchronization table and determine the coprocessor 112 according to the hard thread corresponding to the idle bit. At the same time, the main processor 111 places the idle bit in the busy bit to avoid the main processor 111 from preempting the hard thread corresponding to the idle bit when processing other computing tasks. The idle bit refers to one or more bits indicating that a hard thread is in an idle state. The busy bit refers to one or more bits indicating that a hard thread is in a busy state.

[0058] In the embodiment of the present application, when the task message is transmitted between the main processor 111 and the coprocessor 112, an operation code (operation code, opcode) table is generally used to implement it. The main processor 111 can apply for a memory space in the memory 113 again through the bus 114, as a second shared memory that both the main processor 111 and the coprocessor 112 can access. The second shared memory can store the opcode table. The main processor 111 can redesign the content of the opcode table according to the task to be performed, so that the opcode table can be extended to the offload task to support various offload tasks.

[0059] like Figure 2As shown, the opcode table may include slave, next, opcode, reserved (rsvd), operation parameter (op para), next and operation parameter 2 (next&op para2) and rsvd 2. Among them, Slave indicates which hard thread processes the opcode. Slave is used to identify that the instruction is sent to the hard thread for execution. Next indicates the next operation or instruction to be executed. Next is used for process control and notifies the system to continue to execute the next step. Opcode represents the operation code of the instruction. Opcode is used to identify and recognize different instructions to indicate the specific operation that the computer should perform. Rsvd indicates that some fields or bits in the opcode are reserved fields and are not used temporarily. The reserved fields can be used for future expansion or other purposes. Op para represents the operation parameter or operand of the instruction. Op para specifies the specific data or content required for the execution of the instruction. The operation parameter can be a register, a memory address, a constant, etc. Next&op para2 combines the next step and the second operation parameter together, indicating that the next operation and the second operation parameter are executed at the same time. Rsvd 2 is the same as mentioned above, indicating that some fields or bits in the opcode are reserved fields.

[0060] In one case, opcode can be set to inv, indicating data abandonment. inv can be applied to logical values ​​or bit operations to convert any non-zero or true value to zero or false value, and vice versa. In this case, op para is rsvd. next&oppara2 is rsvd.

[0061] In another case, opcode can be set to end, indicating the end point of the program or instruction stream. When the "end" instruction is executed, the program will stop executing or the instruction stream will end. At this time, op para is rsvd. next&op para2 is rsvd.

[0062] In another case, opcode can be set to skip, which means skip (or branch in conditional control). The skip instruction can be used to skip a specified code block, or to decide whether to skip the next instruction based on a specific condition. In this case, op para is skip and rsvd. next&op para2 is rsvd.

[0063] In another case, opcode can be set to storefrom, which means storing data from the source location. storefrom is used to read data from the specified storage location or register and store the data to the target location. In this case, oppara is store index, word index, and rsvd. next&op para2 is fromindex, word index, and rsvd.

[0064] In another case, opcode can be set to store, which means storing data in a specified location or register. Store is used to copy data from one location to another, or to store data in memory or registers. In this case, op para is store index, word index, and rsvd. Next&op para2 is next max number, nextindex, and rsvd.

[0065] In another case, opcode can be set to cmp, which means to compare the relationship between two values. cmp is used in conditional statements to determine whether two values ​​are equal, larger, or smaller, and perform corresponding operations based on the comparison results. In this case, oppara is req mask. Next&op para2 is next max number, next index, and rsvd.

[0066] In another case, opcode can be set to or, which indicates a logical or (OR) operation. or is used to perform a logical or operation on two Boolean values ​​or bitwise operations. In this case, op para is or mask. next&op para2 is next max number, next index, and rsvd.

[0067] In another case, opcode can be set to add, indicating an addition operation. Add is used to add two values ​​and get the result. In this case, op para is rsvd. Next & op para2 are next max number, next index, and rsvd.

[0068] The main processor 111 can redesign the field content of the opcode table and store the opcode table in the second shared memory. Normally, the coprocessor 112 will detect the synchronization table of the first shared memory. The coprocessor 112 can obtain the synchronization table content of the first shared memory, and when it detects that the bit corresponding to its own hard thread changes from an idle bit position to a busy bit position, it can call the hard thread corresponding to the bit position to access the second shared memory, read the content recorded in the opcode table, to obtain the computing task, and enable the main processor 111 to offload different types of tasks to the coprocessor 112, so that the coprocessor 112 can support more general computing and comparison tasks, such as add, or, cmp, etc. When the main processor 111 runs a task, it fills in the content according to the agreed table format, so that the task on the coprocessor 112 can perform corresponding operations according to the read table content, and realize the task offloading of the main processor 111.

[0069] In an embodiment of the present application, the coprocessor 112 can apply for a memory space in the memory 113 again through the bus 114, as a third shared memory that can be accessed by both the main processor 111 and the coprocessor 112. The third shared memory can store a result table. After receiving the processing instruction, the coprocessor 112 can scan the data stored in the register of the interface board 120 moved by the main control board 110. After the coprocessor 112 scans the data about the same hardware module in the current cycle, it will compare the data about the same hardware module in the current cycle with the data about the same hardware module in the previous cycle, and write the comparison result into the result table. The main processor 111 can obtain the comparison result from the result table in the third shared memory, and determine whether to trigger an alarm based on the comparison result.

[0070] After the hard thread of the coprocessor 112 completes this task, the bit corresponding to the hard thread in the first shared memory may be moved to an idle bit, so that the hard thread of the coprocessor 112 can continue to execute other tasks.

[0071] Figure 3 Schematic diagram of the software structure of a network device provided in an embodiment of the present application. Figure 3 As shown, the network device 300 is divided from a software perspective, including an application (APP) layer 310, a network processor agent (NP-Agent) 320 and an operating system (OS) 330.

[0072] The APP layer 310 is used to perform specific tasks or provide specific functions on the network device 100. The APP layer 310 is created and developed through programming and can help users complete various tasks. In the embodiment of the present application, the APP layer 310 can have multiple APPs, and each APP can perform specific tasks, such as alarm tasks, performance data collection tasks, etc. The tasks of the APP can be offloaded to the NP through the relevant threads of the NP-Agent 320.

[0073] NP-Agent 320 is used to act as an agent for the NP process and is responsible for implementing the initialization of the NP. The initialization of the NP may include the reserved allocation of the memory used by the NP and other initialization-related operations, such as configuring table memory, configuring direct memory access (DMA) channels, etc. NP-Agent 320 may start a corresponding service thread according to different services. For example, NP-Agent 320 may start an alarm inspection service thread for an alarm inspection service. For another example, NP-Agent 320 may start a performance data collection service thread for a performance data collection service.

[0074] OS 330 can build a network processor agent library (libnp_agent), a network processor common library (libnp_common) and a network processor service library (libnp_service) for NP according to the basic services of NP. Among them, libnp_agent provides basic service interfaces for the processes of NP-Agent 320, such as process creation interface, process destruction interface, etc. libnp_common is used for basic operations on NP resources, application table memory space, query of related table contents, etc. libnp_service is used to provide interfaces for specific offloading services, such as task submission interface, task scheduling algorithm implementation interface, etc.

[0075] In the embodiment of the present application, in order to reduce the load and make full use of heterogeneous computing resources (such as NP, etc.), the CPU can offload some periodic tasks to the NP for processing. After the system service is started, the CPU will initialize the NP resources and the relevant service threads through the NP-Agent 320 process. After the system startup is completed, the system startup process will gradually pull up the task process. When the relevant task process needs to use NP to process the task, it can send the relevant request to NP-Agent 320 through the service interface provided by NP-Agent 320, and let NP-Agent 320 send the relevant task to NP. The microcode hard thread of NP will execute the offloaded task and return the result data after the execution is completed. The CPU periodically scans the synchronization table to detect whether the execution of the task is completed at this time. After the CPU determines that the execution of the task is completed, it reads the result data in the shared memory and processes the result data.

[0076] The process of the CPU processing the alarm task is mainly divided into two steps: the first step is data migration. That is, the CPU moves the data stored in the specified register on the specified interface board 120 to the memory 113 of the main control board 110. The second step is scanning and comparison. That is, the CPU scans the data stored in the specified register on the specified interface board 120 stored in the memory 113, and compares the data moved twice to determine whether the data moved twice are the same. If the data moved twice are not the same, an alarm message will be generated and reported to the network management component, such as the alarm software module.

[0077] When the CPU offloads the alarm task to the NP for execution, it mainly offloads the second step to the NP for execution. The CPU can assign the scheduled scanning task to the hard thread of the NP for execution, and let the hard thread of the NP report each scanning result.

[0078] Figure 4 FIG. 1 is a flow chart of a task processing method between a CPU and an NP provided in an embodiment of the present application. Figure 4 As shown, this method is executed by the CPU and NP together, and the specific implementation process is as follows:

[0079] S401, the CPU sends a notification instruction to the specified interface board 120. The notification instruction instructs the interface board 120 to move the data of the specified register to the memory 113 of the main control board 110. The data may be information such as the fault status, alarm type, and alarm level of the specified hardware module. The hardware module is the component currently connected to the interface board 120.

[0080] Combination Figure 5As shown, the connection between the interface board 120 and the OTN chip is taken as an example. The interface board 120 can couple the OTN chip (such as 8755) with the memory 113 (such as synchronous dynamic random access memory (SDRAM)) to realize the transmission of the data of the OTN chip to the memory 113. When the CPU runs the alarm task, it can periodically send a notification instruction to the specified interface board 120 to instruct the interface board 120 to move the data about the fault status, alarm type, alarm level, etc. of the OTN chip stored in the register to the memory 113 in the main control board 110.

[0081] In one embodiment, the interface board 120 is generally connected to the main control board 110 through a direct memory access (DMA) module, so that the main control board 110 can directly read the data stored in the registers of the interface board 120. At this time, the CPU can send a notification instruction to the DMA module, so that the DMA module can read the data stored in the specified register of the specified interface board 120 according to the notification instruction to obtain data about the OTN chip.

[0082] S402, after the CPU determines that the moving operation of the designated interface board 120 is completed, it sends a computing task to the NP.

[0083] Combination Figure 5 As shown, after the designated interface board 120 completes the operation of moving the data about the OTN chip to the memory 113, it will send a move completion message to the CPU to inform the CPU that the move operation is completed. After the CPU determines that the move operation is completed, it can send a computing task to the NP to let the NP scan the data about the OTN chip stored in the memory 113.

[0084] Normally, there is no communication connection between the CPU and the NP. When the CPU unloads the computing task to the NP, it needs to establish a communication connection with the NP to enable the CPU to control and manage the NP to perform the computing task. In the embodiment of the present application, the CPU can apply for a memory space in the memory 113 through the bus 114 as the first shared memory that can be accessed by both the CPU and the NP. The first shared memory can store a synchronization table. The synchronization table includes multiple bits, and one or more bits represent the state of a hard thread of the NP. When the CPU sends a computing task to the NP, the CPU can select an idle bit from the synchronization table and determine the NP based on the hard thread corresponding to the idle bit. At the same time, the CPU sets the idle bit to the busy bit to avoid the CPU from preempting the hard thread corresponding to the idle bit when processing other computing tasks.

[0085] When task messages are transmitted between the CPU and the NP, an opcode table is generally used to implement the transmission. The CPU can apply for a memory space in the memory 113 again through the bus 114 as a second shared memory that can be accessed by both the CPU and the NP. The second shared memory can store the opcode table. The CPU can redesign the content of the opcode table according to the executed task so that the opcode table can be extended to the offload task to support various offload tasks. The opcode table designed by the CPU includes slave, next, opcode, rsvd, op para, next&op para2 and rsvd 2. Opcode can be set to inv, end, skip, storefrom, store, cmp, or, add, etc., and the implementation of the opcode table can support forwarding various offload tasks to the NP. In the embodiment of the present application, the descriptor of the computing task carried by the opcode table designed by the CPU includes a source address, a destination address, a scanning mode and a bytecode address. The source address represents the address of the CPU. The destination address represents the address of the NP. The scanning mode is a memory scanning mode to obtain information related to the alarm of the OTN chip. The bytecode address can be the location of the driver operation window.

[0086] When the CPU sends a computing task to the NP, the bit corresponding to the hard thread of the NP in the first shared memory is moved to the busy bit. The NP will detect the synchronization table of the first shared memory. The NP can obtain the content of the synchronization table of the first shared memory, and when it detects that the bit corresponding to its own hard thread is moved from the idle bit to the busy bit, it can call the hard thread corresponding to the bit to access the second shared memory and read the content recorded in the opcode table to obtain the computing task.

[0087] S403, the NP scans the data stored in the memory 113 based on the computing task.

[0088] S404, the NP compares the scanning result of the current cycle with the scanning result of the previous cycle, and sends the comparison result to the CPU.

[0089] After receiving the computing task, the NP obtains the opcode table from the second shared memory based on the computing task. After obtaining the opcode table, the NP parses the content of the opcode table and reads the moved data stored in the memory 113 based on the content of the opcode table. In one embodiment, the descriptor of the computing task carried by the opcode table includes a source address, a destination address, a scanning mode and a bytecode address. The NP can determine the location of the data scanned on the memory 113 based on the source address and the destination address. The NP can determine how to scan the data on the memory 113 based on the scanning mode. The NP can use a window mechanism to move the window in the memory from the position corresponding to the bytecode address to scan the data stored in the memory 113.

[0090] After the NP scans the moved data stored in the memory 113, it compares the scan result of the current cycle with the scan result of the previous cycle. In one case, when the NP determines that the scan result of the current cycle is the same as the scan result of the previous cycle, the NP can report the comparison result. After the CPU obtains the comparison result, it determines that the hardware module connected to the specified interface board 120 does not trigger an alarm. In another case, when the NP determines that the scan result of the current cycle is different from the scan result of the previous cycle, the NP can report the comparison result. After the CPU obtains the comparison result, it determines that the hardware module connected to the specified interface board 120 triggers an alarm, and the alarm of the hardware module can be processed.

[0091] In the process of NP reporting the comparison result, a memory space can be applied for again in the memory 113 through the bus 114 as a third shared memory accessible to both the CPU and the NP. The third shared memory can store the result table. After the NP obtains the comparison result, the comparison result can be written into the result table of the third shared memory. After the CPU completes the computing task, it will periodically poll the third shared memory to read the comparison result. After the hard thread of the NP completes this task, the bit corresponding to the hard thread in the first shared memory can be moved to an idle bit, so that the hard thread of the NP can continue to execute other tasks.

[0092] In the embodiment of the present application, the network device 100 can abstract the NP resources as a layer, and provide them as general resources to the tasks of the control plane of the network device 100, so that the tasks can be unaware of the differences in the low-level hardware. Exemplarily, the software stack of NP can be divided into a task layer, a task platform layer, a basic platform layer and a driver layer.

[0093] The task layer, also known as the APP layer 310, is mainly responsible for alarm tasks. Other tasks, such as DCN and Telemetry performance reporting, can be added later.

[0094] The task platform layer, also known as NP-runtime, is integrated into the Guangqi platform and acts as an agent for NP services to complete tasks such as receiving and issuing task requests and reporting results. In the embodiment of the present application, the NP-runtime software module is responsible for accepting and managing the configuration of task issuance, periodically triggering the scanning process, and distributing alarms to specific tasks.

[0095] The basic platform layer may include an operating system (OS) and a forwarding development kit (FDK). RTOS provides management of DMA channel resources and a runtime basic function library. FDK provides management and interaction of NP resources. In the embodiment of the present application, FDK's NP-scan is responsible for issuing processing instructions to the microcode thread of NP, and operating various table items, such as opcode tables, report tables, etc. RTOS's DMA-CONTROL is responsible for providing the user state with an interface for DMA channel use, converting the DMA channel into a file handle for user state use. The NP-SCAN scanning module of the NP's microcode, the microcode thread performs data scanning according to the configuration of the opcode, and can generate alarm data.

[0096] The driver layer includes the chip development kit (CDK) driver of NP and the DMA driver provided by the board support package (BSP). In the embodiment of the present application, the DMA_DRIVER of BSP is responsible for driving the DMA hardware and providing the function of data movement, which needs to be managed by the linux dmaengine framework.

[0097] In the experimental simulation process of this application, the network device 100 is an OSN optical transmission device. The main processor 111 is a CPU and the coprocessor 112 is an NP. The experimental results show that after the CPU unloads the OTN alarm task to the NP, the CPU load occupancy can be reduced by 10%. At the same time, LQ OTN is increased from 4K to 8K.

[0098] The embodiment of the present application also provides a network device, which includes at least one memory and multiple processors, wherein the multiple processors include a main processor and a coprocessor, and the main processor and the coprocessor can execute the following Figure 1-Figure 5 And the above corresponding protected technical solutions, so that the computing device has the technical effect of the above protected technical solutions.

[0099] The present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed in a computer, the computer executes the above Figure 1-Figure 5and a task processing method as described in any one of the corresponding description contents.

[0100] In an embodiment of the present application, a computer program product is also provided, wherein the computer program product stores instructions, and when the instructions are executed by a computer, the computer implements the above Figure 1-Figure 5 and a task processing method as described in any one of the corresponding description contents.

[0101] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

[0102] In addition, various aspects or features of the embodiments of the present application can be implemented as methods, devices or products using standard programming and / or engineering techniques. The term "product" used in this application covers a computer program that can be accessed from any computer-readable device, carrier or medium. For example, a computer-readable medium may include, but is not limited to: a magnetic storage device (e.g., a hard disk, a floppy disk or a tape, etc.), an optical disk (e.g., a compact disc (CD), a DVD, etc.), a smart card and a flash memory device (e.g., an erasable programmable read-only memory (EPROM), a card, a stick or a key drive, etc.). In addition, the various storage media described herein may represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing and / or carrying instructions and / or data.

[0103] In the above embodiments, the main processor 111 and the coprocessor 112 can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., an SSD), etc.

[0104] It should be understood that in various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0105] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0106] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0107] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0108] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or an access network device, etc.) to perform all or part of the steps of the method described in each embodiment of the embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0109] The above is only a specific implementation of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited to this. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the embodiments of the present application, which should be covered within the protection scope of the embodiments of the present application.

Claims

1. A task processing method, characterized in that: The method is performed by a network device, the network device comprising a main processor, a memory and at least one coprocessor, and the method comprises: The main processor applies for a first shared memory in the memory, the first shared memory is used to store a synchronization table; the synchronization table includes at least one thread identifier, the thread identifier includes a first state and a second state; the first state indicates that a hard thread of a coprocessor is in an idle state; the second state indicates that a hard thread of the coprocessor is in a busy state; The main processor obtains a first thread identifier from the synchronization table and determines a target coprocessor based on the first thread identifier; the first thread identifier refers to a thread identifier in the first state, the target coprocessor is a coprocessor where a hard thread corresponding to the first thread identifier is located, the at least one coprocessor includes the target processor, and the target processor is used to process a computing task of the main processor.

2. The method according to claim 1, characterized in that: The method further comprises: The main processor converts the state of the first thread identifier from the first state to the second state.

3. The method according to claim 1 or 2, characterized in that: The method further comprises: The main processor applies for a second shared memory in the memory, and the second shared memory is used to store an operation code table, and the operation code table records the computing tasks of the main processor.

4. The method according to claim 3, characterized in that The method further comprises: When the target coprocessor detects that the state of the first thread identifier is the second state, the target coprocessor uses the hard thread corresponding to the first thread identifier to access the operation code table and obtains the content recorded in the operation code table from the second shared memory; The target coprocessor executes the computing task of the main processor based on the content recorded in the operation code table.

5. The method according to claim 4, characterized in that The method further comprises: The target coprocessor converts the state of the first thread identifier from the second state to the first state.

6. The method according to any one of claims 1 to 5, characterized in that: The method further comprises: The target coprocessor applies for a third shared memory in the memory, and the third shared memory is used to store a result table; After the target coprocessor completes the computing task of the main processor, the target coprocessor writes the execution result into the result table in the third shared memory; The main processor polls the result table in the third shared memory to obtain the execution result.

7. The method according to any one of claims 4 to 6, characterized in that: The computing task of the main processor is an alarm task, The target coprocessor executes the computing task of the main processor based on the content recorded in the operation code table, specifically including: The target coprocessor obtains the transfer data from the memory, where the transfer data is data stored in other registers transferred from the main processor to the memory; The target coprocessor compares the moved data of the current cycle with the moved data of the previous cycle to obtain the execution result.

8. The method according to claim 7, characterized in that Before the main processor applies for the first shared memory in the memory, the method further includes: The main processor sends a notification instruction to the designated interface board, wherein the notification instruction instructs the interface board to move data about the designated hardware module to the memory, and the interface board is used to establish a communication connection between the designated hardware module and the main processor.

9. A network device, characterized in that: include: a main processor, a memory and at least one coprocessor, The main processor applies for a first shared memory in the memory, the first shared memory is used to store a synchronization table; the synchronization table includes at least one thread identifier, the thread identifier includes a first state and a second state; the first state indicates that a hard thread of a coprocessor is in an idle state; The second state indicates that a hard thread of the coprocessor is in a busy state; The main processor obtains a first thread identifier from the synchronization table, and determines a target coprocessor according to the first thread identifier; The first thread identifier is a thread identifier in the first state, the target coprocessor is a coprocessor where the hard thread corresponding to the first thread identifier is located, and the at least one coprocessor includes the target processor; The target processor is used to process the computing tasks of the main processor.

10. The network device according to claim 9, characterized in that: The main processor is further configured to convert the state of the first thread identifier from the first state to the second state.

11. The network device according to claim 9 or 10, characterized in that: The target coprocessor is further used to apply for a second shared memory in the memory, and the second shared memory is used to store an operation code table, and the operation code table records the computing tasks of the main processor.

12. The network device according to claim 11, characterized in that: The target coprocessor is further configured to, when detecting that the state of the first thread identifier is the second state, access the operation code table using the hard thread corresponding to the first thread identifier, and obtain the content recorded in the operation code table from the second shared memory; The target coprocessor is further configured to execute the computing task of the main processor based on the content recorded in the operation code table.

13. The network device according to any one of claims 12, characterized in that: The target coprocessor is further configured to convert the state of the first thread identifier from the second state to the first state.

14. The network device according to any one of claims 9 to 13, characterized in that: The target coprocessor is further used to apply for a third shared memory in the memory, and the third shared memory is used to store a result table; The target coprocessor is further configured to write the execution result into the result table in the third shared memory after executing the computing task of the main processor; The main processor is further used to poll the result table in the third shared memory to obtain the execution result.

15. The network device according to any one of claims 12 to 14, characterized in that: The computing task of the main processor is an alarm task, The target coprocessor is specifically used to obtain the transfer data from the memory, where the transfer data is the data stored in other registers transferred from the main processor to the memory; The target coprocessor is specifically used to compare the moved data of the current cycle with the moved data of the previous cycle to obtain the execution result.

16. The network device according to claim 15, characterized in that: The main processor is specifically used to send a notification instruction to a specified interface board, wherein the notification instruction instructs the interface board to move data about a specified hardware module to the memory, and the interface board is used to establish a communication connection between the specified hardware module and the main processor.

17. A computer-readable storage medium, characterized in that: The method comprises computer program instructions, and when the computer program instructions are executed by a network device, the computing device performs the method according to any one of claims 1 to 8.

18. A computer program product comprising instructions, characterized in that The computer program product stores instructions, and when the instructions are executed by a network device, the network device implements the method according to any one of claims 1 to 8.

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