Protection circuit, test mode protection method and chip
By designing a protection circuit including random number generation circuit and logic circuit in the chip, the fuse data tampering problem caused by laser attack is solved, and effective protection of the test mode and the security of the chip data are achieved.
Patent Information
- Application Number
- CN202411822092.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-04-18
AI Technical Summary
The prior art cannot effectively prevent fuse data tampering caused by laser attacks in chip test mode, which in turn leads to unauthorized access and data leakage.
Design a protection circuit to generate random numbers through a random number generation circuit, combine control logic circuit, counting logic circuit and judgment logic circuit to determine the order of written anti-attack verification data and read fuse data, increase the difficulty of attack and verify data consistency to determine whether to enter test mode.
It effectively protects the test mode from being unlocked by the attacker, ensures the security of chip data, and is simple in design, with almost no additional hardware development costs.
Smart Images
Figure CN119849401A_ABST
Abstract
Description
Technical Field
[0001] One or more embodiments of the present disclosure relate to the technical field of test design of circuit chips, and more particularly to a protection circuit, a test mode protection method and a chip. Background Art
[0002] Before the chip is delivered to the user, it needs to be tested in test mode. Test mode usually has the highest access rights, which makes it a target for attack. Laser attacks are widely used to attack test mode to gain high-privilege access due to their advantages such as precise location, precise timing, and easy control.
[0003] However, in the related art, whether the chip has completed the test and locked the test mode is determined only based on whether the fuse data is marked as a locked value, thereby preventing unauthorized access and modification. When the chip is attacked by laser, the value of the fuse data will be tampered with to an unlocked value, causing the chip to enter the test mode when it should not enter the test mode. In the test mode, the internal data of the chip can be accessed at will, which will lead to leakage. Summary of the invention
[0004] In view of this, the present disclosure provides a protection circuit, a test mode protection method and a chip to protect the test mode from being unlocked by an attacker, thereby protecting chip data security.
[0005] Specifically, the present disclosure is achieved through the following technical solutions:
[0006] In a first aspect, the present disclosure provides a protection circuit, the protection circuit comprising:
[0007] A random number generating circuit, used for generating a number of random numbers;
[0008] A control logic circuit is used to determine the anti-attack verification data to be written according to the random numbers, and to determine the reading sequence of the fuse data and the anti-attack verification data that has been written;
[0009] a counting logic circuit, configured to perform timing processing according to any random number among the plurality of random numbers, and to read the fuse data and the written anti-attack verification data in sequence according to the reading when the timing duration reaches a duration corresponding to the any random number;
[0010] The judgment logic circuit is used to determine whether to enter the test mode according to whether the written anti-attack verification data is consistent with the read written anti-attack verification data and whether the read fuse data is a value indicating a locked state.
[0011] Optionally, the counting logic circuit includes:
[0012] A non-volatile memory, used for storing the written anti-attack verification data and the fuse data;
[0013] A counter logic circuit, configured to perform timing processing according to any random number among the random numbers, and send a signal to the non-volatile memory control logic when the timing duration reaches a duration corresponding to any random number;
[0014] The non-volatile memory control logic is used to control the non-volatile memory to write the determined anti-attack verification data after receiving the signal, and when the timing duration reaches the duration corresponding to any random number, read the written anti-attack verification data and the fuse data in sequence according to the reading.
[0015] Optionally, the control logic circuit includes:
[0016] A first latch logic circuit, used for determining the anti-attack verification data written into the non-volatile memory according to any random number among the plurality of random numbers;
[0017] A sequence control circuit, used for determining representative data representing a reading sequence of the fuse data and the written anti-attack verification data according to any random number among the plurality of random numbers;
[0018] The sequence control circuit is further used to send the representative data to the non-volatile memory control logic, so that the non-volatile memory control logic controls the non-volatile memory according to the reading sequence.
[0019] Optionally, the first value composed of data of a first preset number of bits representing the data is used to indicate that the fuse data is read when the number of reads reaches the first value, otherwise the written anti-attack verification data is read.
[0020] Optionally, the second numerical value composed of the data representing the remaining number of bits of the data is used to indicate the number of times the written anti-attack verification data is read after the fuse data is read.
[0021] Optionally, the protection circuit further includes:
[0022] A second latch logic circuit, used for latching the written anti-attack verification data read from the non-volatile memory;
[0023] The third latch logic circuit is used to latch the fuse data read from the non-volatile memory.
[0024] Optionally, the judgment logic circuit is specifically used for:
[0025] If the written anti-attack verification data is consistent with the latched written anti-attack verification data, and both are not all zero or all one, and the latched fuse data is a value indicating an unlocked state, it is determined to enter the test mode.
[0026] Optionally, the protection circuit further includes:
[0027] The locking circuit is used to mark the fuse data as a value indicating a locking state after the test mode is completed, so as to prohibit entering the test mode.
[0028] In a second aspect, the present disclosure provides a test mode protection method, the method comprising:
[0029] Generate some random numbers;
[0030] Determine the anti-attack verification data to be written according to the random numbers, and determine the order of reading the fuse data and the anti-attack verification data that has been written;
[0031] Performing timing processing according to any random number among the random numbers, and when the timing duration reaches the duration corresponding to the random number, sequentially reading the fuse data and the written anti-attack verification data according to the reading;
[0032] Whether to enter the test mode is determined according to whether the written anti-attack verification data is consistent with the read written anti-attack verification data and whether the read fuse data is a value indicating a locked state.
[0033] Optionally, determining the written anti-attack verification data according to the plurality of random numbers, and determining a reading sequence of the fuse data and the written anti-attack verification data, comprises:
[0034] Determine the anti-attack verification data to be written according to any random number among the random numbers;
[0035] According to any random number among the random numbers, representative data for representing a reading sequence of the fuse data and the written anti-attack verification data is determined.
[0036] Optionally, the first value composed of data of a first preset number of bits representing the data is used to indicate that the fuse data is read when the number of reads reaches the first value, otherwise the written anti-attack verification data is read.
[0037] Optionally, the second numerical value composed of the data representing the remaining number of bits of the data is used to indicate the number of times the written anti-attack verification data is read after the fuse data is read.
[0038] Optionally, the method further includes:
[0039] The written anti-attack verification data, the read written anti-attack verification data and the fuse data are latched respectively through latch logic.
[0040] Optionally, determining whether to enter the test mode according to whether the written anti-attack verification data is consistent with the read written anti-attack verification data, and whether the read fuse data is a value indicating a locked state, includes:
[0041] If the written anti-attack verification data is consistent with the latched written anti-attack verification data, and both are not all zero or all one, and the latched fuse data is a value indicating an unlocked state, it is determined to enter the test mode.
[0042] Optionally, after determining to enter the test mode, the method further includes:
[0043] After the test mode is completed, the fuse data is marked as a value indicating a locked state to prohibit entering the test mode.
[0044] In a third aspect, the present disclosure provides a chip, the chip comprising:
[0045] a circuit under test; and
[0046] The protection circuit as described in the first aspect of the present disclosure is connected to the circuit to be tested.
[0047] According to the embodiments of the present disclosure, a number of random numbers are first generated; then, based on the random numbers, the written anti-attack verification data is determined, and the reading sequence of the fuse data and the written anti-attack verification data is determined; further, timing processing is performed according to any random number among the random numbers, and when the timing duration reaches the duration corresponding to any random number, the fuse data and the written anti-attack verification data are read according to the reading sequence; finally, based on whether the written anti-attack verification data is consistent with the read anti-attack verification data, and whether the read fuse data is a value indicating a locked state, it is determined whether to enter the test mode.
[0048] Through the above methods, the technical solution disclosed in the present invention, on the one hand, increases the difficulty of attack by using randomness, making it difficult for attackers to accurately predict which data read out is valid fuse data, and protects the fuse data used to indicate whether the test mode is locked from being tampered with. Even if an attack successfully modifies the fuse data, the subsequent verification step will detect the abnormality and prevent the test mode from being entered, thereby preventing the attacker from entering the test mode to obtain the internal data of the chip, ensuring the security of the chip after delivery to the user; on the other hand, the protection circuit disclosed in the present invention only needs to add a small amount of simple logic circuits, and almost no additional hardware development costs are added. Such a design not only maintains a low hardware complexity, but is also compatible with existing manufacturing processes, achieving efficient security protection while ensuring chip performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0050] Figure 1 is a schematic diagram of a protection circuit 10 shown in an exemplary embodiment;
[0051] Figure 2 is a schematic diagram of another protection circuit 20 according to an exemplary embodiment;
[0052] Figure 3 is a flow chart of a test mode protection method shown in an exemplary embodiment;
[0053] Figure 4 is a flow chart of another test mode protection method shown in an exemplary embodiment;
[0054] Figure 5 is a flow chart of another test mode protection method shown in an exemplary embodiment;
[0055] Figure 6 is a flow chart of another test mode protection method shown in an exemplary embodiment;
[0056] Figure 7 is a block diagram of a chip shown in an exemplary embodiment;
[0057] Figure 8 is a block diagram of another chip shown in an exemplary embodiment. DETAILED DESCRIPTION
[0058] In order to enable those skilled in the art to better understand the technical solutions in the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present disclosure.
[0059] It should be noted that: in other embodiments, the steps of the corresponding method are not necessarily performed in the order shown and described in this disclosure. In some other embodiments, the steps included in the method may be more or less than those described in this disclosure. In addition, a single step described in this disclosure may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this disclosure may also be combined into a single step for description in other embodiments.
[0060] Before the chip is delivered to the user, it needs to be tested in test mode. Test mode usually has the highest access rights, which makes it a target for attack. Laser attacks are widely used to attack test mode to gain high-privilege access due to their advantages such as precise location, precise timing, and easy control.
[0061] However, in the related art, whether the chip has completed the test and the test mode is locked only based on whether the fuse data is marked as a locked value, thereby preventing unauthorized access and modification. When the chip is attacked by laser, the value of the fuse data will be tampered with to a non-locked value, causing the chip to enter the test mode when it should not enter the test mode. In the test mode, the internal data of the chip can be accessed at will, resulting in leakage. Therefore, the existing test mode entry method cannot effectively deal with laser attacks, and a more effective test mode protection method is urgently needed.
[0062] In view of this, the present disclosure aims to propose a protection circuit, a test mode protection method and a chip to protect the test mode from being unlocked by an attacker, thereby protecting chip data security.
[0063] The technical solution first generates a number of random numbers; then, based on the random numbers, determines the anti-attack verification data to be written, and determines the reading sequence of the fuse data and the anti-attack verification data that has been written; further, performs timing processing based on any random number among the random numbers, and when the timing duration reaches the duration corresponding to any random number, reads the fuse data and the anti-attack verification data that has been written according to the reading sequence; finally, determines whether to enter the test mode based on whether the written anti-attack verification data is consistent with the anti-attack verification data that has been read, and whether the fuse data that has been read is a value indicating a locked state.
[0064] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a protection circuit 10 according to an exemplary embodiment. Figure 1 As shown, the protection circuit 10 may include: a random number generating circuit 11, a counting logic circuit 12, a control logic circuit 13, and a judgment logic circuit 14. The random number generating circuit 11 can generate several groups of random numbers, the length of each group of random numbers is not necessarily equal, and the value of each group of random numbers is not necessarily equal. These generated groups of random numbers can be used for subsequent circuit processing. The control logic circuit 13 can select a group of random numbers 101001010110 from the generated groups of random numbers as the anti-attack verification data to be written, and then select another group of random numbers 0000101000011110 from the generated groups of random numbers as the reading sequence of the fuse data and the written anti-attack verification data. The counting logic circuit 12 can select a group of random numbers from the generated groups of random numbers for timing processing. When the timing duration reaches the corresponding duration of the random number, the fuse data storing important configuration information (such as the chip unique identifier) and the written anti-attack verification data are read according to the determined reading sequence.
[0065] In one embodiment, the counting logic circuit 12 may include a counter logic circuit 21, a non-volatile memory control logic 22, and a non-volatile memory 23. The non-volatile memory 23 may store anti-attack verification data and fuse data, and read out the anti-attack verification data and fuse data when it is necessary to determine whether the circuit can enter the test mode. Among them, the fuse data is used to store important configuration information, such as the unique identifier of the chip, the encryption key, etc., and is an object that is vulnerable to attack. The counter logic circuit 21 can select a group of random numbers from the generated groups of random numbers for timing processing, for example, countdown is performed based on a group of random numbers 1010, and the decimal number corresponding to the binary random number 1010 is 10, so the countdown is 10 seconds. When the countdown is over, an interrupt signal is sent to the non-volatile memory control logic 22, so that the non-volatile memory control logic 22 writes the anti-attack verification data 101001010110 determined by the control logic circuit 13 into the non-volatile memory 23, and finally reads out the fuse data and the anti-attack verification data originally stored in the control logic circuit 13 according to the reading sequence of the two types of data determined by the control logic circuit 13. In another embodiment, the corresponding relationship between the selected random number and the timing duration can also be set. After the timing reaches the timing duration corresponding to the selected random number, the counter logic circuit 21 sends an interrupt signal to the non-volatile memory control logic 22 to enable it to perform subsequent processing.
[0066] In one embodiment, the control logic circuit 13 may include a sequential control circuit 31 and a first latch logic circuit 32. The sequential control circuit 31 may determine the representative data 0000101000011110 for representing the read sequence of the fuse data and the anti-attack verification data written into the non-volatile memory 23 according to any random number 0000101000011110 among several groups of random numbers generated by the random number generating circuit 11, and send the representative data 0000101000011110 to the non-volatile memory control logic 22, so that the non-volatile memory control logic 22 controls the non-volatile memory 23 according to the representative data 0000101000011110.
[0067] In one embodiment, the representative data 0000101000011110 is a 16-bit binary data, and the first numerical value composed of the data 00001010 with a preset number of bits (for example, the first 8 bits) is converted into a decimal number 10, indicating that when reading the fuse data and the anti-attack verification data in the non-volatile memory 23, the fuse data is read only after the 10th reading, and when reading from the 1st to the 9th time, what is read is the anti-attack verification data (which is a string of random numbers, allowing the attacker to obtain useless information).
[0068] In one embodiment, in order to improve the protection effect, the remaining bits representing the data also represent the reading order, and the second numerical value composed of the data 000011110 representing the remaining bits (for example, the last 8 bits) of the data 0000101000011110 is converted into a decimal number 30, indicating that when reading the fuse data and anti-attack verification data in the non-volatile memory 23, after reading the fuse data, it is necessary to read the anti-attack verification data 30 times, thereby increasing the difficulty for attackers to accurately predict the timing of attacking the fuse data.
[0069] The judgment logic circuit 14 can determine whether the chip circuit where the protection circuit is located can enter the test mode based on whether the anti-attack verification data to be written into the non-volatile memory 23 is consistent with the anti-attack verification data read from the non-volatile memory 23 in the reading sequence, and whether the fuse data read from the non-volatile memory 23 is a value representing a locked state (e.g., 0 is a test mode locked state, and 1 is a test mode unlocked state).
[0070] It can be seen from the above embodiments that, since the random number generated by the random number generating circuit 11 is used for timing in the protection circuit 10, the duration of each timing is random, so that the attacker cannot predict the specific attack timing. In addition, the random number generated by the random number generating circuit 11 is used as the anti-attack verification data to be written into the non-volatile memory storing the fuse data, and the anti-attack verification data and the fuse data in the non-volatile memory 23 are read according to the reading sequence determined by the random number, so that the fuse data storing important configuration information and indicating whether the test mode is locked is sandwiched in the anti-attack verification data and read according to the sequence determined randomly, which can increase the difficulty for the attacker to accurately attack the fuse data and protect the fuse data from being tampered with. Even if the attacker attacks the anti-attack verification data, he can only obtain useless random numbers. Once the anti-attack verification data or the fuse data is attacked, the judgment logic circuit 14 will compare whether the values before and after the anti-attack verification data are consistent, and judge whether the fuse data is in a locked state. Once there is an abnormality, the test mode is locked to prohibit the attacker from entering the test mode and accessing the internal data of the chip at will. Therefore, the technical solution disclosed in the present invention can make it difficult for attackers to accurately predict which data read out is valid fuse data, and protect the fuse data used to indicate whether the test mode is locked from being tampered with. Even if an attack successfully modifies the fuse data, the subsequent verification step will detect the abnormality and prevent entry into the test mode, thereby preventing attackers from entering the test mode to obtain the internal data of the chip, ensuring the security of the chip after it is delivered to the user.
[0071] See also Figure 2 , Figure 2 FIG. 2 is a schematic diagram of another protection circuit 20 according to an exemplary embodiment. Figure 1The protection circuit 10 shown is similar, Figure 2 The protection circuit 20 shown also includes: a random number generating circuit 11, a counting logic circuit 12, a control logic circuit 13, and a judgment logic circuit 14, and the functions of each part are similar to those of the Figure 1 The functions of the corresponding parts in the protection circuit 10 shown are also similar. Figure 1 The main difference of the protection circuit 10 shown is that Figure 2 The protection circuit 20 shown may further include a third latch logic circuit 41 and a second latch logic circuit 42 .
[0072] In this embodiment, the second latch logic circuit 42 can latch the anti-attack verification data read from the non-volatile memory 23, and is used to subsequently provide the judgment logic circuit 14 to compare the anti-attack verification data before and after writing into the non-volatile memory 23. The third latch logic circuit 41 can latch the fuse data read from the non-volatile memory 23, and is used to subsequently provide the judgment logic circuit 14 to determine whether the value of the fuse data is a value indicating a locked state.
[0073] Specifically, the judgment logic circuit 14 compares the anti-attack verification data latched in the second latch logic circuit 42 (that is, the anti-attack verification data read from the non-volatile memory, whether the data is attacked in the non-volatile memory is temporarily unknown), and compares it with the anti-attack verification data latched in the first latch logic circuit 32 (that is, the anti-attack verification data determined to be written in the non-volatile memory). If the two are consistent, it means that the anti-attack verification data written in the non-volatile memory has not been attacked or tampered in the non-volatile memory, thus satisfying one of the necessary conditions for entering the test mode. If the two are inconsistent, it means that the anti-attack verification data written in the non-volatile memory has been attacked or tampered in the non-volatile memory. At this time, regardless of whether the fuse data has been attacked or tampered by the attacker, the test mode will not be entered, thereby ensuring safety as much as possible. In fact, since the number of times the anti-attack verification data in the non-volatile memory is read is significantly greater than the number of times the fuse data is read, when an attacker intends to attack and tamper with the fuse data in the non-volatile memory, it is very likely that the anti-attack verification data will be read and tampered with. Therefore, adopting this method can avoid direct attacks on the fuse data to a certain extent.
[0074] The judgment logic circuit 14 also needs to judge whether the fuse data latched in the third latch logic circuit 41 is a value indicating a non-locked state (e.g., 0 is a test mode locked state, 1 is a test mode non-locked state). If the fuse data is 1, and the comparison of the anti-attack verification data is also verified, then it can be determined that the circuit can enter the test mode. In rare cases, the attacker reads and tampers with the fuse data in the non-volatile memory at the precise attack time, but does not tamper with the anti-attack verification data in the non-volatile memory. At this time, if the anti-attack verification data before and after writing to the non-volatile memory is compared to determine whether they are consistent, if it is determined that they have not been tampered with by the attack, it is determined that the test mode can be entered, which still has risks. On this basis, it is safer and more reliable to determine whether to enter the test mode by determining whether the fuse data is a value indicating a non-locked state, and to prevent the attacker from tampering with the fuse data indicating the test mode locked state, and then entering the test mode to obtain the internal data of the chip.
[0075] In one embodiment, the first latch logic circuit 32 latches the determined anti-attack verification data to be written, the second latch logic circuit 42 latches the written anti-attack verification data, and the third latch logic circuit 41 latches the fuse data, so that when entering the test mode, the data from different latch logic circuits are verified at the same time, which can reduce the safety risks caused by single point failure or misoperation. Moreover, by separating the storage, the function of each part is clearer, which is convenient for development, testing and maintenance, and can also avoid the competition conditions or data conflicts that may be caused by multiple read and write operations on the same data at the same time. In addition, the latch logic circuits can work in parallel, which improves the speed and efficiency of data processing, especially under high load conditions.
[0076] In one embodiment, the protection circuit 10 may further include a locking circuit (not shown in the figure). When it is determined that the circuit can enter the test mode and the circuit is tested, the fuse data stored in the non-volatile memory 23 is marked as a value 0 indicating a locked state.
[0077] In one embodiment, the protection circuit 20 may further include a locking circuit (not shown in the figure). When it is determined that the circuit can enter the test mode and the circuit is tested, the fuse data stored in the non-volatile memory 23 and the fuse data stored in the third latch logic circuit 41 are both marked as a value of 0 indicating a locked state; or, only the fuse data stored in the non-volatile memory 23 is marked as a value of 0 indicating a locked state, which simplifies the operation, and the subsequent third latch logic circuit 41 will still obtain and store the fuse data of the latch state value 0. However, this real-time protection is relatively insufficient, because if an error occurs in the third latch logic circuit 41, the fuse data of the latch state value 1 stored in it is not updated, and it may still be able to bypass the locking mechanism and re-enter the test mode.
[0078] Through the above embodiment, the fuse data stored in the non-volatile memory 23 is marked as a value indicating a locked state, which means that the overall circuit of the chip where the protection circuit is located has completed the test, and the subsequent chip may be delivered to users for use, which belongs to the user mode of chip delivery and use. The test mode of the chip before delivery will be locked and no longer enabled, so that the internal data in the chip will no longer be open for access, thereby protecting the security of the chip.
[0079] Please refer to Figure 3 , Figure 3 is a flow chart of a test mode protection method shown in an exemplary embodiment. The test mode protection method can be applied to Figure 1 and / or Figure 2 The protection circuit shown is not limited thereto, and the test mode protection method can also be used for other protection circuits or devices. The test mode protection method may include the following steps:
[0080] Step 302: Generate a number of random numbers.
[0081] Generate one or more groups of random numbers. Each group of random numbers can be different or repeated.
[0082] Step 304: Determine the anti-attack verification data to be written according to the random numbers, and determine the reading sequence of the fuse data and the anti-attack verification data that has been written.
[0083] According to the generated groups of random numbers, one group is selected as the anti-attack verification data to be written, and another group is selected as the reading sequence of the fuse data and the written anti-attack verification data. The two groups of data can be the same or different.
[0084] Step 306: Perform timing processing according to any random number among the random numbers, and when the timing duration reaches the duration corresponding to the random number, read the fuse data and the written anti-attack verification data in sequence according to the reading.
[0085] According to the generated random number groups, a group of random numbers or any random number is selected, and timing processing is performed based on the selected random number, which can be a countdown processing based on the selected random number, or a query of the timing duration corresponding to the selected random number, and the timing is started until the timing duration is reached. After the timing is completed, the fuse data and the written anti-attack verification data are read according to the reading sequence determined in step 304. The fuse data and the written anti-attack verification data can be stored in a non-volatile memory or other storage medium.
[0086] Step 308: Determine whether to enter the test mode according to whether the written anti-attack verification data is consistent with the read written anti-attack verification data and whether the read fuse data is a value indicating a locked state.
[0087] Whether the circuit can enter the test mode is determined based on whether the anti-attack verification data to be written determined in step 304 is consistent with the written anti-attack verification data read in step 306, and whether the value of the fuse data read in step 306 indicates the test mode locked state.
[0088] Figure 3 The test mode protection method shown is illustrated in the form of a module. Figure 3 The division of actions in the modules shown is not limited to the illustrated embodiments. For example, actions in one module can be combined with actions in another module, or split into multiple modules. In some embodiments, there may be other steps before, after, or in between the steps of the test mode protection method.
[0089] Please refer to Figure 4 , Figure 4 FIG. 3 is a flow chart of another test mode protection method shown in an exemplary embodiment. Step 304 may include sub-steps 3041 to 3042:
[0090] Sub-step 3041: Determine the anti-attack verification data to be written according to any random number among the random numbers.
[0091] According to any group of random numbers among the generated several groups of random numbers, or any one random number, the anti-attack verification data to be written is determined. Specifically, the random number itself can be used as the anti-attack verification data to be written, or the random number can be used as the anti-attack verification data to be written after specific calculation processing. This embodiment does not limit this.
[0092] Sub-step 3042: Determine representative data for representing a reading sequence of fuse data and written anti-attack verification data according to any random number among the random numbers.
[0093] According to any one of the generated random numbers, or any one of the random numbers, representative data for representing the reading sequence of the fuse data and the written anti-attack verification data is determined. The representative data represents the sequential logic of reading the fuse data and the written anti-attack verification data, such as which reading specifically reads the fuse data or the written anti-attack verification data.
[0094] In one embodiment, the representative data is an even-numbered binary data, and the numerical value composed of the data of the first preset number of bits (for example, the first half of the number of bits) is converted into a decimal number as a first numerical value, indicating that when reading the fuse data and the anti-attack verification data in the non-volatile memory, the fuse data is read only when the first numerical value is read the number of times, and when the first numerical value is not read the number of times, the anti-attack verification data (which is a string of random numbers, allowing the attacker to obtain useless information) is read.
[0095] In one embodiment, in order to improve the protection effect, the remaining bits representing the data also represent the reading order, and the second numerical value composed of the data representing the remaining bits of the data (for example, the last half of the bits) is converted into a decimal number as a second numerical value, indicating that when reading the fuse data and anti-attack verification data in the non-volatile memory, after reading the fuse data, it is necessary to read the anti-attack verification data of the second numerical value again, thereby increasing the difficulty for an attacker to accurately predict the timing of attacking the fuse data.
[0096] See also Figure 5 , Figure 5 FIG. 1 is a flow chart of another test mode protection method shown in an exemplary embodiment. Figure 5 In the illustrated embodiment, after step 306 and before step 308, step 307 may be further included: latching the written anti-attack verification data, the read written anti-attack verification data and the fuse data respectively through latching logic.
[0097] The anti-attack verification data to be written can be latched by the first latch logic circuit, the anti-attack verification data that has been written can be latched by the second latch logic circuit, and the fuse data can be latched by the third latch logic circuit, so that when entering the test mode, data from different latch logic circuits are verified at the same time.
[0098] See also Figure 6 , Figure 6 FIG. 1 is a flow chart of another test mode protection method shown in an exemplary embodiment. Figure 6 In the illustrated embodiment, step 308 may further include step 310: after the test mode is completed, marking the fuse data as a value indicating a locked state to prohibit entering the test mode.
[0099] When it is determined that the circuit can enter the test mode and the circuit is tested, the fuse data stored in the non-volatile memory is marked as a value indicating a locked state, thereby preventing the circuit from entering the test mode again.
[0100] Figure 5 and 6 The actions of the steps shown are illustrated in the form of modules, and the order of the modules and the division of the actions in the modules are not limited to the illustrated embodiments. For example, the actions in one module can be combined with the actions in another module, or split into multiple modules. In some embodiments, there can be other sub-steps before, after, or in between the module steps.
[0101] The implementation process of each step in the above test mode protection method is specifically described in detail in the implementation process of the functions and effects of the corresponding circuits or units in the above protection circuit, which will not be repeated here.
[0102] Please refer to Figure 7 , Figure 7 is a block diagram of a chip shown in an exemplary embodiment. Figure 8 , Figure 8 The chip 700 and the chip 800 may be digital chips, analog chips or other types of chips, and the present application does not limit the type of chips.
[0103] like Figure 7 As shown, the chip 700 includes a protection circuit 10 and a circuit to be protected 30. The protection circuit 10 is connected to the circuit to be protected 30 to determine whether the circuit to be protected 30 can enter the test mode, thereby protecting the internal data in the chip 700 from being leaked due to an attacker entering the test mode.
[0104] like Figure 8 As shown, the chip 800 includes a protection circuit 20 and a circuit to be protected 30. The protection circuit 20 is connected to the circuit to be protected 30 to determine whether the circuit to be protected 30 can enter the test mode, thereby protecting the internal data in the chip 800 from being leaked due to an attacker entering the test mode.
[0105] In the above embodiments, the protection circuit and the circuit to be protected can be integrated together inside the chip, so that a single package is more economical and efficient than the package of multiple independent components. The integrated design reduces the number of external connection points and reduces the probability of failure due to poor welding or other manufacturing defects.
[0106] The embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the components may be selected according to actual needs to achieve the purpose of the present application.
[0107] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.
Claims
1. A protection circuit, characterized in that: The protection circuit comprises: A random number generating circuit, used for generating a number of random numbers; A control logic circuit is used to determine the anti-attack verification data to be written according to the random numbers, and to determine the reading sequence of the fuse data and the anti-attack verification data that has been written; a counting logic circuit, configured to perform timing processing according to any random number among the plurality of random numbers, and to read the fuse data and the written anti-attack verification data in sequence according to the reading when the timing duration reaches a duration corresponding to the any random number; The judgment logic circuit is used to determine whether to enter the test mode according to whether the written anti-attack verification data is consistent with the read written anti-attack verification data and whether the read fuse data is a value indicating a locked state.
2. The protection circuit according to claim 1, characterized in that: The counting logic circuit comprises: A non-volatile memory, used for storing the written anti-attack verification data and the fuse data; A counter logic circuit, configured to perform timing processing according to any random number among the random numbers, and send a signal to the non-volatile memory control logic when the timing duration reaches a duration corresponding to any random number; The non-volatile memory control logic is used to control the non-volatile memory to write the determined anti-attack verification data after receiving the signal, and when the timing duration reaches the duration corresponding to any random number, read the written anti-attack verification data and the fuse data in sequence according to the reading.
3. The protection circuit according to claim 2, characterized in that: The control logic circuit comprises: A first latch logic circuit, used for determining the anti-attack verification data written into the non-volatile memory according to any random number among the plurality of random numbers; A sequence control circuit, used for determining representative data representing a reading sequence of the fuse data and the written anti-attack verification data according to any random number among the plurality of random numbers; The sequential control circuit is further used to send the representative data to the non-volatile memory control logic, so that the non-volatile memory control logic controls the non-volatile memory according to the representative data.
4. The protection circuit according to claim 3, characterized in that: The first value composed of data representing a pre-set number of bits of data is used to indicate that when the number of reads reaches the first value, the fuse data is read, otherwise the written anti-attack verification data is read.
5. The protection circuit according to claim 4, characterized in that: The second value composed of the data representing the remaining bits of the data is used to indicate the number of times the written anti-attack verification data is read after the fuse data is read.
6. The protection circuit according to claim 2, characterized in that: The protection circuit further comprises: A second latch logic circuit, used for latching the written anti-attack verification data read from the non-volatile memory; The third latch logic circuit is used to latch the fuse data read from the non-volatile memory.
7. The circuit according to claim 6, characterized in that The judgment logic circuit is specifically used for: If the written anti-attack verification data is consistent with the latched written anti-attack verification data, and both are not all zero or all one, and the latched fuse data is a value indicating an unlocked state, it is determined to enter the test mode.
8. The circuit according to claim 1, characterized in that The protection circuit further comprises: The locking circuit is used to mark the fuse data as a value indicating a locking state after the test mode is completed, so as to prohibit entering the test mode.
9. A test mode protection method, characterized in that: The method comprises: Generate some random numbers; Determine the anti-attack verification data to be written according to the random numbers, and determine the order of reading the fuse data and the anti-attack verification data that has been written; Performing timing processing according to any random number among the random numbers, and when the timing duration reaches the duration corresponding to the random number, sequentially reading the fuse data and the written anti-attack verification data according to the reading; Whether to enter the test mode is determined according to whether the written anti-attack verification data is consistent with the read written anti-attack verification data and whether the read fuse data is a value indicating a locked state.
10. The method according to claim 9, characterized in that The step of determining the anti-attack verification data to be written according to the random numbers, and determining the order of reading the fuse data and the anti-attack verification data that has been written, includes: Determine the anti-attack verification data to be written according to any one of the random numbers; According to any random number among the random numbers, representative data for representing a reading sequence of the fuse data and the written anti-attack verification data is determined.
11. The method according to claim 10, characterized in that The first value composed of data representing a pre-set number of bits of data is used to indicate that when the number of reads reaches the first value, the fuse data is read, otherwise the written anti-attack verification data is read.
12. The method according to claim 11, characterized in that The second value composed of the data representing the remaining bits of the data is used to indicate the number of times the written anti-attack verification data is read after the fuse data is read.
13. The method according to claim 9, characterized in that After sequentially reading the fuse data and the written anti-attack verification data according to the reading, the method further includes: The written anti-attack verification data, the read written anti-attack verification data and the fuse data are latched respectively through latch logic.
14. The method according to claim 13, characterized in that The step of determining whether to enter the test mode according to whether the written anti-attack verification data is consistent with the read anti-attack verification data and whether the read fuse data is a value indicating a locked state includes: If the written anti-attack verification data is consistent with the latched written anti-attack verification data, and both are not all zero or all one, and the latched fuse data is a value indicating an unlocked state, it is determined to enter the test mode.
15. The method according to claim 9, characterized in that After determining to enter the test mode, the method further includes: After the test mode is completed, the fuse data is marked as a value indicating a locked state to prohibit entering the test mode.
16. A chip, characterized in that: The chip comprises: a circuit under test; and The protection circuit according to any one of claims 1 to 7, connected to the circuit to be tested.