EFlash control system and method based on instruction pre-reading

Abstract

The invention belongs to the technical field of chips, and discloses an eFlash control system and method based on instruction pre-reading, and the system comprises an instruction pre-reading circuit and an eFlash controller which are connected with each other; the instruction pre-reading circuit is used for receiving transmission information of the CPU and sequentially generating an instruction taking signal and an instruction pre-reading signal based on the transmission information; the instruction taking signal and the instruction pre-reading signal are sequentially sent to an eFlash controller; the eFlash controller is used for judging whether a read address in an instruction taking signal is equal to a pre-read address in the pre-read register or not when the instruction taking signal is received; if yes, outputting an instruction hit signal; and when an instruction pre-reading signal is received, the pre-reading address in the pre-reading register is increased by a preset instruction length. On the premise that the chip area is not increased basically, 0-waiting-period instruction fetching can be achieved, and the instruction fetching efficiency is improved by about 20%.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an eFlash control system and method based on instruction pre-reading. Background Art

[0002] The eFlash data read time is usually between 25 and 35ns. That is, it takes 25 to 35ns from the eFlash interface to initiate a data read instruction to the data being read out, so the eFlash read speed can only reach 40Mhz at the fastest. When the system main frequency exceeds the eFlash data read time, the HREADYOUT signal on the bus end of the eFlash controller must be pulled down to 0 before the data read out of the eFlash is valid. Therefore, the increase in the system main frequency does not increase the system operating efficiency linearly, and there will be a partial loss of energy consumption ratio.

[0003] The existing eFlash instruction pre-reading method uses a CACHE cache design method to predict the data that is cyclically accessed in the eFlash and store it in the SRAM in the CACHE, or uses a larger bit width eFlash design method to pre-read multiple consecutive instructions at a time. Although the two existing pre-reading methods can improve the operating efficiency of the system, the use of CACHE cache or a larger bit width eFlash will lead to an increase in chip area and cost. Summary of the invention

[0004] The present application provides an eFlash control system and method based on instruction pre-reading, which can achieve 0-wait cycle instruction fetching without substantially increasing the chip area, thereby improving instruction fetching efficiency by about 20%.

[0005] In a first aspect, an embodiment of the present application provides an eFlash control system based on instruction pre-reading, including:

[0006] Interconnected instruction pre-reading circuit and eFlash controller;

[0007] The instruction pre-reading circuit is used to receive the transmission information of the CPU, and sequentially generate an instruction fetch signal and an instruction pre-reading signal based on the transmission information; and sequentially send the instruction fetch signal and the instruction pre-reading signal to the eFlash controller;

[0008] The eFlash controller is used to determine whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register when receiving the instruction fetch signal; if so, output an instruction hit signal; when receiving the instruction pre-read signal, increase the pre-read address in the pre-read register by a preset instruction length.

[0009] Furthermore, the transmission information includes a selection signal, a transmission request signal, a transmission type signal, a transmission operation signal and a transmission completion signal.

[0010] Furthermore, the instruction pre-reading circuit includes a first logic module, a state switching module, a first state machine, a second state machine and a second logic module; the first logic module is used to receive the transmission information and generate an instruction fetch signal, and send the instruction fetch signal to the state switching module, the first state machine, the second state machine and the eFlash controller respectively;

[0011] The state switching module is used to flip the state switching signal when detecting the falling edge of the instruction fetch signal, and send the state switching signal to the second state machine, and send it to the first state machine through the NOT gate;

[0012] The first state machine is used to generate a first pre-read signal according to the state switching signal, the instruction fetch signal and the transmission completion signal, and send the first pre-read signal to the second logic module; the second state machine is used to generate a second pre-read signal according to the state switching signal, the instruction fetch signal and the transmission completion signal, and send the second pre-read signal to the second logic module; the second logic module is used to generate an instruction pre-read signal according to the first pre-read signal and the second pre-read signal, and send the instruction pre-read signal to the eFlash controller.

[0013] Furthermore, the first logic module includes a first NOT gate, a second NOT gate and an AND gate; the output end of the AND gate is respectively connected to the input end of the state switching module, the first state machine, the second state machine and the eFlash controller;

[0014] The first NOT gate is used to receive the transmission type signal, flip it and send it to the input end of the AND gate;

[0015] The second NOT gate is used for receiving the transmission operation signal, flipping it and sending it to the input end of the AND gate.

[0016] Furthermore, the second logic module is an OR gate, the input end of the OR gate is respectively connected to the output end of the first state machine and the output end of the second state machine, and the output end of the OR gate is connected to the input end of the eFlash controller.

[0017] Furthermore, the first state machine is specifically configured to generate a first pre-read signal according to the received transmission completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

[0018] Furthermore, the second state machine is specifically configured to generate a second pre-read signal according to the received transmission completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

[0019] Furthermore, the bit width of the eFlash controller is 32 bits.

[0020] Furthermore, the preset instruction length is 4 bits.

[0021] In a second aspect, an embodiment of the present application provides an eFlash control method based on instruction pre-reading, including:

[0022] The instruction pre-reading circuit receives the transmission information of the CPU and generates an instruction fetch signal based on the transmission information;

[0023] The instruction pre-read circuit sends an instruction fetch signal to the eFlash controller;

[0024] The eFlash controller receives an instruction fetch signal and determines whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register; if so, an instruction hit signal is output;

[0025] The instruction pre-reading circuit generates an instruction pre-reading signal based on the transmission information and sends the instruction pre-reading signal to the eFlash controller;

[0026] The eFlash controller receives the instruction pre-read signal and increases the pre-read address in the pre-read register by a preset instruction length.

[0027] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects:

[0028] An eFlash control system based on instruction pre-reading provided by an embodiment of the present application generates an instruction fetch signal and an instruction pre-read signal through an instruction pre-reading circuit, so that after the eFlash controller completes the corresponding read operation according to the instruction fetch signal, it can immediately update the pre-read address in the pre-read register to the next continuous address according to the instruction pre-reading signal and the preset instruction length, so that when the operation is performed according to the instruction fetch signal next time, because the read address and the pre-read address in the instruction fetch signal are equal, the eFlash controller will directly output an instruction hit signal, indicating that the received instruction fetch signal has been pre-read, and there is no need to wait for the completion of the instruction fetch by pulling down the bus terminal HREADYOUT signal of 1 cycle; the instruction pre-reading circuit of the present application can be reused on different process platforms, and the instruction fetch efficiency is improved by about 20% without basically increasing the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A structural diagram of an instruction pre-reading circuit provided for an exemplary embodiment of the present application.

[0030] Figure 2 A timing diagram of generating an instruction fetch signal provided for an exemplary embodiment of the present application.

[0031] Figure 3A state machine operation timing diagram provided for an exemplary embodiment of the present application.

[0032] Figure 4 A schematic diagram of a pre-read hit structure in an eFlash controller provided as an exemplary embodiment of the present application.

[0033] Figure 5 A comparison timing diagram of the pre-read hit process provided for an exemplary embodiment of the present application.

[0034] Figure 6 A flowchart of an eFlash control method based on instruction pre-reading is provided as an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0036] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0037] An embodiment of the present application provides an eFlash control system based on instruction pre-reading, including an instruction pre-reading circuit and an eFlash controller connected to each other; the instruction pre-reading circuit is used to receive transmission information from a CPU, and to sequentially generate an instruction fetch signal and an instruction pre-reading signal based on the transmission information; and the instruction fetch signal and the instruction pre-reading signal are sequentially sent to the eFlash controller.

[0038] The eFlash controller is used to determine whether the read address in the fetch instruction signal is equal to the pre-read address in the pre-read register when receiving the fetch instruction signal; if so, output an instruction hit signal.

[0039] When receiving the instruction pre-read signal, the eFlash controller increases the pre-read address in the pre-read register by a preset instruction length.

[0040] The transmission information includes a selection signal, a transmission request signal, a transmission type signal, a transmission operation signal and a transmission completion signal. When the bit width of the eFlash controller is 32 bits, the preset instruction length is 4 bits.

[0041] Specifically, see Figure 1 The instruction pre-reading circuit includes a first logic module, a state switching module fsm_sel, a first state machine fsm_0, a second state machine fsm_1 and a second logic module.

[0042] The first logic module is used to receive the transmission information and generate an instruction fetch signal, and send the instruction fetch signal to the state switching module, the first state machine, the second state machine and the eFlash controller respectively.

[0043] like Figure 1 As shown, the first logic module includes a first NOT gate, a second NOT gate and an AND gate; the output ends of the AND gate are respectively connected to the input ends of the state switching module, the first state machine, the second state machine and the eFlash controller (the eFlash controller is not marked).

[0044] The first NOT gate is used to receive the transmission type signal, flip it and send it to the input end of the AND gate.

[0045] The second NOT gate is used for receiving the transmission operation signal, flipping it and sending it to the input end of the AND gate.

[0046] like Figure 1 As shown, the HSEL signal is a selection signal, which is used to indicate which Slave is currently selected for transmission. When HSEL=1, it indicates that the current Slave is selected; HTRANS[1] is a transmission request signal, which is used to indicate the current transmission type.

[0047] HPROT[0] is the transfer type signal, which indicates that the current data transfer is instruction / data. When HPROT[0]=0, it indicates that the data transfer is an instruction fetch request. HWRITE is the transfer operation signal, which indicates the current transfer direction, i.e., read / write operation. HREADY is the transfer completion signal, which indicates whether the current transfer is completed. HREADY=1 indicates that the current transfer is completed.

[0048] See also Figure 1 and Figure 2 , the fetch_signal instruction fetch signal is generated by the combinational logic composed of AHB related signals, that is, fetch_signal = HSEL&HTRANS[1]&~HPROT[0]&~HWRITE&HREADY.

[0049] When all the above transmission signals meet the conditions, the fetch_signal instruction fetch signal is 1, indicating that the Master initiates a valid instruction fetch operation to the Slave through the AHB bus.

[0050] The state switching module is used to flip the state switching signal when detecting the falling edge of the instruction fetch signal, and send the state switching signal to the second state machine and then to the first state machine through the NOT gate.

[0051] The first state machine is used to generate a first pre-read signal according to the state switching signal, the instruction fetch signal and the transmission completion signal, and send the first pre-read signal to the second logic module; the second state machine is used to generate a second pre-read signal according to the state switching signal, the instruction fetch signal and the transmission completion signal, and send the second pre-read signal to the second logic module; the second logic module is used to generate an instruction pre-read signal according to the first pre-read signal and the second pre-read signal, and send the instruction pre-read signal to the eFlash controller.

[0052] The second logic module is an OR gate, the input end of the OR gate is respectively connected to the output end of the first state machine and the output end of the second state machine, and the output end of the OR gate is connected to the input end of the eFlash controller.

[0053] Figure 1 The falling edge symbol between the two state machines and the second logic module indicates that the first pre-read signal or the second pre-read signal is valid on the falling edge. fetch_signal is a fetch instruction signal, signal prefetch_signal0 is the first pre-read signal generated by the first state machine fsm_0, and prefetch_signal1 is the second pre-read signal generated by the second state machine fsm_1.

[0054] The present application adopts two parallel cross-working state machines fsm_0 and fsm_1, and generates an instruction pre-read signal by monitoring the information sent by the CPU to the AHB bus. The initial value of the two state machines is 0 after power-on reset. When the instruction fetch signal is monitored, the two state machines start to work alternately, and the monitoring of the HREADY signal indicates that the instruction fetch operation of the current working state machine is completed. Because the instruction fetch operation initiated by the AHB bus is a pipeline structure, the present application adopts two parallel cross-working state machines to avoid the situation where the instruction fetch operation is not processed in time.

[0055] See also Figure 3 , fetch_signal instruction fetch signal is used to control the state switching of state machines fsm_0 and fsm_1.

[0056] The first state machine is specifically configured to generate a first pre-read signal according to the received transmission completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

[0057] The second state machine is specifically configured to generate a second pre-read signal according to the received transmission completion signal and send the signal to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

[0058] In the specific implementation process, the initial value of fsm_sel is 0. Every time an instruction fetch operation is monitored, that is, when the fetch_signal signal falls, the fsm_sel signal is flipped, and the switching state machines fsm_0 and fsm_1 work alternately.

[0059] The present application assumes that the first state machine fsm_0 records the instruction fetch operation first. When fsm_0 = 0, the falling edge of the fetch_signal signal is detected, the state switching signal fsm_sel = 0 and the transmission completion signal HREADY = 1, then fsm_0 is set to 1 (such as Figure 3 As shown by the blue arrow in the figure); when fsm_0=1, HREADY=1 is detected, indicating that the instruction fetching operation of the first state machine fsm_0 is completed, and fsm_0=0 (as shown in the figure); Figure 3 When the instruction fetch operation is detected again, the parallel second state machine fsm_1 records the instruction fetch operation. When fsm_1 = 0, the falling edge of the fetch_signal signal is detected, the state switching signal fsm_sel = 1 and HREADY = 1, and fsm_1 is set to 1 (as shown in FIG. Figure 3 When fsm_1=1, HREADY=1 is detected, indicating that the instruction fetching operation of state machine fsm_1 is completed, and fsm_1=0 (as shown in the blue arrow in the figure). Figure 3 When no instruction fetch signal arrives, the state of the state machine remains unchanged, thus avoiding inefficient continuous pre-reading.

[0060] prefetch_signal0 is the first pre-read signal generated by the first state machine fsm_0, and prefetch_signal1 is the second pre-read signal generated by the second state machine fsm_1. The two state machines work alternately to initiate instruction pre-read signals. The instruction pre-read signal prefetch_signal output by the OR gate will be sent to the eFlash controller. The eFlash controller will initiate an instruction pre-read operation to the eFlash in advance before the Master initiates the next instruction fetch operation to the Slave through the AHB bus, that is, during the idle period of the AHB bus, based on prefetch_signal, thereby improving the efficiency of eFlash instruction fetching.

[0061] See also Figure 4 and Figure 5 HADDR represents the address bus. fetch_signal is the instruction fetch signal initiated by the CPU ( Figure 1 fetch_addr is the read address of the instruction fetch signal, which is generated by the HADDR signal and stored in the fetch_addr register. prefetch_signal is the instruction pre-read signal ( Figure 1 As shown), prefetch_addr is the corresponding pre-read address, which is stored in the prefetch_addr register. Each instruction fetch operation automatically updates prefetch_addr to the next continuous address of the current flash address, that is, prefetch_addr = fetch_addr + 4 (eflash bit width 32bit). When the read address of the initiated instruction fetch signal is the same as the pre-read address, the fetch_hit signal, that is, the instruction hit signal, will be triggered, indicating that the current instruction fetch has been pre-read, and there is no need to wait for the completion of the read instruction by pulling down HREADYOUT for 1cycle. Subsequent continuous instruction fetches trigger fetch_hit without pulling down HREADYOUT, thereby achieving 0 waiting cycle instruction fetching and improving instruction fetching efficiency.

[0062] The above-mentioned embodiment provides an eFlash control system based on instruction pre-reading, which generates an instruction fetch signal and an instruction pre-read signal through an instruction pre-reading circuit, so that after the eFlash controller completes the corresponding read operation according to the instruction fetch signal, it can immediately update the pre-read address in the pre-read register to the next continuous address according to the instruction pre-reading signal and the preset instruction length, so that when the operation is performed according to the instruction fetch signal next time, because the read address and the pre-read address in the instruction fetch signal are equal, the eFlash controller will directly output an instruction hit signal, indicating that the received instruction fetch signal has been pre-read, and there is no need to wait for the completion of the instruction fetch by pulling down the bus terminal HREADYOUT signal of 1 cycle; the instruction pre-reading circuit of the present application can be reused on different process platforms, and the instruction fetch efficiency is improved by about 20% without basically increasing the chip area.

[0063] See also Figure 6 Another embodiment of the present application provides an eFlash control method based on instruction pre-reading, including:

[0064] Step S1 : the instruction pre-reading circuit receives the transmission information of the CPU and generates an instruction fetch signal based on the transmission information.

[0065] Step S2: the instruction pre-reading circuit sends an instruction fetch signal to the eFlash controller.

[0066] Step S3, the eFlash controller receives the instruction fetch signal and determines whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register; if so, an instruction hit signal is output.

[0067] Step S4: the instruction pre-reading circuit generates an instruction pre-reading signal based on the transmission information and sends it to the eFlash controller.

[0068] In step S5, the eFlash controller receives the instruction pre-read signal and increases the pre-read address in the pre-read register by the preset instruction length. The specific definition of the eFlash control method based on instruction pre-reading provided in this embodiment can be found in the embodiment of the eFlash control system based on instruction pre-reading above, which will not be repeated here.

[0069] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An eFlash control system based on instruction pre-reading, characterized in that: include: Interconnected instruction pre-reading circuit and eFlash controller; The instruction pre-reading circuit is used to receive the transmission information of the CPU, and sequentially generate an instruction fetch signal and an instruction pre-reading signal based on the transmission information; and sequentially send the instruction fetch signal and the instruction pre-reading signal to the eFlash controller; The eFlash controller is used to determine whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register when receiving the instruction fetch signal; if so, output an instruction hit signal; and when receiving the instruction pre-read signal, increase the pre-read address in the pre-read register by a preset instruction length.

2. The eFlash control system based on instruction pre-reading according to claim 1, characterized in that: The transmission information includes a selection signal, a transmission request signal, a transmission type signal, a transmission operation signal and a transmission completion signal.

3. The eFlash control system based on instruction pre-reading according to claim 2, characterized in that: The instruction pre-reading circuit includes a first logic module, a state switching module, a first state machine, a second state machine and a second logic module; The first logic module is used to receive the transmission information and generate the instruction fetch signal, and send the instruction fetch signal to the state switching module, the first state machine, the second state machine and the eFlash controller respectively; The state switching module is used to flip the state switching signal when detecting the falling edge of the instruction fetch signal, and send the state switching signal to the second state machine and send it to the first state machine through the NOT gate; The first state machine is used to generate a first pre-read signal according to the state switching signal, the instruction fetch signal and the transmission completion signal, and send the first pre-read signal to the second logic module; The second state machine is used to generate a second pre-read signal according to the state switching signal, the instruction fetch signal and the transmission completion signal, and send the second pre-read signal to the second logic module; The second logic module is used to generate the instruction pre-read signal according to the first pre-read signal and the second pre-read signal, and send the instruction pre-read signal to the eFlash controller.

4. The eFlash control system based on instruction pre-reading according to claim 3, characterized in that: The first logic module includes a first NOT gate, a second NOT gate and an AND gate; the output end of the AND gate is respectively connected to the input end of the state switching module, the first state machine, the second state machine and the eFlash controller; The first NOT gate is used to receive the transmission type signal, flip it and send it to the input end of the AND gate; The second NOT gate is used for receiving the transmission operation signal, flipping it and sending it to the input end of the AND gate.

5. The eFlash control system based on instruction pre-reading according to claim 3, characterized in that: The second logic module is an OR gate, the input end of the OR gate is respectively connected to the output end of the first state machine and the output end of the second state machine, and the output end of the OR gate is connected to the input end of the eFlash controller.

6. The eFlash control system based on instruction pre-reading according to claim 3, characterized in that: The first state machine is specifically configured to generate the first pre-read signal according to the received transmission completion signal and send it to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

7. The eFlash control system based on instruction pre-reading according to claim 3, characterized in that: The second state machine is specifically configured to generate the second pre-read signal according to the received transmission completion signal and send it to the second logic module when the state switching signal is at a high level and a falling edge of the instruction fetch signal is detected.

8. The eFlash control system based on instruction pre-reading according to claim 1, characterized in that: The bit width of the eFlash controller is 32 bits.

9. The eFlash control system based on instruction pre-reading according to claim 8, characterized in that: The preset instruction length is 4 bits.

10. An eFlash control method based on instruction pre-reading, characterized in that: include: The instruction pre-reading circuit receives the transmission information of the CPU and generates an instruction fetch signal based on the transmission information; The instruction pre-reading circuit sends the instruction fetch signal to the eFlash controller; The eFlash controller receives the instruction fetch signal, determines whether the read address in the instruction fetch signal is equal to the pre-read address in the pre-read register; if so, outputs an instruction hit signal; The instruction pre-reading circuit generates an instruction pre-reading signal based on the transmission information and sends the instruction pre-reading signal to the eFlash controller; The eFlash controller receives the instruction pre-read signal and increases the pre-read address in the pre-read register by a preset instruction length.

Images