Method for extracting interface state density of semiconductor device, electronic equipment and storage medium

Abstract

The invention discloses a method for extracting the interface state density of a semiconductor device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a drain current corresponding to a gate voltage according to the gate-drain transfer characteristics of the semiconductor device; obtaining a surface potential at a conducting channel of the semiconductor device according to the drain current; obtaining an interface state charge equivalent voltage according to the gate voltage; and obtaining the interface state density according to the surface potential and the interface state charge equivalent voltage. According to the method provided by the invention, the interface state density of the semiconductor device at the energy level position near the conduction band can be extracted, the characteristics of the semiconductor device can be known more deeply, and the optimization of the characteristics of the semiconductor device is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for extracting interface state density of a semiconductor device, an electronic device and a non-volatile readable storage medium. Background Art

[0002] For semiconductor devices such as SiC MOSFET (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor), the gate oxide interface quality is poor, the gate oxide reliability is not high, and there is a large on-resistance, which to a certain extent restricts the development and application of SiC MOSFET in the field of vehicle electronics. Among them, interface state defects are one of the important factors affecting gate oxide reliability and on-resistance. Therefore, it is very necessary to effectively evaluate the interface state density of semiconductor devices for the development of semiconductor device gate oxide process.

[0003] At present, the methods for extracting the interface state density of semiconductor devices such as SiC MOSFET mainly include CV method, conductivity method, subthreshold current method, etc. These methods are unable to extract the interface state density of the energy level near the conduction band at the current temperature, thus affecting the optimization of semiconductor device performance. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the present invention is to provide a method for extracting the interface state density of a semiconductor device, which can realize the extraction of the interface state density of the semiconductor device at the energy level position near the conduction band, which is more conducive to the optimization of the characteristics of the semiconductor device.

[0005] A second objective of the present invention is to provide an electronic device.

[0006] A third object of the present invention is to provide a non-volatile readable storage medium.

[0007] In order to achieve the above-mentioned purpose, the method for extracting the interface state density of a semiconductor device according to the first aspect of the embodiment of the present invention includes: obtaining a drain current corresponding to a gate voltage according to the gate-drain transfer characteristics of the semiconductor device; obtaining a surface potential at a conductive channel of the semiconductor device according to the drain current; obtaining an interface state charge equivalent voltage according to the gate voltage; and obtaining an interface state density according to the surface potential and the interface state charge equivalent voltage.

[0008] According to the method for extracting the interface state density of a semiconductor device according to an embodiment of the present invention, based on the gate-drain transfer characteristics of the semiconductor device, that is, the gate voltage and the corresponding drain current, the surface potential at the conductive channel of the semiconductor device can be obtained using the drain current. This surface potential directly reflects the potential distribution near the conductive channel. The interface state charge equivalent voltage can be obtained using the gate voltage, which means that the charge distribution at different energy level positions near the conduction band can be obtained by changing the gate voltage, especially the charge information related to the interface state. The interface state density of the semiconductor device at the energy level position near the conduction band can be obtained based on the surface potential and the interface state charge equivalent voltage, which can be more conducive to the optimization of the characteristics of the semiconductor device.

[0009] In some embodiments, the interface state density is obtained according to the surface potential and the equivalent voltage change, including: obtaining the surface potential change, the surface potential change is the change of the surface potential with the change of the drain current; obtaining the interface state charge equivalent voltage change, the interface state charge equivalent voltage change is the change of the interface state charge equivalent voltage with the change of the gate voltage; obtaining the interface state density according to the surface potential change and the interface state charge equivalent voltage change.

[0010] In some embodiments, the interface state density is obtained by the following formula:

[0011]

[0012] Among them, D it is the interface state density, is the surface potential change, C ox is the oxide layer capacitance per unit area, q is the electrostatic charge, ΔV it is the change in the interface state charge equivalent voltage.

[0013] In some embodiments, obtaining the surface potential at the conductive channel of the semiconductor device according to the drain current includes: obtaining the surface potential by solving the following formula and the one-dimensional Poisson equation:

[0014]

[0015] Among them, I ds is the drain current, μ is the electron mobility of the conductive channel, W is the conductive channel width, L is the conductive channel length, Q i,v＝0 is the inversion layer electron density when the electron quasi-Fermi potential is zero, V ds is the drain voltage.

[0016] In some embodiments, obtaining the interface state charge equivalent voltage according to the gate voltage of the gate-drain transfer characteristic includes: obtaining the interface state charge equivalent voltage according to the following formula:

[0017]

[0018] Among them, V it is the interface state charge equivalent voltage, V gs is the gate voltage, V fb is the flat band voltage of the semiconductor device, is the surface potential, ε s is the dielectric constant of the semiconductor device substrate, E is the vertical electric field at the gate oxide interface, C ox is the oxide layer capacitance per unit area.

[0019] In some embodiments, the semiconductor device is configured in the following manner to characterize the gate-drain transfer characteristics of the semiconductor device: the source is grounded; the drain is biased at a preset drain voltage in the mV range; the gate voltage varies within a preset voltage scanning range so that the semiconductor device changes from a depletion state to a strong inversion state; the gate-drain transfer characteristic is a curve of the drain current changing with the gate voltage.

[0020] In some embodiments, the preset drain voltage V ds Satisfy: |V ds |≤200mV.

[0021] In some embodiments, the preset voltage scanning range is 0V-5V, and the voltage step length of the gate voltage does not exceed 200mV.

[0022] In some embodiments, the method further includes: obtaining the Fermi level position and interface state density of the semiconductor device under different gate voltages corresponding to the gate-drain transfer characteristics; obtaining an interface state density energy level distribution curve based on the Fermi level position and the interface state density, wherein the Fermi level position is the horizontal coordinate and the interface state density is the vertical coordinate.

[0023] In some embodiments, the Fermi level position is obtained by the following formula:

[0024]

[0025] Among them, E c -E1 represents the energy level E1 relative to the bottom of the conduction band E c The location of E g is the bandgap width of the semiconductor device substrate, q is the electrostatic charge, is the surface potential, is the bulk Fermi potential of the semiconductor device substrate.

[0026] In some embodiments, the semiconductor device includes a metal oxide semiconductor field effect transistor based on SiC material.

[0027] In order to achieve the above-mentioned purpose, the electronic device of the second aspect embodiment of the present invention includes: at least one processor; a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and when the at least one processor executes the computer program, it implements the method for extracting the interface state density of the semiconductor device described in the above embodiment.

[0028] The electronic device according to the embodiment of the present invention adopts the method for extracting the interface state density of the semiconductor device described in the above embodiment, so as to realize the extraction of the interface state density of the semiconductor device at the energy level position near the conduction band, which is more conducive to the optimization of the characteristics of the semiconductor device.

[0029] In order to achieve the above-mentioned purpose, the non-volatile readable storage medium of the third aspect of the present invention has a computer program stored thereon, and when the computer program is executed, the method for extracting the interface state density of the semiconductor device described in the above embodiment is implemented.

[0030] According to the non-volatile readable storage medium of an embodiment of the present invention, by executing a computer program related to a method for extracting the interface state density of a semiconductor device, the interface state density of the semiconductor device at the energy level position near the conduction band can be extracted, which is more conducive to the optimization of the characteristics of the semiconductor device.

[0031] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0033] Figure 1 is a flow chart of a method for extracting interface state density of a semiconductor device according to an embodiment of the present invention;

[0034] Figure 2 is an overall flow chart of a method for extracting interface state density of a semiconductor device according to an embodiment of the present invention;

[0035] Figure 3 is a device structure diagram of a SiC MOSFET according to an embodiment of the present invention;

[0036] Figure 4 is a graph showing a drain current-gate voltage characteristic curve of a SiC MOSFET according to an embodiment of the present invention;

[0037] Figure 5is a schematic diagram of a curve showing a change in surface potential at a SiC MOSFET conductive channel as a function of gate voltage according to an embodiment of the present invention;

[0038] Figure 6 is the energy level E1 relative to the bottom of the conduction band E according to one embodiment of the present invention. c Schematic diagram of the curve of the position changing with the gate voltage;

[0039] Figure 7 is a schematic diagram of a curve showing a change in the interface state density of a SiC MOSFET with different energy level positions according to an embodiment of the present invention;

[0040] Figure 8 is a block diagram of an electronic device according to an embodiment of the present invention.

[0041] Reference numerals:

[0042] Electronic device 100;

[0043] Memory 101; processor 102. DETAILED DESCRIPTION

[0044] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0045] In the related art, the methods for extracting the interface state density of semiconductor devices such as SiC MOSFET mainly include CV method, conductivity method, subthreshold current method, etc. None of these methods can extract the interface state density of the energy level near the conduction band at the current temperature. Taking the CV method (capacitance-voltage method) as an example, in the methods of extracting interface state density such as the CV method, it is usually necessary to analyze the capacitance-voltage curve. The basic idea of ​​this method can be to change the gate voltage, measure the change in capacitance, and use the relationship between capacitance and voltage to derive the interface state density.

[0046] However, there are some challenges in extracting the interface state density near the conduction band. This is because in the capacitance-voltage curve, especially when the gate voltage is large, the entire capacitance structure changes, causing the series model of the resistance and capacitance of the equivalent circuit to no longer hold. Therefore, the interface state density near the conduction band cannot be accurately extracted. This is because in this case, the charge distribution at the interface may be significantly affected by the electric field, and this effect cannot be fully reflected in the equivalent circuit model.

[0047] Therefore, traditional methods such as the CV method can usually only extract the interface state density far away from the conduction band, while the applicability of these methods is limited for high energy levels near the conduction band.

[0048] In order to solve the above problems, an embodiment of the present invention proposes a method for extracting the interface state density of a semiconductor device. The method can extract the interface state density of the semiconductor device at the energy level position near the conduction band, which is more conducive to optimizing the characteristics of the semiconductor device.

[0049] Reference below Figure 1 A method for extracting interface state density of a semiconductor device according to an embodiment of the present invention is described.

[0050] Figure 1 is a flow chart of a method for extracting interface state density of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the method for extracting the interface state density of a semiconductor device includes at least steps S1-S4, which are specifically as follows.

[0051] S1, obtaining a drain current corresponding to a gate voltage according to a gate-drain transfer characteristic of a semiconductor device.

[0052] In some embodiments, the gate-drain transfer characteristic of a semiconductor device may refer to the relationship between the gate voltage and the drain current, which is usually expressed in the form of a curve graph. Taking SiC MOSFET as an example, its gate-drain transfer characteristic can be obtained through testing or simulation experiments. In a laboratory or production environment, by applying different gate voltages through a test instrument, the state of the conductive channel can be changed to measure the corresponding drain current, thereby establishing a gate-drain transfer characteristic curve. The gate-drain transfer characteristic reflects the current transfer characteristics of the semiconductor device and provides a linear relationship between the gate voltage and the drain current, which is of key significance for understanding the overall performance of the semiconductor device, current switching characteristics, etc.

[0053] In some embodiments, the gate-drain transfer characteristic can capture information related to the interface state density at the energy level position near the conduction band in the change of the drain current. Different interface states have different effects on the gate-drain transfer characteristic, so by analyzing this characteristic, information about the interface state density can be derived.

[0054] In some embodiments, the conduction band may refer to an energy level in a solid where electrons can move freely when their energy is high. In a semiconductor device, the position of the conduction band determines the electrical conductivity of the device.

[0055] S2, obtaining the surface potential at the conductive channel of the semiconductor device according to the drain current.

[0056] In some embodiments, the surface potential at the conductive channel of the semiconductor device can be realized by means of a physical model, a mathematical model or an experimental data processing method, and the surface potential at the conductive channel of the semiconductor device can be derived by measuring or simulating the drain current. The surface potential may refer to the electric potential on the surface of the conductive channel of the semiconductor device. It is directly related to the interface state density, especially near the conduction band, and the surface potential also changes when the gate voltage changes. In addition, when extracting the interface state density of the semiconductor device, the change in surface potential provides key information to help understand the energy level position and possible interface state defect states.

[0057] In some embodiments, interface state defects can be located at the interface of a semiconductor device such as SiC MOSFET, and are caused by incomplete oxidation of SiC. Due to their large number, such defects have a critical limiting effect on the channel mobility of SiC MOSFET. In SiC MOSFET, interface state defects are usually distributed throughout the forbidden band gap, and have the highest density near the conduction band, affecting the performance of the device.

[0058] S3, obtaining the interface state charge equivalent voltage according to the gate voltage.

[0059] In some embodiments, the interface state charge equivalent voltage may refer to the potential formed at the interface by the charge caused by the interface state of the semiconductor device. This potential can be regarded as a potential barrier formed by the interface state, thereby affecting the electron energy level distribution in the semiconductor device. The change of the interface state charge equivalent voltage reflects the change of the interface state density, which is the key information for extracting the interface state density and is of great significance for evaluating device performance and formulating optimization strategies.

[0060] In some embodiments, different gate voltages are applied by a test instrument, and the interface state charge equivalent voltage corresponding to different gate voltages can be calculated by combining the physical structure of the semiconductor device, the electric field model, and the mathematical model. The energy level position near the conduction band has a key influence on the electrical properties of the semiconductor device, and the change in the interface state charge equivalent voltage provides information on the interface state density in this area, which helps to deeply understand and optimize the electrical properties of the device.

[0061] S4, obtain the interface state density based on the surface potential and the interface state charge equivalent voltage.

[0062] In some embodiments, data of surface potential and interface state charge equivalent voltage under different gate voltages can be used to establish a suitable mathematical model or equation to obtain accurate and reliable interface state density information. Interface state density can refer to the number of electron states (or hole states) located in the forbidden band gap of a semiconductor device such as SiC, usually expressed as unit area (square centimeters) and unit energy level (electron volts). This density describes the number of electron states or hole states that exist per unit area and per unit energy level in the forbidden band gap. Interface state density is a key parameter for the performance and stability of semiconductor devices because it affects the transmission and energy level distribution of electrons in the conductive channel.

[0063] Therefore, obtaining the interface state density can provide a more comprehensive understanding of the electrical properties of semiconductor devices, especially the interface state density at the energy level position near the conduction band. This is critical for optimizing semiconductor device performance, improving manufacturing processes, and improving the reliability and stability of semiconductor devices. Information on interface state density helps to understand the interface state defects of semiconductor devices, optimize the charge transfer process, and provide strong support for the further design and manufacturing of semiconductor devices.

[0064] According to the method for extracting the interface state density of a semiconductor device according to an embodiment of the present invention, based on the gate-drain transfer characteristics of the semiconductor device, that is, the gate voltage and the corresponding drain current, the surface potential at the conductive channel of the semiconductor device can be obtained using the drain current. This surface potential directly reflects the potential distribution near the conductive channel. The interface state charge equivalent voltage can be obtained using the gate voltage, which means that the charge distribution at different energy level positions near the conduction band can be obtained by changing the gate voltage, especially the charge information related to the interface state. The interface state density of the semiconductor device at the energy level position near the conduction band can be extracted based on the surface potential and the interface state charge equivalent voltage, which helps to have a deeper understanding of the characteristics of the semiconductor device, thereby improving the performance of the semiconductor device.

[0065] In some embodiments, obtaining the interface state density according to the surface potential and the equivalent voltage change includes: obtaining the surface potential change and obtaining the interface state charge equivalent voltage change. Obtaining the interface state density according to the surface potential change and the interface state charge equivalent voltage change.

[0066] Specifically, the surface potential variation is the variation of the surface potential with the change of the drain current. This variation can be obtained by changing the operating point of the semiconductor device in the experiment or simulation, that is, applying different gate voltages to obtain different drain currents. Then, different drain currents can be brought into the mathematical model or formula to calculate different surface potential values, and the surface potential variation is the difference between different surface potential values. The acquisition of the surface potential variation is intended to capture the correlation between the surface potential and the drain current of the semiconductor device. This correlation is crucial to understanding the electric field distribution and electron transport behavior inside the device.

[0067] In addition, the interface state charge equivalent voltage variation is the variation of the interface state charge equivalent voltage with the gate voltage. This variation can be calculated by applying different gate voltages in experiments or simulations, and combining the surface potential at the conductive channel of the semiconductor device obtained previously, using some mathematical models or formulas to calculate the interface state charge equivalent voltage under different gate voltages, and the interface state charge equivalent voltage variation is the difference between different interface state charge equivalent voltages. The acquisition of the interface state charge equivalent voltage variation is intended to reveal the distribution of interface state charges near the conduction band and understand their influence on electron transport and device performance.

[0068] Furthermore, by analyzing and processing the obtained surface potential change and interface state charge equivalent voltage change, a mathematical model or equation can be established to calculate the interface state density of semiconductor devices at energy level positions near the conduction band. Information on interface state density helps to reveal interface state defects in semiconductor devices, optimize the charge transfer process, and provide guidance for device design and manufacturing.

[0069] In some embodiments, the interface state density can be obtained by the following formula:

[0070]

[0071] Among them, D it is the interface state density. it It represents the interface state density per unit energy level and per unit area, that is, the interface state density at the energy level position near the conduction band. is the surface potential change. It is expressed as the change in surface potential at the conductive channel of a semiconductor device. ox is the oxide layer capacitance per unit area. In semiconductor devices, the oxide layer usually refers to the insulating layer, such as silicon oxide. The oxide layer capacitance describes the ability of the insulating layer to store charge. The oxide layer capacitance per unit area C oxis a constant. This is because in a typical MOSFET structure, the material and thickness of the oxide layer are usually uniform, so its capacitance can be regarded as a known constant under given process and material conditions. q is the electrostatic charge, which is a constant and the basic unit of charge. Its value is approximately 1.602×10 -19 Coulomb. ΔV it is the change in interface state charge equivalent voltage, which indicates the change in interface state charge equivalent voltage as the gate voltage changes.

[0072] Therefore, this formula provides a method to calculate the interface state density using relevant quantities in experimental or simulation data and some fixed constants, which helps to gain a deeper understanding of the performance of semiconductor devices and optimize device design.

[0073] In some embodiments, obtaining a surface potential at a conductive channel of a semiconductor device according to a drain current includes: obtaining the surface potential by solving the following formula and a one-dimensional Poisson equation:

[0074]

[0075] Among them, I ds is the drain current, which can represent the current from the drain to the source in the semiconductor device. It is one of the key parameters to describe the working state and performance of the device. The size and change of the drain current can reflect the characteristics of the device's conductive performance. μ is the electron mobility of the conductive channel, which can represent the rate at which electrons migrate in the conductive channel of the semiconductor. It is a material property and is usually regarded as a known constant in semiconductor device design. W is the conductive channel width, which can represent the lateral dimension of the conductive channel in the semiconductor device. Usually, in device design, the conductive channel width is a parameter determined by the manufacturing process. L is the conductive channel length, which represents the longitudinal dimension of the conductive channel in the semiconductor device. The conductive channel length is also a parameter determined by the manufacturing process in device design. Q i,v＝0 is the inversion layer electron density when the electron quasi-Fermi potential is zero. The electron quasi-Fermi potential can be a concept describing the electron energy level distribution in the equilibrium state, and Q i is the charge density associated with it. ds The drain voltage represents the voltage between the drain and source in a semiconductor device. It is one of the important parameters that affect the working state of a semiconductor device. Changing the drain voltage can adjust the device's operating point and performance.

[0076] Specifically, the above formula describes the drain current I in the semiconductor device ds The inversion layer electron density Q when the electron quasi-Fermi potential is zero i,v＝0By applying different gate voltages in experiments or simulations, the corresponding drain current can be obtained using the curve of the gate-drain transfer characteristic, and then other constant parameters can be substituted into the above formula to obtain the corresponding Q i,v＝0 The value of Q i,v＝0 With surface potential There is a certain mathematical relationship, namely, through Q i,v＝0 The surface potential can be obtained by combining the analytical solution and numerical solution of the one-dimensional Poisson equation. Among them, the one-dimensional Poisson equation is usually used to describe the charge distribution and potential distribution in semiconductor devices. In semiconductor devices, due to the change of gate voltage, the electron density of the conductive channel may change, which in turn affects the surface potential at the conductive channel. Therefore, the surface potential The surface potential at the channel can be obtained by combining the one-dimensional Poisson equation and the above formula with experimental data using numerical calculation methods. By applying different gate voltages V in experiments or simulations gs , we can obtain the corresponding surface potential So we can get the surface potential With the gate voltage V gs The amount of change

[0077] In some embodiments, obtaining the interface state charge equivalent voltage according to the gate voltage of the gate-drain transfer characteristic includes: obtaining the interface state charge equivalent voltage according to the following formula:

[0078]

[0079] Among them, V it is the interface state charge equivalent voltage, which can represent the potential caused by the interface state charge on the gate oxide interface of the semiconductor device and is the interface state charge information to be extracted. gs V is the gate voltage, which can represent the voltage between the gate and the source in a semiconductor device. It is a known quantity applied by external control and directly affects the working state and performance of the device. fb It is the flat band voltage of the semiconductor device, which can be expressed as the external voltage required to prevent the energy band from bending at the semiconductor surface. It is a parameter of the semiconductor device characteristics, usually a known quantity that does not change with the gate voltage and can be determined by experiment or simulation. ε is the surface potential, which can represent the potential on the surface of the conductive channel of a semiconductor device. sis the dielectric constant of the semiconductor device substrate, which can represent the response ability of the semiconductor material under a vertical electric field. It is a physical property of the semiconductor material and is also a known constant. E is the vertical electric field at the gate oxide interface, which can be calculated based on the device structure and the applied voltage. The gate oxide interface can refer to the interface or critical interface between the oxide layer and silicon carbide (SiC). C ox The capacitance of the oxide layer per unit area can represent the responsiveness of the oxide layer to charge. It is usually a known quantity that can be calculated from the thickness and dielectric constant of the oxide layer, or obtained through experiments.

[0080] Specifically, the above formula describes the gate voltage V gs The interface state charge equivalent voltage V it The relationship between the interface state charge equivalent voltage V it Can be adjusted with gate voltage V gs This is because, in the above formula, when a specific gate voltage is applied in an experiment or simulation, the Q i,v＝0 Solving the one-dimensional Poisson equation together gives the corresponding surface potential Moreover, for the vertical electric field E at the gate oxide interface, this variable changes with the gate voltage and can be solved by combining φs and the analytical solution of the one-dimensional Poisson equation. As for other parameters, that is, the flat band voltage V fb 、The dielectric constant ε of the semiconductor device substrate s , Oxide capacitance per unit area C ox Depends on the characteristics of materials and devices, does not change in the experiment, and can therefore be used as a known constant to enter the gate voltage V gs The interface state charge equivalent voltage V it The gate voltage V can be obtained from the relationship between gs The corresponding interface state charge equivalent voltage V it By applying different gate voltages V in experiments or simulations gs , you can get the corresponding V fb +V it , due to V fb does not change with the gate voltage. Therefore, it can be obtained that gs The change in ΔV it .

[0081] In some embodiments, the semiconductor device is configured in the following manner to characterize the gate-drain transfer characteristic of the semiconductor device, including: the source is grounded. The drain is biased at a preset drain voltage in the order of mV. The gate voltage is varied within a preset voltage sweep range so that the semiconductor device changes from a depletion state to a strong inversion state. The gate-drain transfer characteristic is a curve of the drain current changing with the gate voltage.

[0082] The purpose of grounding the source is to ensure that the source maintains a fixed potential when measuring the gate-drain transfer characteristic to provide a relatively stable reference point so that the potential at the source is zero. The drain is biased at a preset drain voltage in the mV range to ensure that the semiconductor device is in the normal operating area during the measurement. This helps to obtain an accurate gate-drain transfer characteristic curve, from the depletion state to the strong inversion state.

[0083] Specifically, in semiconductor devices, the depletion state can indicate that there are almost no free electrons in the conductive channel of the device, and the electrons are mainly concentrated at a position far away from the conduction band. The strong inversion state can indicate that the Fermi level position near the conductive channel is closer to the conduction band and the electron density is larger. By changing the gate voltage within a preset voltage scanning range, the semiconductor device can gradually change from the depletion state to the strong inversion state to achieve state switching. This switching process is to observe the charge distribution and gate-drain transfer characteristics of semiconductor devices under different working conditions.

[0084] Furthermore, during the process of gate voltage change, the drain current under different gate voltages can be recorded, so that a curve of the relationship between drain current and gate voltage can be established. This curve provides detailed information about the current transfer characteristics of semiconductor devices and is a key indicator for evaluating the performance of semiconductor devices.

[0085] In some embodiments, the preset drain voltage V ds Satisfy: |V ds |≤200mV, so that the drain electrode of the semiconductor device is in a low voltage state. This is to obtain the surface potential at the conductive channel of the semiconductor device according to the drain current, and the drain current I ds Some assumptions are used in the derivation and simplification process to simplify the calculation and make the formula valid. Specifically, when V ds If V is small enough, the conduction region of the semiconductor device can be considered linear, making the relationship between drain current and gate voltage much simpler. ds The relationship between the conduction area and the drain current is no longer linear, that is, the relationship between the surface potential at the conductive channel of the semiconductor device according to the drain current does not hold. Therefore, such simplification is to make the derivation of the formula more convenient, and the low voltage condition makes the formula valid under this linear approximation.

[0086] In some embodiments, the preset voltage scanning range is 0V-5V. The range of 0V to 5V covers the normal working range of general semiconductor devices. This range allows covering different working regions from depletion state to strong inversion state, which helps to fully understand the performance of the device. In semiconductor devices, the gate voltage V gsThe change of V gs When it is lower, the semiconductor device is in a depletion state, the channel is basically closed, and the current is very small. gs Gradually increases, the electric field strength increases, the channel begins to form, the current increases, the semiconductor device gradually enters a strong inversion state, and finally reaches the on state.

[0087] Therefore, by changing the gate voltage in the scanning range of 0V-5V, different working states of the semiconductor device, including conduction and cutoff, can be observed in a larger voltage range. In general, this voltage range is sufficient to cover the state near the conduction band, so that the experiment does not need to specially adjust the voltage range.

[0088] In some embodiments, the voltage step size of the gate voltage does not exceed 200mV. This means that during the scanning process, the gate voltage is increased by no more than 200mV each time. This helps to carefully observe and record the effect of the gate voltage on the drain current, and provide a more detailed gate-drain transfer characteristic curve. Therefore, by limiting the step size, the slight effect of gate voltage changes on the performance of semiconductor devices can be more accurately captured, thereby more comprehensively understanding the gate-drain transfer characteristics. Such control and selection can improve the accuracy and reliability of the experiment.

[0089] In some embodiments, the method for extracting the interface state density of a semiconductor device further includes: obtaining the Fermi level position and the interface state density under different gate voltages corresponding to the gate-drain transfer characteristics of the semiconductor device. The Fermi level position may refer to the position of the Fermi level in the electronic energy band relative to the reference energy level in the semiconductor device. The Fermi level position plays a key role in the distribution and conductivity of electrons. In semiconductors, the Fermi level is generally considered to be a higher energy position in the electronic energy band, which divides the electronic energy band into a valence band and a conduction band. In thermal equilibrium, the Fermi level position gives the average energy of electrons in the semiconductor, while in a non-equilibrium state, the Fermi level position may change with the action of an external electric field.

[0090] In some embodiments, the interface state density may refer to the density of electron or hole states at energy levels present near the conduction band or valence band in a semiconductor device. These interface states are caused by interface defects and have a significant impact on the electrical properties of semiconductor devices. The distribution and variation of the interface state density are crucial to understanding the performance and stability of the device. By measuring the Fermi level position and the corresponding interface state density under different gate voltages, a relationship diagram between the Fermi level position and the interface state density, i.e., the interface state density energy level distribution curve, can be drawn. Among them, the Fermi level position is the horizontal coordinate and the interface state density is the vertical coordinate. This curve shows the changing trend of the interface state density present in semiconductor devices under different gate voltages, which helps to more comprehensively understand the energy band structure and interface state density distribution of semiconductor devices under different electric field conditions. By observing and analyzing this curve, the device performance can be more deeply understood, providing strong support for optimizing the design and manufacture of semiconductor devices.

[0091] In some embodiments, the Fermi level position can be obtained by the following formula:

[0092]

[0093] Among them, E c -E1 represents the energy level E1 relative to the bottom of the conduction band E c Location. g is the bandgap width of the semiconductor device substrate. The bandgap width can be the energy difference between the conduction band and the valence band, which is an important feature of semiconductor materials. q is the electrostatic charge, is the surface potential, is the bulk Fermi potential of the semiconductor device substrate. Bulk Fermi potential can refer to the potential difference between the Fermi level in the semiconductor far away from the surface and the center of the band gap.

[0094] Specifically, the surface potential can be measured or calculated at different gate voltages. Bandgap width E g , body Fermi potential By substituting these values ​​into the formula, we can calculate the data of the Fermi level relative to the bottom of the conduction band as the gate voltage changes. By obtaining the Fermi level position under different electric field conditions, we can reveal the distribution of electron energy levels in semiconductor devices and help us to deeply understand the working principle of the device.

[0095] In some embodiments, E1 in the above formula may be a general energy level. In semiconductor devices, energy levels are usually used to indicate the energy state of electrons. Here, E1 may refer to the energy level of a point at a distance from the conduction band. It is not a specific value, but is used to indicate a range of possible energy levels. c It can be the energy level at the bottom of the conduction band, also called the conduction band edge.c can be a reference point, usually defined as zero energy. Therefore, E c -E1 can refer to the energy difference between a specific energy level E1 and the bottom of the conduction band. Near the conduction band, the interface state density D it With E c -E1 changes because the interface state density may be different at different energy level positions.

[0096] Figure 2 is a general flow chart of a method for extracting interface state density of a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the overall process of the method for extracting the interface state density of a semiconductor device includes at least steps S10-S15, which are specifically as follows.

[0097] S10, source grounded, preset drain voltage V ds is a small voltage, satisfying |V ds |≤200mV.

[0098] S11, preset gate voltage V gs The scan range is 0V-5V, the step size does not exceed 200mV, and the drain current I is monitored. ds .

[0099] S12, using the formula: Calculate the surface potential in the conductive channel of a semiconductor device

[0100] S13, using the formula: Calculate the interface state charge equivalent voltage V it With the gate voltage V gs The change in ΔV it .

[0101] S14, using the formula: Calculate the interface state energy level E1 relative to the conduction band bottom E at different gate voltages c Location E c -E1.

[0102] S15, using the formula: The interface state density is calculated and the energy level distribution of the interface state density is obtained.

[0103] In some embodiments, the semiconductor device includes a metal oxide semiconductor field effect transistor (MOSFET) based on SiC material. SiC material is often used in high temperature, high frequency and high power applications and is an important semiconductor material. MOSFET is a field effect transistor that controls the formation of a conductive channel by applying a voltage on an oxide layer. This makes MOSFET widely used as a switch or amplifier in electronic devices. MOSFET using SiC as a semiconductor material is usually called SiC MOSFET. It has the advantages of both SiC materials and MOSFET devices.

[0104] Figure 3 is a device structure diagram of a SiC MOSFET according to an embodiment of the present invention, such as Figure 3 As shown, Figure 3 The structure described is a typical N-channel MOSFET structure. Figure 3 The S in the figure represents the source of the MOSFET, which is usually the current input terminal of the device. G represents the gate of the MOSFET. The gate can be used to control the current transmission between the source and the drain. When an appropriate voltage is applied to the gate, it can control whether the channel between the source and the drain is conductive. D represents the drain of the MOSFET, which is usually the current output terminal of the device.

[0105] In some embodiments, Figure 3 As shown, N+ represents a highly doped n-type semiconductor material. The role of N+ in MOSFET can be to increase the conductivity of the source, drain and gate regions to enable MOSFET to perform current control and switching operations more efficiently. In N-channel MOSFET, Pwell (P-type well) is the region where the channel is formed. When an appropriate voltage is applied to the gate (G), the electric field formed controls the charge in Pwell, thereby forming a conductive channel connecting the source (S) and the drain (D). This electric field controls the formation and closing of the channel by changing the potential between the gate and the substrate (usually Pwell).

[0106] In some embodiments, the basic principle of MOSFET is to control the movement of electrons or holes in the channel by changing the gate voltage, thereby adjusting the current from the source to the drain. When the gate voltage increases, the electric field strength increases, the channel conductivity increases, the current flows from the source to the drain, and the MOSFET is in the on state. On the contrary, when the gate voltage decreases, the electric field weakens, the channel conductivity decreases, the current decreases, and the MOSFET is in the off state.

[0107] In some embodiments, an N-channel SiC MOSFET lateral device is used as an experimental sample. The gate length of the SiC MOSFET is 50um, the gate width is 200um, and the gate oxide layer thickness is 50nm. The experimental conditions are set, that is, the source is grounded, the drain voltage is biased at 50mV, the gate voltage scan range is 0V to 5V, the step size is 200mV, and the drain current is monitored. When the gate voltage changes within the preset voltage scan range so that the semiconductor device changes from the depletion state to the strong inversion state, a curve of the drain current changing with the gate voltage can be obtained, see Figure 4 shown. Figure 4 The drain current-gate voltage characteristic curve of SiC MOSFET measured in the experiment, namely the gate-drain transfer characteristic, is shown. This curve reflects the change of drain current under different gate voltages and provides basic data for subsequent interface state density extraction.

[0108] Furthermore, according to the formula Solving the one-dimensional Poisson equation gives the surface potential Therefore, by applying different gate voltages within the preset voltage scanning range, different drain currents can be obtained, and then a curve diagram of the surface potential change at the conductive channel of the SiC MOSFET under different gate voltages can be obtained, see Figure 5 shown. Figure 5 The surface potential of the SiC MOSFET conductive channel calculated from the experiment is shown in Figure 2. With the gate voltage V gs This curve helps to observe the changing trend of surface potential under different gate voltages. The change of surface potential directly affects the movement of electrons in the conductive channel, so accurate measurement and analysis of it is very important to understand and improve the performance of MOSFET. It also provides data support for the subsequent extraction of interface state density of semiconductor devices.

[0109] Furthermore, according to the formula The interface state charge equivalent voltage V can be calculated it Therefore, by applying different gate voltages within the preset voltage scanning range, the surface potential of the SiC MOSFET conductive channel under different gate voltages can be obtained. Thus, the interface state charge equivalent voltage change ΔV of SiC MOSFET under different gate voltages can be obtained. it .

[0110] Furthermore, according to the formula It can be calculated that the energy level E1 relative to the bottom of the conduction band E under different gate voltages c The location of Figure 6 As shown, Figure 6 The energy level E1 is shown relative to the bottom of the conduction band Ec The curve of the position of the energy level with different gate voltages reveals the distribution of energy levels near the conduction band. The ordinate represents the position of the energy level relative to the bottom of the conduction band. c -E1, the horizontal axis represents the gate voltage V gs The change of this curve reflects the difference in the relative position of the electron energy level in the conduction band under different gate voltages. This is of great significance for understanding the distribution of electrons in semiconductor devices, especially for extracting the interface state density at the energy level position near the conduction band.

[0111] Furthermore, according to the formula The interface state density distribution of SiC MOSFET at room temperature can be calculated. By applying different gate voltages within the preset voltage scanning range, the surface potential change at the conductive channel of SiC MOSFET under different gate voltages can be obtained. And the interface state charge equivalent voltage change ΔV of SiC MOSFET under different gate voltages it , so that the interface state density of SiC MOSFET under different gate voltages can be obtained. Figure 6 The energy level E1 is shown relative to the bottom of the conduction band E c The position of the gate voltage changes with different gate voltages. In this way, the change of the gate voltage can be converted into an energy level difference (E c -E1) to better understand the relationship between the interface state density Dit and the energy level position (E c -E1) relationship curve. Figure 7 As shown, Figure 7 The changing trend of SiC MOSFET interface state density with different energy level positions is shown.

[0112] Therefore, we can analyze Figure 7 To understand the energy level distribution of interface state density in SiC MOSFET under different gate voltage conditions. Such information is important for gaining in-depth understanding of device performance, identifying potential problems and optimizing them.

[0113] Reference below Figure 8 An electronic device according to an embodiment of the present invention is described.

[0114] Figure 8 is a block diagram of an electronic device according to an embodiment of the present invention, such as Figure 8 As shown, the electronic device 100 includes: at least one processor 102 and a memory 101 .

[0115] In some embodiments, the electronic device 100 may be various types of devices, such as a computer, a smart phone, an embedded system, etc.

[0116] In some embodiments, the memory 101 is in communication with at least one processor 102, and the memory 101 stores a computer program that can be executed by at least one processor 102. The memory 101 can be a solid-state memory (such as a flash memory) or a random access memory (RAM), which is used to store programs and intermediate calculation results. When the at least one processor 102 executes the computer program, the method for extracting the interface state density of the semiconductor device described in the above embodiment is implemented.

[0117] According to the electronic device 100 of the embodiment of the present invention, the method for extracting the interface state density of the semiconductor device described in the above embodiment is adopted to realize the extraction of the interface state density of the semiconductor device at the energy level position near the conduction band, which helps to have a deeper understanding of the characteristics of the semiconductor device, thereby improving the performance of the semiconductor device.

[0118] The embodiment of the present invention further provides a non-volatile readable storage medium on which a computer program is stored. When the computer program is executed by the processor 102, the method for extracting the interface state density of the semiconductor device described in the above embodiment is implemented. The specific implementation process of the method for extracting the interface state density of the semiconductor device can refer to the description of the above embodiment.

[0119] According to the non-volatile readable storage medium of an embodiment of the present invention, by executing a computer program related to a method for extracting the interface state density of a semiconductor device, the interface state density of the semiconductor device at the energy level position near the conduction band can be extracted, which is more conducive to the optimization of the characteristics of the semiconductor device.

[0120] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0121] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for extracting interface state density of a semiconductor device, characterized in that: include: Obtaining a drain current corresponding to a gate voltage according to a gate-drain transfer characteristic of a semiconductor device; Obtaining a surface potential at a conductive channel of the semiconductor device according to the drain current; Obtaining an interface state charge equivalent voltage according to the gate voltage; The interface state density is obtained according to the surface potential and the interface state charge equivalent voltage.

2. The method according to claim 1, characterized in that Obtaining interface state density according to the surface potential and the equivalent voltage change includes: Obtaining a surface potential variation, wherein the surface potential variation is a variation of the surface potential as the drain current changes; Obtaining an interface state charge equivalent voltage variation, wherein the interface state charge equivalent voltage variation is a variation of the interface state charge equivalent voltage as the gate voltage changes; The interface state density is obtained according to the surface potential change and the interface state charge equivalent voltage change.

3. The method according to claim 2, characterized in that The interface state density is obtained by the following formula: Among them, D it is the interface state density, is the surface potential change, C ox is the oxide layer capacitance per unit area, q is the electrostatic charge, ΔV it is the change in the interface state charge equivalent voltage.

4. The method according to claim 1, characterized in that: Obtaining a surface potential at a conductive channel of the semiconductor device according to the drain current, comprising: The surface potential is obtained by solving the one-dimensional Poisson equation using the following formula: Among them, I ds is the drain current, μ is the electron mobility of the conductive channel, W is the conductive channel width, L is the conductive channel length, Q i,v＝0 is the inversion layer electron density when the electron quasi-Fermi potential is zero, V ds is the drain voltage.

5. The method according to claim 1, characterized in that Obtaining an interface state charge equivalent voltage according to a gate voltage of the gate-drain transfer characteristic includes: The interface state charge equivalent voltage is obtained according to the following formula: Among them, V it is the interface state charge equivalent voltage, V gs is the gate voltage, V fb is the flat band voltage of the semiconductor device, is the surface potential, ε s is the dielectric constant of the semiconductor device substrate, E is the vertical electric field at the gate oxide interface, C ox is the oxide layer capacitance per unit area.

6. The method according to any one of claims 1 to 5, characterized in that: The semiconductor device is configured in the following manner to characterize the gate-drain transfer characteristics of the semiconductor device: The source is grounded; The drain is biased at a preset drain voltage in the mV range; The gate voltage changes within a preset voltage scanning range so that the semiconductor device changes from a depletion state to a strong inversion state; The gate-drain transfer characteristic is a curve showing a change in the drain current as a function of the gate voltage.

7. The method according to claim 6, characterized in that The preset drain voltage V ds Satisfy: |V ds |≤200mV.

8. The method according to claim 6, characterized in that The preset voltage scanning range is 0V-5V, and the voltage step length of the gate voltage does not exceed 200mV.

9. The method according to claim 1, characterized in that: The method further comprises: Obtaining the Fermi level position and interface state density of the semiconductor device at different gate voltages corresponding to the gate-drain transfer characteristics; An interface state density energy level distribution curve is obtained according to the Fermi energy level position and the interface state density, wherein the Fermi energy level position is the abscissa and the interface state density is the ordinate.

10. The method according to claim 9, characterized in that The Fermi level position is obtained by the following formula: Among them, E c -E1 represents the energy level E1 relative to the bottom of the conduction band E c The location of E g is the bandgap width of the semiconductor device substrate, q is the electrostatic charge, is the surface potential, is the bulk Fermi potential of the semiconductor device substrate.

11. The method according to claim 1, characterized in that: The semiconductor device includes a metal oxide semiconductor field effect transistor based on SiC material.

12. An electronic device, characterized in that: include: at least one processor; a memory communicatively coupled to the at least one processor; The memory stores a computer program executable by the at least one processor, and the at least one processor implements the method for extracting the interface state density of a semiconductor device as described in any one of claims 1 to 11 when executing the computer program.

13. A non-volatile readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, the method for extracting the interface state density of a semiconductor device according to any one of claims 1 to 11 is implemented.

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