Semiconductor device

Abstract

The invention provides a semiconductor device and a forming method thereof, the semiconductor device comprises a plurality of array blocks, each array block comprises a plurality of first address lines and a plurality of second address lines, the first address lines extend along a first direction, the second address lines extend along a second direction, and the first address lines and the second address lines intersect in different planes. The first address line has a first size in the first direction, the second address line has a second size in the second direction, and the first size is larger than a half of the second size. According to the design of the array block in the embodiment of the invention, the length of the first address line in the extension direction is increased, and the area of the array block is increased. As the number of the first address lines is not increased, the number of circuits for controlling the first address lines does not need to be increased, equivalently, the whole array block adopts fewer first address line control circuits to control a larger array block, so that more design areas of other circuits can be vacated, and the overall performance of the memory is further optimized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] In order to solve the extreme challenges of memory miniaturization and three-dimensional stacking, Selector Only Memory (SOM) in non-volatile memory technology has attracted widespread attention from researchers at home and abroad. Its storage unit consists of only one selector, combining memory and selector.

[0003] Currently, the research on selective memory is mainly based on a three-dimensional stacking architecture based on a cross-point matrix. In the array block designed based on this research, the layout space of the circuit is limited, thereby affecting the overall performance of the memory.

[0004] Therefore, how to increase the circuit design area in the array block is a problem that needs to be solved urgently. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor device that can increase the circuit design area in an array block.

[0006] The present application provides a semiconductor device, comprising: a plurality of array blocks, each of the array blocks comprising a plurality of first address lines and a plurality of second address lines, the first address lines extending along a first direction, the second address lines extending along a second direction, and the first address lines and the second address lines crossing in different planes, the first address lines having a first size in the first direction, the second address lines having a second size in the second direction, and the first size being greater than half of the second size.

[0007] In some embodiments, each of the array blocks includes an array core area and a first via area arranged along the second direction, the area where the first address line and the second address line intersect forms the array core area, and the second address line spans the array core area and the first via area; the number of the second address lines is greater than one half of the number of the first address lines.

[0008] In some embodiments, the ratio of the area of ​​the array core region to the area of ​​the array block is 65.4% to 71.1%.

[0009] In some embodiments, a size of the array block along the second direction is 230 micrometers to 240 micrometers, and a size of the array block along the first direction is 170 micrometers to 190 micrometers.

[0010] In some embodiments, the array block includes two array core areas and one first via area, and along the second direction, the first via area is located between the two array core areas; the size of the array core area along the first direction is larger than the size along the second direction.

[0011] In some embodiments, a size of the array core region along the second direction is 80 micrometers to 90 micrometers, and a size of the array core region along the first direction is 160 micrometers to 180 micrometers.

[0012] In some embodiments, the size of the array core region along the first dimension is twice the size along the second dimension.

[0013] In some embodiments, it also includes: a first circuit, a second circuit and an expansion circuit, all of which are arranged on a side of the first address line away from the second address line; the first circuit and the expansion circuit are both located in the core area of ​​the array, and the first circuit is electrically connected to the first address line; the second circuit is at least located in the first via area, and is connected to the second address line through a conductive plug in the first via area.

[0014] In some embodiments, it also includes: a second via area, a third address line and a third circuit; the second via area is located on at least one side of each array core area along the first direction; the third address line extends along the first direction and spans two adjacent array blocks; the third circuit is located on the side of the first address line away from the second address line, the third circuit is at least located in the second via area, and is connected to the third address line through a conductive plug in the second via area.

[0015] In some embodiments, the array blocks are arranged in an array in the first direction and the second direction and are stacked in a third direction, which is perpendicular to the plane of the first direction and the second direction; the two array blocks stacked along the third direction are offset from each other in the first direction and the second direction.

[0016] In the semiconductor device provided by the present application, each array block includes a plurality of first address lines and a plurality of second address lines, and the first size is greater than half of the second size. Compared with the case where the first size is less than half of the second size, the design of the array block in the present application lengthens the length of the first address line in the extension direction, thereby increasing the area of ​​the array block. Since the number of first address lines is not increased, the number of circuits for controlling the first address lines does not need to be increased, which is equivalent to the entire array block using fewer first address line control circuits to control a larger array block, thereby freeing up more design area for other circuits, further optimizing the overall performance of the memory.

[0017] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0019] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0020] Figure 1 is a schematic diagram of a top view of a semiconductor device provided in some embodiments of the present application;

[0021] Figure 2 This application Figure 1 A schematic diagram of the layout of an array block of a semiconductor device in an embodiment;

[0022] Figure 3 is a schematic diagram of a top view of a semiconductor device provided in some other embodiments of the present application;

[0023] Figure 4 This application Figure 3 A schematic diagram of the layout of an array block of a semiconductor device in an embodiment;

[0024] Figure 5 is a schematic diagram of a cross-sectional structure of a plurality of array blocks along a second direction and a third direction provided by some embodiments of the present application;

[0025] Figure 6 is a schematic diagram of a cross-sectional structure of a plurality of array blocks along a first direction and a third direction provided by some embodiments of the present application;

[0026] Figure 7 A schematic diagram of the arrangement of address lines in an array block provided by an embodiment;

[0027] Figure 8 yes Figure 7 Dimensional design diagram of array blocks provided in the embodiment;

[0028] Fig. 9 This application Figure 3 and Figure 4 The dimension design diagram of the array block provided in the embodiment. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0030] Currently, the array block of the selected memory is mainly laid out with the number of bit lines being about twice the number of word lines, but the length of the bit line is less than half the length of the word line. The design method with the number of bit lines being about twice the number of word lines makes it easier to control the voltage drop of the bit lines, but the length of the bit lines limits the area of ​​the array block and the design area of ​​the underlying circuit.

[0031] Based on the above reasons, an embodiment of the present application provides a semiconductor device, which includes a plurality of array blocks, each of the array blocks includes a plurality of first address lines and a plurality of second address lines, the first address lines extend along a first direction, the second address lines extend along a second direction, and the first address lines and the second address lines cross in different planes, the first address lines have a first size in the first direction, the second address lines have a second size in the second direction, and the first size is greater than half of the second size.

[0032] Compared to the case where the first size is less than half of the second size, the design of the array block in the embodiment of the present application lengthens the length of the first address line in the extension direction, thereby increasing the area of ​​the array block. Since the number of first address lines is not increased, the number of circuits for controlling the first address lines does not need to be increased, which is equivalent to using fewer first address line control circuits to control a larger array block in the entire array block, thereby freeing up more design area for other circuits, further optimizing the overall performance of the memory.

[0033] The semiconductor device provided in the embodiments of the present application is described below with reference to the accompanying drawings.

[0034] See also Figure 1 and Figure 2 , Figure 1 is a schematic diagram of a top view of a semiconductor device provided in some embodiments of the present application, Figure 2 This application Figure 1 A schematic diagram of the layout of an array block of a semiconductor device in an embodiment. It should be noted that: Figure 1 and Figure 2 The dashed box in the figure represents the range of an array block. Figure 1 It mainly shows the arrangement of the first address line and the second address line in an array block. Figure 2 It mainly shows the layout of the driving circuit in an array block.

[0035] The semiconductor device 100 includes a plurality of array blocks 10, each of the array blocks 10 includes a plurality of first address lines 11 and a plurality of second address lines 12, the first address lines 11 extend along a first direction Y, the second address lines 12 extend along a second direction X, and the first address lines 11 and the second address lines 12 cross in different planes, the first address lines 11 have a first size L1 in the first direction Y, the second address lines 12 have a second size L2 in the second direction X, and the first size L1 is greater than half of the second size L2.

[0036] In some embodiments, the first size L1 may be equal to half of the second size L2 , that is, the length of the first address line 11 is twice the length of the second address line 12 .

[0037] The first address line 11 and the second address line 12 cross in different planes, which means that the first address line 11 and the second address line 12 are not in the same plane. Figure 1 As shown, the first address line 11 may be located below the second address line 12, so the second address line 12 blocks part of the first address line 11. It can be understood that the first direction Y and the second direction X are also skewed, for example, the first direction Y may be perpendicular to the second direction X or intersect at a certain angle.

[0038] In some embodiments, one of the first address line 11 and the second address line 12 is a bit line, and the other is a word line. Figure 1 The first address line 11 is a bit line, and the second address line 12 is a word line.

[0039] like Figure 2 As shown, from the layout of the array block 10, each of the array blocks 10 may include an array core area C and a first via area V1 arranged along the second direction X, the first address line 11 is located in the array core area C, and the second address line 12 spans the array core area C and the first via area V1. The area where the first address line 11 and the second address line 12 intersect forms the array core area C. The area ratio of the array core area C to the array block 10 is the array efficiency of the array block 10.

[0040] In some embodiments, the array block 10 includes two array core regions C and one first via region V1. Along the second direction X, the first via region V1 is located between the two array core regions C. In other words, the array core region C is located on both sides of the first via region V1 along the second direction X, which can reduce the overall voltage drop.

[0041] In some embodiments, the size of each array core region C along the first direction Y is larger than the size along the second direction X, thereby providing space for the layout of the first address lines 11 and the second address lines 12. In some embodiments, the number of the second address lines 12 is larger than half of the number of the first address lines 11, and the number of the second address lines 12 increases with the length of the first address lines 11, and the area of ​​the array core region C can be increased accordingly.

[0042] The semiconductor device 100 may further include a first circuit S1, a second circuit S2, and an expansion circuit D, wherein the first circuit S1, the second circuit S2, and the expansion circuit D are all arranged on a side of the first address line 11 away from the second address line 12. The first circuit S1 and the expansion circuit D are both located in the array core area C, and the first circuit S1 is electrically connected to the first address line 11. The second circuit S2 is at least located in the first via area V1, and is connected to the second address line 12 through a conductive plug in the first via area V1.

[0043] In some embodiments, the first circuit S1 may include a word line selector, and the second circuit S2 may include a bit line selector. The expansion circuit D is located at both sides of the first circuit S1 along the first direction Y, and the expansion circuit D may include a decoder and a control circuit.

[0044] See also Figure 3 and Figure 4 , Figure 3 is a schematic diagram of a top view of a semiconductor device provided in some other embodiments of the present application, Figure 4 This application Figure 3 A schematic diagram of the layout of an array block of a semiconductor device in an embodiment. It should be noted that: Figure 3 and Figure 4 The dotted box in FIG. 1 represents the range of an array block 10. Figure 3 It mainly shows the arrangement of the first address line 11 and the second address line 12 in an array block 10. Figure 4 It mainly shows the layout of the driving circuit in an array block 10. The driving circuit is located at the bottom layer, that is, at the lower layer of the first address line 11.

[0045] Figure 3 and Figure 4 Example and Figure 1 and Figure 2 The difference between the embodiments is that the semiconductor device 100 has a two-layer stacked structure.

[0046] The semiconductor device 100 may further include a second via region V2, a third address line 13, and a third circuit S3, wherein the second via region V2 is located at least on one side of each array core region C along the first direction Y. The third address line 13 extends along the first direction Y and spans across two adjacent array blocks 10. The third circuit S3 is located on a side of the first address line 11 away from the second address line 12, and the third circuit S3 is at least located in the second via region V2, and is connected to the third address line 13 through a conductive plug in the second via region V2.

[0047] In some embodiments, the second via regions V2 are located on both sides of the array core region C in the first direction Y.

[0048] In some embodiments, a size of each array core region C along the first direction Y is greater than a size along the second direction X.

[0049] For example, the size of each array core area C along the first direction Y is twice the size along the second direction X. When an array block 10 includes two array core areas C, it is equivalent to that the size of one array core area C along the first direction Y is equal to the sum of the sizes of the two array core areas C along the second direction X.

[0050] In some embodiments, Figure 3 As shown, a third address line 13 extends from the array block 10 to another array block 10 adjacent along the first direction Y. Two third address lines 13 separated from each other are included in one array block 10. For example, a portion of two third address lines 13 adjacent to each other along the first direction Y exist in one array block 10, and the two third address lines 13 are spaced apart at positions corresponding to the first circuit S1, and a portion of the first address line 11 is exposed at the spaced position.

[0051] In some embodiments, the array blocks 10 are arranged in an array in the first direction Y and the second direction X, and are stacked in a third direction, the third direction being perpendicular to the plane of the first direction and the second direction, wherein the two array blocks 10 stacked along the third direction are offset from each other.

[0052] For example, the two array blocks 10 stacked along the third direction may be offset from each other along the first direction Y by a distance of half the array block 10 , and may also be offset from each other along the second direction X by a distance of half the array block 10 .

[0053] The semiconductor device 100 may further include a first conductive plug CT1, a second conductive plug CT2, and a third conductive plug CT3, wherein the first conductive plug CT1 is connected between the first circuit S1 and the first address line 11. The second conductive plug CT2 is located in the first via region V1, and is connected between the second circuit S2 and the second address line 12. The third conductive plug CT3 is located in the second via region V2, and is connected between the third circuit S3 and the third address line 13.

[0054] The semiconductor device 100 may further include a memory array located in the core array region C.

[0055] In some embodiments, the memory array may include a first memory cell structure and a second memory cell structure, wherein the first memory cell structure is located between the first address line 11 and the second address line 12, and is located at the intersection of the first address line 11 and the second address line 12; and the second memory cell structure is located between the second address line 12 and the third address line 13, and is located at the intersection of the second address line 12 and the third address line 13. That is, the first memory cell structure and the second memory cell structure share a layer of second address line 12.

[0056] In some other embodiments, the semiconductor device 100 further includes a fourth address line, which is located between the second address line 12 and the third address line 13 , extends along the second direction X, and crosses the array core region C and the first via region V1 .

[0057] The fourth address line can be connected to the second address line 12 in a one-to-one correspondence and overlapped, so Figure 3 The fourth address line is not visible in the figure, the second address line 12 is a lower word line, and the fourth address line can be an upper word line. The first conductive plug CT1 is also connected to the fourth address line, that is, the first circuit S1 drives the second address line 12 and the fourth address line together.

[0058] The first memory cell structure is located between the first address line 11 and the second address line 12, and at the intersection of the first address line 11 and the second address line 12; the second memory cell structure is located between the fourth address line and the third address line 13, and at the intersection of the fourth address line and the third address line 13. In other words, the first memory cell structure is controlled by the first address line 11 and the second address line 12, and the second memory cell structure is controlled by the third address line 13 and the fourth address line. In some embodiments, an array block 10 may include the first address line 11, the second address line 12, the third address line 13, and the fourth address line, as well as the first memory cell structure and the second memory cell structure along the third direction.

[0059] See also Figure 5 and Figure 6 , Figure 5 is a schematic diagram of a cross-sectional structure of a plurality of array blocks along a second direction and a third direction provided in some embodiments of the present application, Figure 6 It is a schematic diagram of the cross-sectional structure of multiple array blocks along the first direction and the third direction provided by some embodiments of the present application. Figure 5 and Figure 6 The first array block B1 and the second array block B2 are stacked along the third direction Z, and the first array block B1 and the second array block B2 are both distributed in the first direction Y and the second direction X in an array.

[0060] The first array block B1 includes a first address line 11, a second address line 12, a third address line 13, and a fourth address line 14, and a first memory cell structure C1 and a second memory cell structure C2 along the third direction Z. The first memory cell structure C1 is located between the first address line 11 and the second address line 12, the second memory cell structure C2 is located between the third address line 13 and the fourth address line 14, and the fourth address line 14 is located between the second address line 12 and the second memory cell structure C2.

[0061] The second array block B2 includes the fifth address line 15, the sixth address line 16, the seventh address line 17 and the eighth address line 18, and the third memory cell structure C3 and the fourth memory cell structure C4 along the third direction. The third memory cell structure C3 is located between the fifth address line 15 and the sixth address line 16, the fourth memory cell structure C4 is located between the seventh address line 17 and the eighth address line 18, and the eighth address line 18 is located between the sixth address line 16 and the fourth memory cell structure C4.

[0062] In some embodiments, each memory cell structure is located at the intersection between two address lines. Each memory cell structure may include a first electrode, a gating layer, a second electrode, a phase change memory layer, and a third electrode stacked along a third direction Z. Taking the first memory cell structure C1 as an example, its first electrode is connected to the first address line 11, and its third electrode is connected to the second address line 12.

[0063] In some other embodiments, each memory cell structure may include a first electrode, a gating layer, and a second electrode stacked along a third direction Z. Taking the first memory cell structure C1 as an example, its first electrode is connected to the first address line 11, and its second electrode is connected to the second address line 12. The gating layer has both storage and switching functions.

[0064] In some embodiments, the material of the gating layer is a dual-function material (DFM). Exemplarily, the material of the gating layer may include any appropriate bidirectional threshold switch (OTS) material, which may include chalcogenide alloys, such as germanium (Ge), arsenic (As) and selenium (Se) and compounds thereof; the first electrode and the second electrode may be the same material or different materials, and the materials of the first electrode and the second electrode include but are not limited to copper (Cu), aluminum (Al), gold (Au), tungsten (W), carbon (C) and compounds thereof, conductive doped semiconductors, etc.

[0065] In some embodiments, the second array block B2 is offset along the first direction Y and along the second direction X relative to the first array block B1 .

[0066] In some embodiments, Figure 5 As shown, the second array block B2 is offset by a distance of half an array block along the second direction X relative to the first array block B1; Figure 6 As shown, the second array block B2 is offset along the first direction Y by a distance of half an array block relative to the first array block B1.

[0067] In some embodiments, the first array block B1 further includes a first conductive plug CT1, a second conductive plug CT2, and a third conductive plug CT3. Figure 6 As shown, the first conductive plug CT1 is located on a side of the first address line 11 away from the second address line 12, and is connected to the first address line 11. Figure 5 As shown, the second conductive plug CT2 is located at a side of the second address line 12 away from the fourth address line 14, and is connected to the second address line 12. Figure 6 As shown, the third conductive plug CT3 is located at a side of the third address line 13 away from the fifth address line 15 , and is connected to the third address line 13 .

[0068] The second array block B2 also includes conductive plugs to connect the address lines. The connection method between the conductive plugs and the address lines in the first array block B1 may be referred to and will not be described in detail herein.

[0069] See also Figure 7 , Figure 7 The following is a schematic diagram of the arrangement of address lines in an array block provided by an embodiment. Figure 1 and Figure 3 The difference in the embodiment is that Figure 7 In the embodiment, the size of the first address line 11 along the first direction Y is smaller than half of the size of the second address line 12 along the second direction X, and the number of the first address lines 11 is greater than or equal to twice the number of the second address lines 12 , so that the voltage drop of the first address line 11 can be reduced.

[0070] contrast Figure 3 (or Figure 1 )and Figure 7 It can be seen that Figure 1 and Figure 3 In the array block 10 of the semiconductor device 100 provided in the embodiment, the length of the first address line 11 is lengthened, and the number of the second address lines 12 is increased, so the area of ​​the array core area C (or the storage array) is increased, and the space of the array block 10 along the first direction Y is increased. Correspondingly, the length of the third address line 13 is also increased, but the number remains unchanged.

[0071] Since the number of the first address lines 11 (connecting the first circuit S1) and the third address lines 13 (connecting the corresponding third circuit S3) does not increase, the area of ​​the first circuit S1 and the area of ​​the third circuit S3 can remain unchanged. Figure 4 It can be seen that the array block 10 is arranged along the first direction Y with the third circuit S3, the expansion circuit D and the first circuit S1. Since the areas of the first circuit S1 and the third circuit S3 can remain unchanged, the area of ​​the expansion circuit D can be relatively increased, which increases the designability and further optimizes the overall performance of the memory.

[0072] Although the area of ​​the array block 10 increases, the areas of the expansion circuit D and the array core area C are mainly increased, so the area proportion of the expansion circuit D in the array block 10 increases, and the area proportion of the array core area C in the array block 10 increases, so the utilization rate of the expansion circuit D increases and the array efficiency is improved.

[0073] In some embodiments, the semiconductor device 100 includes a plurality of array blocks 10 arranged in an array, and an isolation region is provided between two adjacent array blocks 10 to reduce interference between adjacent array blocks 10 . However, the isolation region occupies a portion of the area of ​​the entire semiconductor device 100 .

[0074] In the semiconductor device 100 provided in the present application, since the area of ​​a single array block 10 is increased, the number of array blocks 10 in the entire semiconductor device 100 is reduced, and the number and area of ​​isolation regions are also reduced, thereby further improving the array efficiency of the array block 10.

[0075] See also Figure 8 and Fig. 9 , Figure 8 yes Figure 7 The dimension design diagram of the array block provided in the embodiment, Fig. 9 This application Figure 3 and Figure 4 The dimension design diagram of the array block provided in the embodiment.

[0076] like Figure 8 As shown, the size BXL1 of the array block 10 along the second direction X can be 230um to 240um, the size BYL1 of the array block 10 along the first direction Y can be 90um to 110um, the size AXL1 of the array core area C along the second direction X and the size ALY1 of the array core area C along the first direction Y can both be 80um to 90um. According to different size values, the array efficiency of the array core area C is 61.8% to 67.5%.

[0077] like Figure 4 and Fig. 9 As shown, the size BXL2 of the array block 10 along the second direction X can be 230um-240um, the size BYL2 of the array block 10 along the first direction Y can be 170um-190um, the size AXL2 of the array core area C along the second direction X is 80um-90um, and the size ALY2 of the array core area C along the first direction Y can be 160um-180um, and the array efficiency of the array core area C is 65.4%-71.1%. Figure 8 In the embodiment, the array efficiency of the array block 10 in the semiconductor device 100 provided in the embodiment of the present application is improved by 3% to 4%, and the overall cost is reduced.

[0078] The embodiments of the present application also provide a method for forming the semiconductor device in any of the above embodiments. All methods for forming the semiconductor device are within the protection scope of the present application.

[0079] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0080] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0081] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0082] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A semiconductor device, characterized in that: include: A plurality of array blocks, each of the array blocks comprising a plurality of first address lines and a plurality of second address lines, the first address lines extending along a first direction, the second address lines extending along a second direction, and the first address lines and the second address lines crossing in different planes, the first address lines having a first size in the first direction, the second address lines having a second size in the second direction, and the first size being greater than one half of the second size.

2. The semiconductor device according to claim 1, wherein: Each of the array blocks comprises an array core area and a first via area arranged along the second direction, the area where the first address line and the second address line intersect forms the array core area, and the second address line spans the array core area and the first via area; The number of the second address lines is greater than half of the number of the first address lines.

3. The semiconductor device according to claim 2, characterized in that The ratio of the area of ​​the array core region to the area of ​​the array block is 65.4% to 71.1%.

4. The semiconductor device according to claim 2, characterized in that The size of the array block along the second direction is 230 micrometers to 240 micrometers, and the size of the array block along the first direction is 170 micrometers to 190 micrometers.

5. The semiconductor device according to claim 2, wherein: The array block includes two array core areas and one first via area. Along the second direction, the first via area is located between the two array core areas. The size of the array core area along the first direction is greater than the size along the second direction.

6. The semiconductor device according to claim 5, characterized in that The size of the array core area along the second direction is 80 micrometers to 90 micrometers, and the size of the array core area along the first direction is 160 micrometers to 180 micrometers.

7. The semiconductor device according to claim 5, characterized in that The size of the array core region along the first direction is twice the size along the second dimension direction.

8. The semiconductor device according to claim 1, wherein: Also includes: The first circuit, the second circuit and the expansion circuit are all arranged on a side of the first address line away from the second address line; The first circuit and the expansion circuit are both located in the core area of ​​the array, and the first circuit is electrically connected to the first address line; The second circuit is at least located in the first via region and is connected to the second address line through a conductive plug in the first via region.

9. The semiconductor device according to claim 2, characterized in that Also includes: a second via region, a third address line, and a third circuit; The second via region is located on at least one side of each array core region along the first direction; The third address line extends along the first direction and crosses two adjacent array blocks; The third circuit is located at a side of the first address line away from the second address line. The third circuit is at least located in the second via region and is connected to the third address line through a conductive plug in the second via region.

10. The semiconductor device according to claim 1, wherein: The array blocks are arranged in arrays in the first direction and the second direction, and are stacked in a third direction, and the third direction is perpendicular to the plane of the first direction and the second direction; The two array blocks stacked along the third direction are offset from each other in the first direction and the second direction.

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