Semiconductor memory device and test method thereof

Abstract

The invention provides a semiconductor memory device and a testing method thereof. The semiconductor memory device includes a plurality of word lines, a row decoder, a first voltage pump circuit, a first programmable current comparator, and a control circuit. The row decoder decodes the row address data and selects a test word line to be electrically connected with the first test path according to the row address data. The first voltage pump circuit is disposed on the first test path and applies a test voltage to the test word line. The first programmable current comparator compares a test current flowing through the first test path with a programmable reference current to provide a test result signal. The control circuit compares the corresponding test current with the programmable reference current by using the plurality of word lines as test word lines in sequence, and judges whether the test word lines are bad or not according to the test result signal.

Description

Technical Field

[0001] The present invention relates to a memory testing technology, and in particular to a semiconductor memory device and a testing method adopted therein. Background Art

[0002] Wordline leakage (including wordline to wordline, wordline to bitline and wordline to storage capacitor leakage) is a common defect in the manufacturing process of dynamic random access memory (DRAM), which is prone to quality problems. Compared with low-impedance wordline leakage (higher leakage current value), high-impedance wordline leakage (lower leakage current value) is difficult to detect through traditional functional tests. Although high-impedance wordline leakage may not cause memory function failure in real time, once the leakage current path exists, there is a risk of turning into low-impedance wordline leakage after a period of use, causing its reliability to deteriorate rapidly over time.

[0003] In order to improve the test quality and coverage, DC testing is an alternative solution that can directly apply voltage to the circuit board from the outside to measure the word line leakage current to detect high-impedance word line leakage current. However, when using DC testing, DC testing and functional testing need to be switched alternately, and the switching process is very time-consuming, making it impossible to introduce DC testing into the standard test items for mass production. Summary of the invention

[0004] The present invention provides a semiconductor memory device and a test method thereof, which can detect a high-impedance word line leakage current in a functional test.

[0005] The semiconductor memory device of the present invention includes a plurality of word lines, a row decoder, a first voltage pump circuit, a first programmable current comparator and a control circuit. The row decoder is coupled between the plurality of word lines and the first test path, decodes the row address data, and selects a test word line from the plurality of word lines to be electrically connected to the first test path. The first voltage pump circuit is configured on the first test path, receives and adjusts the operating voltage to apply the test voltage to the test word line. The first programmable current comparator is coupled to the first test path, transmits the operating voltage to the first voltage pump circuit according to the received supply voltage, and compares the test current flowing through the first test path with the programmable reference current to provide a test result signal. The control circuit is coupled to the row decoder and the first programmable current comparator, and according to the operation command, sequentially uses the plurality of word lines as test word lines to compare the corresponding test current with the programmable reference current through the first programmable current comparator, and determines whether the test word line is defective according to the corresponding test result signal.

[0006] The testing method of the semiconductor memory device of the present invention comprises the following steps: decoding the row address data by a row decoder, and selecting a test word line from a plurality of word lines to be electrically connected to a test path; receiving an operating voltage obtained according to a supply voltage and adjusting it, so as to apply the test voltage to the test word line through the test path; comparing the test current flowing through the test path with a programmable reference current to provide a test result signal; and according to an operation command, using a plurality of word lines as test word lines in sequence to compare the corresponding test current with the programmable reference current, and judging whether the test word line is defective according to the corresponding test result signal.

[0007] Based on the above, the semiconductor memory device and its testing method of the present invention can simplify the test of high-impedance word line leakage current to be performed in the functional test, overcoming the limitation that the DC test and the functional test need to be switched alternately. In this way, not only can the test time be greatly reduced, but it can also be introduced into the standard test items of mass production to filter out bad components and improve the reliability of the product.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention;

[0010] Figure 2 is a circuit diagram of a programmable current comparator according to an embodiment of the present invention;

[0011] Figure 3 is a flow chart of a test operation of a semiconductor memory device according to an embodiment of the present invention;

[0012] Figure 4 is a waveform diagram of a test operation of a semiconductor memory device according to an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of the structure of a row address latch according to an embodiment of the present invention;

[0014] Figure 6 is a partial circuit diagram of a semiconductor memory device according to another embodiment of the present invention;

[0015] Figure 7 is a flow chart of a method for testing a semiconductor memory device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0017] Please refer to Figure 1 The semiconductor memory device 100 includes n word lines WL0 to WLn-1, a row decoder 110, a voltage pump circuit 120, a programmable current comparator 130, a control circuit 140, a row address latch 150, and a refresh counter 160. The word lines WL0 to WLn-1 are respectively arranged to cross with m bit line pairs formed by bit lines BL0 to BLm-1 and BL*0 to BL*m-1, and memory cells MC are arranged at the intersections of the word lines and the bit lines. These memory cells M can, for example, form a dynamic random access memory (DRAM) array. n and m are positive integers greater than 1.

[0018] The row decoder 110 is coupled between the word lines WL0-WLn-1 and the test path TP. The row decoder 110 can decode the row address data ADD and select the test word line WLt from the word lines WL0-WLn-1 according to the decoding result to be electrically connected to the test path TP. Figure 1 The illustrated case is that the word line WL1 is selected as the test word line WLt, but this case is only an example, and the bit line serving as the test word line WLt will change with the increment of the row address data ADD.

[0019] The voltage pump circuit 120 is disposed on the test path TP. The voltage pump circuit 120 can receive the operating voltage Vt and adjust it to apply the test voltage Vpp to the test word line WLt. For example, the voltage pump circuit 120 can respond to a specific oscillation signal to increase the operating voltage Vt, thereby generating a test voltage Vpp (e.g., 3.3 or 3.5 volts) to be applied to the test word line WLt via the test path TP.

[0020] The programmable current comparator 130 is coupled to the test path TP. The programmable current comparator 130 can transmit the operating voltage Vt to the voltage pump circuit 120 according to the received supply voltage Vs. The supply voltage Vs can be converted from a power supply voltage inside or outside the semiconductor memory device 100, for example, 2.9 volts. In addition, the programmable current comparator 130 can compare the test current Ivpp flowing through the test path TP with the programmable reference current to provide a test result signal Dout. When the test result signal Dout is at a first logic level, it indicates that the test word line WLt is bad, and when the test result signal Dout is at a second logic level, it indicates that the test word line WLt is good. Incidentally, the above-mentioned first logic level can be logic 1 or logic 0, and the above-mentioned second logic level can be logic 0 or 1 complementary to the first logic level, without fixed restrictions. When the test word line WLt is good, the test current Ivpp is, for example, about 10mA. When the test word line WLt is bad, the test current Ivpp is increased to, for example, 20mA, 30mA, or even 100mA.

[0021] Since the programmable current comparator 130 is located at the DC source of the internal test path TP of the semiconductor memory device 100 , it is able to isolate noise and interference sources and focus on testing the leakage current of the test word line WLt, thereby improving the test accuracy.

[0022] The control circuit 140 is coupled to the row decoder 110 and the programmable current comparator 130. The control circuit 140 is, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD) or other similar devices.

[0023] The programmable reference current of the programmable current comparator 130 can be pre-adjusted according to the setting signal Sset provided by the control circuit 140. The following examples are used to illustrate the internal details of the programmable current comparator 130. Figure 2, the setting signal Sset provided by the control circuit 140 includes a first setting signal Sset1, a second setting signal Sset2, a third setting signal Sset3 and a fourth setting signal Sset4. The programmable current comparator 130 includes an input node Nin, an output node Nout, a first switch SW1 to a fourth switch SW4, a first resistor R1 to a sixth resistor R6, a first comparator CMP1 and a second comparator CMP2. The input node Nin receives a supply voltage Vs. The output node Nout is coupled to the test path TP and is used to output an operating voltage Vt. The first switch SW1 to the fourth switch SW4 are respectively coupled between the input node Nin and the output node Nout in different circuit paths, and are respectively controlled by the first setting signal Sset1 to the fourth setting signal Sset4 to be turned on or off. The first resistor R1 and the first switch SW1 are connected in series on a first circuit path between the input node Nin and the output node Nout. The second resistor R2 and the second switch SW2 are connected in series on a second circuit path between the input node Nin and the output node Nout. The third resistor R3 and the third switch SW3 are connected in series on a third circuit path between the input node Nin and the output node Nout. The first end of the fourth resistor R4 is coupled to the input node Nin. The first end of the fifth resistor R5 is coupled to the output node Nout. The non-inverting input end of the first comparator CMP1 is coupled to the second end of the fourth resistor R4, and the inverting input end is coupled to the second end of the fifth resistor R5. The non-inverting input end of the second comparator CMP2 is coupled to the output end of the first comparator CMP1, the inverting input end receives a reference voltage Vref (for example, 1 volt, the voltage value can also be determined by the setting signal Sset), and the output end is used to output the test result signal Dout. The first end of the sixth resistor R6 is coupled to the non-inverting input end of the first comparator CMP1, and the second end is coupled to the non-inverting input end of the second comparator CMP2.

[0024] In this embodiment, the voltage Vout outputted by the output terminal of the first comparator CMP1 can be expressed by the following formula (1):

[0025] Vout=Id*Rsen*(R6 / R4) (1)

[0026] Wherein, Id is the current flowing from the input node Nin to the output node Nout, and Rsen is the equivalent resistance between the input node Nin and the output node Nout. The following Table 1 records the correspondence between the first setting signal Sset1 to the fourth setting signal Sset4 and the equivalent resistance Rsen. In this example, the first resistor R1 is 20 ohms, the second resistor R2 is 10 ohms, the third resistor R3 is 5 ohms, the fourth resistor R4 is 2.5k ohms, the fifth resistor R5 is 2.5k ohms, and the sixth resistor R6 is 22.5k ohms, but those skilled in the art can make appropriate adjustments according to their actual needs.

[0027]

[0028] Table 1

[0029] In this example, when the first setting signal Sset1 to the third setting signal Sset3 are logic 1, the first switch SW1 to the third switch SW3 are turned on, and when the fourth setting signal Sset4 is logic 1, the fourth switch SW4 is turned off. Conversely, when the first setting signal Sset1 to the third setting signal Sset3 are logic 0, the first switch SW1 to the third switch SW3 are turned off, and when the fourth setting signal Sset4 is logic 0, the fourth switch SW4 is turned on. In Table 1, the corresponding equivalent resistance Rsen is listed for the first setting signal Sset1 to the fourth setting signal Sset4 of various logical combinations. In the normal mode where the fourth switch SW4 is turned on (the fourth setting signal Sset4 is logic 0), the input node Nin and the output node Nout are short-circuited, and the word lines WL0 to WLn-1 are not tested at this time, and the supply voltage Vs is equal to the operating voltage Vt.

[0030] On the other hand, in the test mode where the fourth switch SW4 is disconnected (the fourth setting signal Sset4 is logic 1), the equivalent resistance Rsen between the input node Nin and the output node Nout will change with the different logical combinations of the first setting signal Sset1 to the third setting signal Sset3. When the test word line WLt is tested, the current Id is equal to the test current Ivpp, and the voltage Vout output by the output end of the first comparator CMP1 is equal to the voltage value obtained by substituting the current Id into formula (1) and calculating together with the preset equivalent resistance Rsen. Afterwards, the second comparator CMP2 compares the voltage Vout depending on the test current Ivpp with the reference voltage Vref, thereby achieving the effect of comparing the test current Ivpp with the programmable reference current. When the voltage Vout is greater than the reference voltage Vref, a test result signal Dout at a first logic level is generated. When the voltage Vout is less than the reference voltage Vref, a test result signal Dout at a second logic level is generated.

[0031] Through the circuit structure described above, the control circuit 140 can provide a setting signal Sset to the programmable current comparator 130 to adjust the test point (the gear of the programmable reference current) for different devices, memory specifications, and leakage current conditions to determine the abnormal range of the test current Ivpp. It should be noted that although the present embodiment is described with a programmable current comparator including 4 switches, the number of the above components is not used to limit the present invention. Those skilled in the art can, depending on their needs for the gear of the programmable reference current and referring to the teachings of this embodiment, extrapolate the number of the above components to less or more.

[0032] Please go back Figure 1 The row address latch 150 is coupled to the row decoder 110, the programmable current comparator 130 and the control circuit 140. When the test result signal Dout is at the first logic level (indicating that the test word line WLt is bad), the row address latch 150 can respond to the latch pulse signal Slatch output by the control circuit 140 and store the row address of the current row decoder 110 as the bad row address Badd.

[0033] The refresh counter 160 is coupled to the row decoder 110 and the control circuit 140. The refresh counter 160 can be used to increment the row address data ADD in the test mode, and output the incremented row address data ADD to the row decoder 110 in sequence.

[0034] The control circuit 140 can enter the test mode according to, for example, an operation command CMD from an external memory controller, and use the word lines WL0~WLn-1 in sequence as the test word line WLt to compare the corresponding test current Ivpp with the programmable reference current through the programmable current comparator 130, and determine whether the test word line WLt is defective according to the corresponding test result signal Dout.

[0035] For more details, please also refer to Figure 3 and Figure 4 First, in step S300, the control circuit 140 can set the internal voltage (including the test voltage Vpp, the word line voltage and the bit line voltage, etc.) to an appropriate logic level according to the operation command CMD. The semiconductor memory device 100 can respond to Figure 4 The intermediate frequency signal CLK is used to perform the operation. In step S302, Figure 4 At time point t1, the control circuit 140 enters the test mode related to the word line leakage current, sets the equivalent resistance Rsen and the reference voltage Vref of the programmable current comparator 130 through the setting signal Sset, and sets the initial value of i to 0.

[0036] In step S304, Figure 4 At time point t2, the control circuit 140 tests the word line WLi as the test word line WLt. Specifically, the control circuit 140 may issue a command to the refresh counter 160 to provide the row address data ADD corresponding to the word line WL0 to the row decoder 110, thereby causing the row decoder 110 to select the word line WL0 as the test word line WLt. As a result, the test voltage Vpp is applied to the test word line WLt, and the logic level of the test word line WLt rises to an enable level (3.3 volts). At the same time, during the test period of testing the test word line WLt, the control circuit 140 may control the row decoder 110 to disable the word lines WLi-1 and WLi+1 adjacent to the test word line WLt (word line WLi) to maintain them at a disable level (-0.2 volts).

[0037] In step S306, the control circuit 140 waits for a detection time Ts, such as 10 μs, to allow the voltage Vout in the programmable current comparator 130 to reach a steady state. Next, in step S308, Figure 4 At time point t3, the control circuit 140 outputs the execution pulse signal Scomp to the programmable current comparator 130 to start comparing the voltage Vout with the reference voltage Vref through the second comparator CMP2 to provide a test result signal Dout. If the voltage Vout is greater than the reference voltage Vref, the control circuit 140 receives the test result signal Dout of the first logic level. In this case, Figure 4 As shown, at time point t4, the control circuit 140 outputs the latch pulse signal Slatch to the row address latch 150, and stores the row address of the current row decoder 110 as the bad row address Badd. If the voltage Vout is less than the reference voltage Vref, the control circuit 140 receives the test result signal Dout of the second logic level. In this case, the control circuit 140 does not output the latch pulse signal Slatch to the row address latch 150.

[0038] In step S310, the control circuit 140 increments i (i=i+1) and determines whether the incremented i is greater than n-1. If not, the process returns to step S304 to continue testing the next test word line WLt (word line WL1). After completing the test of all word lines WL0 to WLn-1 by repeatedly executing steps S304, S306, S308, and S310, the incremented i will be greater than n-1, and the test operation of this embodiment is terminated.

[0039] It should be noted that, although the row address data ADD in this embodiment is provided sequentially by the refresh counter 160 according to the command from the control circuit 140, in other embodiments, the refresh counter may be omitted and the row address data ADD may be provided directly by the external memory controller. Figure 1 As shown, the test result signal Dout can also be directly transmitted to the outside through the input and output pins, so that the user can directly know which bit line is defective.

[0040] Through the test operation described above, the test for the high-impedance word line leakage current can be simplified to be performed during the functional test without the need for additional DC test, thereby significantly reducing the test time.

[0041] In one embodiment, the row address latch 150 is constructed in a stacked memory structure, for example, and has a First In Last Out (FILO) characteristic. Figure 5 As shown, the row address latch 150 includes k shift registers 500_0 ˜ 500_k−1 and an overflow buffer 510 .

[0042] Each shift register 500_0-500_k-1 includes a plurality of address bits 502 and a valid bit 504. The plurality of address bits 502 are used to store bad row addresses Badd consisting of binary values ​​A0-Aj-1. The valid bit 504 is used to store a valid flag FV indicating whether the corresponding plurality of address bits 502 are valid. k and j are positive integers greater than 1. The overflow buffer 510 is used to store an overflow flag FO indicating whether the row address latch 150 overflows.

[0043] Before testing the word line leakage current of the word lines WL0 to WLn-1, all buffers in the row address latch 150 need to be reset to logic 0. During the test of the word lines WL0 to WLn-1, the bad row address Badd will be input to the row address latch 150 in parallel and latched into the shift registers 500_0 to 500_k-1 in sequence. At this time, the valid flag FV of the shift register storing the bad row address Badd will be set to logic 1.

[0044] After the test of the word lines WL0-WLn-1 is completed, the bad row address Badd is serially outputted from the top shift register 500_0 through the output pin TDO in a first-in-last-out manner. In this way, a word line repair procedure can be automatically performed according to the bad row address Badd, for example, a spare bit line is used to replace a normal bit line corresponding to the bad row address Badd by blowing a fuse, and it is easy to combine and execute with the procedures of Post-Package-Repair (PPR), Built-In-Self-Test (BIST) and Built-In-Self-Build-In-Self-Test (BISR).

[0045] In addition, when all the shift registers 500_0 ˜ 500_k-1 have stored the bad row address Badd, the overflow flag FO will be set to logic 1 to indicate that the storage space of the row address latch 150 is full and no new bad row address Badd can be stored.

[0046] In one embodiment, bit lines of different blocks may be tested by different programmable current comparators due to different design methods. Figure 6 As shown, the semiconductor memory device 600 includes a row decoder 610 , a first voltage pump circuit 620_1 , a second voltage pump circuit 620_2 , a first programmable current comparator 630_1 , a second programmable current comparator 630_2 , and an OR gate 640 .

[0047] The row decoder 610 is coupled between the plurality of word lines corresponding to the first programmable current comparator 630_1 and the first test path TP1, and is coupled between the plurality of word lines corresponding to the second programmable current comparator 630_2 and the second test path TP2. The row decoder 610 can decode the row address data ADD, and according to the decoding result, the corresponding word line is used as the test word line WLt to be electrically connected to the first test path TP1 or the second test path TP2.

[0048] The first voltage pump circuit 620_1 is disposed on the test path TP1 and can receive and adjust the operation voltage Vt1 to apply the test voltage Vpp1 to the test word line WLt electrically connected to the first test path TP1.

[0049] The second voltage pump circuit 620_2 is disposed on the test path TP2 and can receive and adjust the operation voltage Vt2 to apply the test voltage Vpp2 to the test word line WLt electrically connected to the second test path TP2.

[0050] The first programmable current comparator 630_1 is coupled to the first test path TP1. The first programmable current comparator 630_1 can transmit the operation voltage Vt1 to the first voltage pump circuit 620_1 according to the received supply voltage Vs. In addition, the first programmable current comparator 630_1 can compare the test current Ivpp1 flowing through the first test path TP1 with the corresponding programmable reference current to output the first test result signal Dout1 to the OR gate 640.

[0051] The second programmable current comparator 630_2 is coupled to the second test path TP2. The second programmable current comparator 630_2 can transmit the operation voltage Vt2 to the second voltage pump circuit 620_2 according to the received supply voltage Vs. In addition, the second programmable current comparator 630_2 can compare the test current Ivpp2 flowing through the second test path TP2 with the corresponding programmable reference current to output the second test result signal Dout2 to the OR gate 640.

[0052] The first input terminal of the OR gate 640 receives the first test result signal Dout1 from the first programmable current comparator 630_1, the second input terminal receives the second test result signal Dout2 from the second programmable current comparator 630_2, and the output terminal provides the test result signal Dout. Through the circuit structure described above, multiple programmable current comparators can be set in the semiconductor memory device to test the bit lines of different blocks.

[0053] It should be noted that, according to different design methods, the equivalent resistance Rsen preset by the first programmable current comparator 630_1 and the second programmable current comparator 630_2 can be the same or different. The supply voltage Vs received by the first programmable current comparator 630_1 and the second programmable current comparator 630_2 can also be the same or different. In addition, the row decoder 610 can be split into multiple decoders to respectively couple different test paths to test the corresponding multiple word lines.

[0054] Furthermore, although the present embodiment is described with reference to a semiconductor memory device including two voltage pump circuits and two programmable current comparators, the number of the above components is not intended to limit the present invention. Those skilled in the art may, according to their actual needs and with reference to the teachings of the present embodiment, infer the number of the above components to be greater.

[0055] Please refer to Figure 7In this embodiment, the testing method of the semiconductor memory device includes the following steps. The row address data is decoded by a row decoder, and a test word line is selected from a plurality of word lines to be electrically connected to the test path (step S700). An operating voltage obtained according to a supply voltage is received and adjusted to apply the test voltage to the test word line through the test path (step S702). The test current flowing through the test path is compared with a programmable reference current to provide a test result signal (step S704). According to the operation command, a plurality of word lines are sequentially used as test word lines to compare the corresponding test current with the programmable reference current, and whether the test word line is defective is determined according to the corresponding test result signal (step S706). The implementation details of the above steps S700, S702, S704 and S706 can be referred to. Figures 1 to 6 The embodiments of the present invention will not be described in detail here.

[0056] It should be noted that although the testing method of this embodiment is mainly aimed at word line leakage current, the present invention is not limited thereto and can also be applied to other types of leakage detection on word lines through appropriate timing arrangement and required voltage setting.

[0057] In summary, the semiconductor memory device and the test method thereof of the present invention can simplify the test of the word line leakage current of high impedance to be performed in the functional test, without the need for additional DC test. In this way, not only can the test time be greatly reduced, but it can also be introduced into the standard test items of mass production to filter out bad components and improve the reliability of the product.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor memory device, characterized in that: include: multiple word lines; A row decoder, coupled between the plurality of word lines and the first test path, decodes row address data and selects a test word line from the plurality of word lines to be electrically connected to the first test path; A first voltage pump circuit is configured on the first test path, receives an operating voltage and adjusts it to apply a test voltage to the test word line; a first programmable current comparator coupled to the first test path, transmitting the operating voltage to the first voltage pump circuit according to the received supply voltage, and comparing the test current flowing through the first test path with a programmable reference current to provide a test result signal; as well as The control circuit is coupled to the row decoder and the first programmable current comparator. According to the operation command, the multiple word lines are sequentially used as the test word lines to compare the corresponding test current with the programmable reference current through the first programmable current comparator, and whether the test word line is defective is determined according to the corresponding test result signal.

2. The semiconductor memory device according to claim 1, wherein: When the test result signal is at a first logic level, it indicates that the test word line is defective, and when the test result signal is at a second logic level, it indicates that the test word line is good.

3. The semiconductor memory device according to claim 1, wherein: The control circuit provides a setting signal to the first programmable current comparator to adjust the programmable reference current according to the setting signal.

4. The semiconductor memory device according to claim 3, wherein: The setting signal includes a first setting signal, a second setting signal, a third setting signal and a fourth setting signal, and the first programmable current comparator includes: an input node receiving the supply voltage; an output node, coupled to the first test path and used to output the operating voltage; A first switch, coupled between the input node and the output node, and controlled to be turned on or off by the first setting signal; A first resistor connected in series with the first switch on a first circuit path between the input node and the output node; A second switch, coupled between the input node and the output node, and controlled to be turned on or off by the second setting signal; a second resistor connected in series with the second switch on a second circuit path between the input node and the output node; A third switch, coupled between the input node and the output node, and controlled by the third setting signal to be turned on or off; a third resistor connected in series with the third switch on a third circuit path between the input node and the output node; a fourth switch, coupled between the input node and the output node, and turned on or off by the fourth setting signal; a fourth resistor, a first end of which is coupled to the input node; a fifth resistor, a first end of which is coupled to the output node; A first comparator, a non-inverting input terminal of which is coupled to the second end of the fourth resistor, and an inverting input terminal of which is coupled to the second end of the fifth resistor; A second comparator, whose non-inverting input terminal is coupled to the output terminal of the first comparator, whose inverting input terminal receives a reference voltage, and whose output terminal is used to output the test result signal; and A sixth resistor has a first end coupled to the non-inverting input terminal of the first comparator, and a second end coupled to the non-inverting input terminal of the second comparator.

5. The semiconductor memory device according to claim 1, wherein: Also includes: The row address latch is coupled to the row decoder, the first programmable current comparator and the control circuit. When the test result signal is at a first logic level, the row address of the current row decoder is stored as a bad row address in response to a latch pulse signal output by the control circuit.

6. The semiconductor memory device according to claim 5, wherein: The row address latch is constructed in a stack memory structure. The row address latch includes a plurality of shift registers. Each of the plurality of shift registers includes: A plurality of address bits for storing the bad row address; and The valid bit is used to store a valid flag indicating whether the corresponding plurality of address bits are valid.

7. The semiconductor memory device according to claim 6, wherein: The row address latch also includes: The overflow buffer is used to store an overflow flag indicating whether the row address latch overflows.

8. The semiconductor memory device according to claim 1, wherein: After the test word line receives the test voltage, after a detection time, the control circuit outputs an execution pulse signal to the first programmable current comparator to start comparing the test current with the programmable reference current.

9. The semiconductor memory device according to claim 1, wherein: During a test period for testing the test word line, the control circuit controls the row decoder to disable the plurality of word lines adjacent to the test word line.

10. The semiconductor memory device according to claim 1, wherein: Also includes: The refresh counter is coupled to the row decoder and the control circuit, and is used for incrementing the row address data in a test mode, and sequentially outputting the incremented row address data to the row decoder.

11. The semiconductor memory device according to claim 1, wherein: Also includes: A second voltage pump circuit is disposed on a second test path coupled to the row decoder, receives an operating voltage and adjusts it to apply a test voltage to the test word line; a second programmable current comparator coupled to the second test path, transmitting the operating voltage to the second voltage pump circuit according to the received supply voltage, and comparing the test current flowing through the second test path with the programmable reference current to output a second test result signal; as well as An OR gate, a first input terminal of which receives the first test result signal from the first programmable current comparator, a second input terminal of which receives the second test result signal from the second programmable current comparator, and an output terminal of which provides the test result signal.

12. A method for testing a semiconductor memory device, characterized in that: The semiconductor memory device includes a plurality of word lines and a row decoder, wherein the row decoder is coupled between the plurality of word lines and a test path, and the test method includes the following steps: Decoding the row address data by the row decoder, and selecting a test word line from the plurality of word lines to electrically connect to the test path; receiving an operating voltage obtained according to a supply voltage and adjusting the operating voltage so as to apply a test voltage to the test word line via the test path; comparing a test current flowing through the test path with a programmable reference current to provide a test result signal; as well as According to the operation command, the plurality of word lines are sequentially used as the test word lines to compare the corresponding test current with the programmable reference current, and whether the test word line is defective is determined according to the corresponding test result signal.

13. The testing method according to claim 12, characterized in that: When the test result signal is at a first logic level, it indicates that the test word line is defective, and when the test result signal is at a second logic level, it indicates that the test word line is good.

14. The testing method according to claim 12, characterized in that: Also includes: The programmable reference current is adjusted according to a setting signal.

15. The testing method according to claim 12, characterized in that: Also includes: When the test result signal is at a first logic level, the current row address of the row decoder is stored in the row address latch as a bad row address in response to a latch pulse signal.

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