Focusing ring and preparation method thereof

Abstract

The invention relates to a focusing ring and a preparation method thereof, the focusing ring comprises a first semiconductor material layer, the first semiconductor material layer comprises a lower surface used for contacting an electrostatic chuck and an upper surface facing an upper electrode and a wafer to be processed, the upper surface of the first semiconductor material layer comprises a first surface and a second surface, the first surface is perpendicular to the thickness direction of the first semiconductor material layer, and the distance between each position in the second surface from outside to inside along the radial direction of the focusing ring and the lower surface is gradually reduced; the second semiconductor material layer is formed on the upper surface of the first semiconductor material layer through an epitaxial growth process, the crystal orientation of crystal grains in the second semiconductor material layer is perpendicular to the upper surface, and the second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer. Therefore, the influence of uneven deformation of the focusing ring on the edge electric field of the wafer is avoided, and uneven etching of the edge position of the wafer is finally avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a focusing ring and a method for preparing the same. Background Art

[0002] Plasma etching is one of the key processes in wafer processing. In the plasma etching chamber, an electrostatic chuck is used to fix the wafer, and the plasma etches a specific structure on the surface of the wafer under the action of the electric field between the upper electrode and the lower electrode. At present, the diameter of the electrostatic chuck is usually set to be slightly smaller than the diameter of the wafer, and a focusing ring is set around the electrostatic chuck to prevent the plasma from eroding the electrostatic chuck and ensure the balance of the electric field.

[0003] In actual use, the surface of the focus ring exposed to the plasma environment will also be etched by plasma. As the loss of the focus ring increases, the force of its balanced electric field gradually weakens. The degree of etching varies from place to place on the focus ring surface, which causes the degree of change in the electric field force at different places on the focus ring. The electric field at the edge of the wafer is easily distorted, resulting in uneven etching at the edge of the wafer, and even introducing other risks. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a focusing ring and a method for preparing the same in order to solve the problems existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a focusing ring, which is applied to a semiconductor etching device, wherein the semiconductor etching device includes an electrostatic chuck as a lower electrode and carrying a wafer to be processed, and an upper electrode arranged corresponding to the electrostatic chuck, wherein the focusing ring is arranged at the periphery of the electrostatic chuck, and the focusing ring includes: A first semiconductor material layer, the first semiconductor material layer comprising a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the wafer to be processed, the upper surface of the first semiconductor material layer comprising a first surface and a second surface, the first surface being perpendicular to a thickness direction of the first semiconductor material layer, and the spacing between each position of the second surface and the lower surface gradually decreases from the outside to the inside along the radial direction of the focus ring; The second semiconductor material layer is formed on the upper surface of the first semiconductor material layer through an epitaxial growth process. The crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. The second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer.

[0006] In the above technical solution, a homogeneous epitaxial layer, i.e., a second semiconductor material layer, is epitaxially grown on the upper surface of the first semiconductor material layer. At this time, the surface of the focusing ring is the surface of the second semiconductor material layer, and the crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. Then, the crystal orientation of the grains on the surface of the focusing ring is perpendicular to the surface of the focusing ring, and the grain size is the diameter of the cross section of the grain, i.e., the grains are evenly arranged and have the same grain size at various locations on the surface of the focusing ring. Thus, without changing the material of the focusing ring, the arrangement uniformity and grain size consistency of the grains on the surface of the focusing ring are improved, avoiding the problem of uneven arrangement and inconsistent grain size of grains at various locations on the surface when only the first semiconductor material layer is used as the focusing ring in the related art, thereby avoiding different etching consumption in actual use, and keeping the electric field at the edge of the wafer balanced to prevent uneven etching at the edge of the wafer.

[0007] In combination with the first aspect of the present application, in an optional implementation, the resistivity of the second semiconductor material layer is less than the resistivity of the first semiconductor material layer.

[0008] In the above technical solution, the resistivity of the second semiconductor material layer is lower than that of the first semiconductor material layer, and the conductivity of the second semiconductor material layer is better. In actual use, it is helpful to avoid the accumulation of charge on the surface of the focusing ring and reduce the risk of arcing.

[0009] In combination with the first aspect of the present application, in an optional embodiment, the thickness of the second semiconductor material layer is 5%-10% of the thickness of the focusing ring; wherein the thickness of the focusing ring is the sum of the thickness of the first semiconductor material layer and the thickness of the second semiconductor material layer, and the thickness of the first semiconductor material layer is the maximum value of the distance between the upper surface and the lower surface.

[0010] In the above technical solution, the thickness of the second semiconductor material layer is controlled to be 5%-10% of the thickness of the focusing ring. Within this range, the uniformity of grain arrangement and particle size consistency in the second semiconductor material layer are better, and the bonding with the first semiconductor material layer is better and is not easy to fall off.

[0011] In a second aspect, an embodiment of the present application provides a method for preparing a focusing ring, wherein the focusing ring is applied to a semiconductor etching device, wherein the semiconductor etching device includes an electrostatic chuck as a lower electrode and carrying a wafer to be processed, and an upper electrode arranged corresponding to the electrostatic chuck, wherein the focusing ring is arranged at the periphery of the electrostatic chuck, and the method includes: providing a substrate; Growing a layer of material to be processed on the surface of the substrate; removing the substrate; A portion of the material layer to be processed is removed from a side of the material layer to be processed facing the substrate to form a first semiconductor material layer, wherein the first semiconductor material layer is annular, comprises a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the wafer to be processed, and the upper surface of the first semiconductor material layer comprises a first surface and a second surface, wherein the first surface is perpendicular to the thickness direction of the first semiconductor material layer, and the distance between each position of the second surface and the lower surface along the radial direction of the first semiconductor material layer from the outside to the inside gradually decreases; A second semiconductor material layer is epitaxially grown on the upper surface of the first semiconductor material layer to form a focus ring, wherein the crystal orientation of grains in the second semiconductor material layer is perpendicular to the upper surface, and the second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer.

[0012] In the above technical solution, a homogeneous epitaxial layer, i.e., a second semiconductor material layer, is epitaxially grown on the upper surface of the first semiconductor material layer. At this time, the surface of the focusing ring is the surface of the second semiconductor material layer, and the crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. Then, the crystal orientation of the grains on the surface of the focusing ring is perpendicular to the surface of the focusing ring, and the grain size is the diameter of the cross section of the grain, i.e., the grains are evenly arranged and have the same grain size at various locations on the surface of the focusing ring. Without changing the material of the focusing ring, the arrangement uniformity and grain size consistency of the grains on the surface of the focusing ring are improved, avoiding the problem of uneven arrangement and inconsistent grain size of grains at various locations on the surface when only the first semiconductor material layer is used as the focusing ring in the related art, thereby avoiding different etching consumption in actual use, and keeping the electric field at the edge of the wafer balanced to prevent uneven etching at the edge of the wafer.

[0013] In combination with the second aspect of the present application, in an optional embodiment, the growth conditions for growing the material layer to be processed include a first growth temperature; the growth conditions for growing the second semiconductor material layer include a second growth temperature; wherein the second growth temperature is lower than the first growth temperature.

[0014] In the above technical scheme, the growth temperature of the second semiconductor material layer is controlled to be lower than the growth temperature of the first semiconductor material layer, so that the grain size of the grown second semiconductor material layer is smaller and the crystallinity is better, which is beneficial to ensuring the uniformity of grain arrangement and consistency of grain size at various locations on the surface of the second semiconductor material layer, and is more beneficial to resisting etching damage and maintaining electric field balance during actual use.

[0015] In combination with the second aspect of the present application, in an optional embodiment, the growth conditions for growing the material layer to be processed include a first growth pressure; the growth conditions for growing the second semiconductor material layer include a second growth pressure; wherein the second growth pressure is less than the first growth pressure.

[0016] In the above technical scheme, the growth pressure of the second semiconductor material layer is controlled to be lower than the growth pressure of the first semiconductor material layer, so that the grain size of the grown second semiconductor material layer is smaller and the crystallinity is better, which is beneficial to ensuring the uniformity of grain arrangement and consistency of grain size at various locations on the surface of the second semiconductor material layer, and is more beneficial to resisting etching damage and maintaining electric field balance during actual use.

[0017] In combination with the second aspect of the present application, in an optional embodiment, the growth conditions for growing the material layer to be processed include introducing a first doping gas; the growth conditions for growing the second semiconductor material layer include introducing a second doping gas; wherein the content of nitrogen atoms in the total doping amount of the second doping gas is greater than the content of nitrogen atoms in the total doping amount of the first doping gas.

[0018] In the above technical solution, the content of nitrogen atoms in the total doping amount of the second doping gas is controlled to be greater than the content of nitrogen atoms in the total doping amount of the first doping gas, which means that in the process of growing the second semiconductor material layer, the content of nitrogen atoms in the growth chamber is higher, and the increase in the nitrogen atom content reduces the resistivity of the grown material layer, that is, the resistivity of the second semiconductor material layer is less than that of the first semiconductor material layer, and the conductivity of the second semiconductor material layer is better. Therefore, in actual use, it is helpful to avoid the accumulation of charges on the surface of the focusing ring and reduce the risk of arcing.

[0019] In conjunction with the second aspect of the present application, in an optional implementation, the amount of the second doping gas introduced is greater than the amount of the first doping gas introduced.

[0020] In the above technical solution, the amount of doping gas introduced is increased when preparing the second semiconductor material layer, which is beneficial to increase the content of nitrogen atoms in the growth chamber, and then make the resistivity of the second semiconductor material layer smaller than the resistivity of the first semiconductor material layer, so as to avoid charge accumulation on the surface of the focusing ring and reduce the risk of arcing.

[0021] In conjunction with the second aspect of the present application, in an optional implementation, the nitrogen atomic composition of the second doping gas is greater than the nitrogen atomic composition of the first doping gas.

[0022] In the above technical solution, when growing the second semiconductor material layer, a doping gas different from that for growing the first semiconductor material layer is selected. The nitrogen atom component in the second doping gas is higher, so that the content of nitrogen atoms in the growth chamber increases, and then the resistivity of the second semiconductor material layer is made smaller than that of the first semiconductor material layer, so as to avoid charge accumulation on the surface of the focusing ring and reduce the risk of arcing.

[0023] In conjunction with the second aspect of the present application, in an optional implementation, before epitaxially growing the second semiconductor material layer on the upper surface of the first semiconductor material layer, the preparation method further includes: placing the first semiconductor material layer in a carrier, the carrier covering other surfaces of the first semiconductor material layer except the upper surface; After epitaxially growing the second semiconductor material layer on the upper surface of the first semiconductor material layer, the preparation method further includes: removing the carrier.

[0024] In the above technical solution, before epitaxial growth, the first semiconductor material layer is placed in a carrier, and the carrier covers other surfaces except the upper surface, thereby preventing the second semiconductor material layer from growing on other surfaces of the first semiconductor material layer.

[0025] The focusing ring and the preparation method thereof provided in the embodiments of the present application have at least the following beneficial effects: By epitaxially growing a homogeneous epitaxial layer, i.e., a second semiconductor material layer, on the upper surface of the first semiconductor material layer, the surface of the focusing ring is the surface of the second semiconductor material layer, and the crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface, then the crystal orientation of the grains on the surface of the focusing ring is perpendicular to the surface of the focusing ring, and the grain size is the diameter of the cross section of the grain, i.e., the arrangement of the grains on the surface of the focusing ring is uniform and the grain size is consistent. Thus, without changing the material of the focusing ring, the arrangement uniformity and grain size consistency of the grains on the surface of the focusing ring are improved, avoiding the problem of uneven arrangement and inconsistent grain size of the grains on the surface when only the first semiconductor material layer is used as the focusing ring in the related art, thereby avoiding different etching consumption in actual use, and keeping the electric field at the edge of the wafer balanced, avoiding uneven etching at the edge of the wafer; By setting the resistivity of the second semiconductor material layer to be lower than that of the first semiconductor material layer, the conductivity of the second semiconductor material layer is better, which is helpful to avoid the accumulation of charges on the surface of the focusing ring and reduce the risk of arcing in actual use; By controlling the thickness of the second semiconductor material layer to 5%-10% of the thickness of the focusing ring, within this range, the process time can be controlled to avoid affecting production efficiency. The grain arrangement uniformity and particle size consistency in the second semiconductor material layer are better, and the bonding with the first semiconductor material layer is better and less likely to fall off.

[0026] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 The figure is a schematic diagram of the installation of the focus ring and the wafer to be processed in the plasma etching chamber; Figures 2 to 3 is a schematic diagram of the cross-sectional structure of a focusing ring during the preparation process in the related art; Figure 4 for Figure 2 Electron micrograph of the structure shown; Figure 5 for Figure 4 The electron microscope image shown is a local enlarged view of the part of silicon carbide close to the graphite substrate; Figure 6 for Figure 4 The electron microscope image shown is a local enlarged view of the part of silicon carbide away from the graphite substrate; Figure 7 It is a schematic diagram of the cross-sectional structure of a focusing ring after plasma etching in the related art; Figure 8 A schematic cross-sectional structure diagram of a focusing ring provided in an optional embodiment of the present application; Fig. 9 A schematic cross-sectional structure diagram of a focusing ring provided in another optional embodiment of the present application; Fig.10 A schematic cross-sectional structure diagram of a focusing ring provided in yet another optional embodiment of the present application; Fig.11 A schematic diagram of a process for preparing a focusing ring provided in an embodiment of the present application; Figure 12 to Figure 13 A schematic diagram of the cross-sectional structure of a focusing ring during the preparation process provided in an optional embodiment of the present application.

[0028] Description of reference numerals: 1. Electrostatic chuck; 2. Wafer to be processed; 3. Focus ring; 4. Substrate; 5. Carrier; 21. Attachment; 30. Material layer to be processed; 31. First material layer; 32. First semiconductor material layer; 33. Second semiconductor material layer; 301. Step surface; 302. Lower surface; 303. Upper surface; 304. Outer surface; 305. Inner surface; 311. First step surface; 312. Second step surface; 313. Third step surface; 321. First surface; 322. Second surface; 323. Third surface; 313a. Inner side of lower step surface; 313b. Outer side of lower step surface; 401. Growth surface. DETAILED DESCRIPTION

[0029] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0030] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0031] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0032] When an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0033] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0036] Figure 1 The schematic diagram of the installation of the focusing ring and the wafer to be processed in the plasma etching chamber is shown. The plasma etching device includes an electrostatic chuck 1 as a lower electrode, which is also used to fix the wafer to be processed 2 thereon to prevent the wafer to be processed 2 from shifting during the process. The electrostatic chuck 1 can be made of metal, such as aluminum, aluminum alloy, etc. Corresponding to the electrostatic chuck 1, the plasma etching device also includes an upper electrode (not shown in the figure), and a gap is formed between the upper electrode and the electrostatic chuck 1. After conduction, an electric field is generated in the gap, and plasma etches the surface of the wafer to be processed 2 under the action of the electric field.

[0037] The electrostatic chuck 1 is usually designed as a cylindrical boss. The upper half of the cylindrical boss is close to the wafer 2 to be processed. The diameter of the cross section of the upper half of the boss is smaller than the diameter of the cross section of the lower half of the boss. The diameter of the cross section of the upper half of the boss is slightly smaller than the diameter of the wafer 2 to be processed, so as to avoid plasma erosion to the electrostatic chuck 1 and cause contamination in the etching chamber. As a result, the wafer 2 to be processed extends beyond the contact surface with the electrostatic chuck 1, and the edge of the wafer is located outside the electrostatic chuck 1, resulting in different electric fields at the edge and center of the wafer. In order to ensure the uniformity of the electric field at the edge and center of the wafer, a focusing ring 3 is usually set at the edge of the wafer in this field. Please refer to Figure 1 The focusing ring 3 is arranged on the lower boss of the electrostatic chuck 1, and surrounds the upper boss of the electrostatic chuck 1, thereby not only adjusting the uniformity of the electric field, but also preventing the lower boss of the electrostatic chuck 1 from being etched by plasma.

[0038] It should be noted that, although the embodiments of the present application are specifically described by taking a plasma etching device as an example, the semiconductor etching device in the present application does not exclude other etching devices including the electrostatic chuck 1, the upper electrode and the focusing ring 3 as described above. It should be understood that in the semiconductor etching process, the surface exposed to the etching environment is usually corroded, and the focusing ring provided in the present application can be applied to any semiconductor etching device in need.

[0039] However, the surface of the focus ring 3 exposed to the plasma environment will also be eroded by the plasma. As the use time increases, the focus ring 3 is continuously etched and consumed by the plasma and deformed, and its force on the electric field also changes. The degree of etching consumption at different parts of the focus ring 3 may be different, and its uneven deformation causes uneven changes in the electric field at the edge of the wafer, exacerbating the adverse effect on the etching effect.

[0040] Please refer to Figure 2 and Figure 3 In the related art, the focus ring is usually formed by growing a material layer 30 to be processed on a substrate 4, and then processing the material layer 30 to be processed to obtain a first material layer 31 of a preset shape. The first material layer 31 is directly used as the focus ring, and the step surface 301 of the first material layer 31 is the surface of the focus ring. The first material layer 31 is annular, and includes a lower surface 302 and a step surface 301 facing the upper electrode and the wafer 2 to be processed. The step surface 301 includes a first step surface 311 and a second step surface 312. The first step surface 311 is perpendicular to the thickness direction of the first material layer 31. The distance between each position of the second step surface 312 and the lower surface 302 along the radial direction of the first material layer 31 from the outside to the inside gradually decreases. Among them, the material layer 30 to be processed can be understood as a rectangular material layer.

[0041] The crystal orientation of the grains in the material layer 30 to be processed is the thickness direction of the material layer 30 to be processed, and the crystal orientation of the grains in the first material layer 31 obtained by processing is the thickness direction of the first material layer 31. The first step surface 311 is perpendicular to the thickness direction of the first material layer 31, and the first step surface 311 is perpendicular to the crystal orientation. In other words, the crystal orientation of the grains at the first step surface 311 is perpendicular to the first step surface 311, and the grain size of the grains at the first step surface 311 can be understood as the diameter of the cross section of the grain; while the spacing between each position from the outside to the inside along the radial direction of the first material layer 31 in the second step surface 312 and the lower surface 302 gradually decreases, and the second step surface 312 is not perpendicular to the crystal orientation. In other words, the crystal orientation of the grains at the second step surface 312 is not perpendicular to the second step surface 312, and the grain size of the grains is not the diameter of the cross section of the grains. Therefore, the arrangement and grain size of the grains displayed at the second step surface 312 are different from those of the first step surface 311.

[0042] In some focusing rings, the second step surface 312 is an inclined surface, then the grain size of the grains at the second step surface 312 can be understood as the diameter of the oblique section of the grain, which is obviously larger than the diameter of the cross section of the grain. Therefore, the grain size of the grains at the second step surface 312 is different from the grain sizes of the grains at the other two locations, and the grains at the second step surface 312 are not perpendicular to the second step surface 312, and the grains are arranged unevenly and loosely; in some other focusing rings, the second step surface 312 is a vertical surface, specifically, the direction of the second step surface 312 is the thickness direction of the first material layer 31, then the grain size of the grains in the surface layer on the second step surface 312 side can be understood as the diameter of the longitudinal section of the grain, so the same conclusion as above can be obtained.

[0043] like Figure 3 As shown, the step surface 301 of the first material layer 31 may also include a third step surface 313 , which is perpendicular to the thickness direction of the first material layer 31 , and the distance between the first step surface 311 and the lower surface 302 is different from the distance between the third step surface 313 and the lower surface 302 .

[0044] Understandably, according to crystallographic theory, during the crystal growth process, atoms will be preferentially stacked on the crystal plane with the lowest crystal plane energy, thereby obtaining a dense structure. When the material of the substrate 4 is graphite, and the material of the material layer 30 to be processed is silicon carbide, when the silicon carbide material layer is grown on the graphite substrate, the grains near the growth interface are arranged uniformly and tightly and the grain size is small. As the growth continues, the grains compete to grow, the grain size of the grains has a certain tendency to increase, and it is easy for the grains to be arranged loosely. Figures 4 to 6, shows the distribution of grains in the silicon carbide material layer at a magnification of 200 and a scale of 200μm; the silicon carbide material layer is mainly composed of columnar grains with a

[111] crystal orientation, and the grains are arranged evenly and tightly near the substrate and have a small grain size, and the grain size gradually increases in the direction away from the substrate. Therefore, the third step surface 313 is perpendicular to the thickness direction of the first material layer 31, the crystal orientation of the grains at the third step surface 313 is perpendicular to the third step surface 313, and the grain size of the grains at the third step surface 313 is also the diameter of the cross section of the grain; but since the first step surface 311 and the third step surface 313 are at different heights, the grain size and arrangement of the grains at different heights are different, which leads to different grain sizes and arrangements of the grains at the first step surface 311 and the third step surface 313.

[0045] It can be seen that in the related art, the first material layer 31 is used as the focus ring, the step surface 301 of the first material layer 31 is the surface of the focus ring, and the grains on the surface of the focus ring 3 are unevenly arranged and have inconsistent grain sizes. Figure 7 , the surface of the focus ring 3 shows different etching consumption, and the shaded part of the surface of the focus ring 3 in the figure is the etching consumption part. The etching consumption at the second step surface 312 is the largest. The uneven deformation of the surface of the focus ring 3 aggravates the distortion of the electric field and causes the problem of uneven etching at the edge of the wafer.

[0046] Based on this, the present application embodiment provides a focusing ring, please refer to Figure 1 The focusing ring is used in a semiconductor etching device. The semiconductor etching device includes an electrostatic chuck 1 as a lower electrode and carrying a wafer 2 to be processed, and an upper electrode (not shown in the figure) arranged corresponding to the electrostatic chuck 1. The focusing ring 3 is arranged on the periphery of the electrostatic chuck 1. Please refer to Figures 8 to 10 , the focus ring includes: A first semiconductor material layer 32, the first semiconductor material layer 32 includes a lower surface 302 for contacting the electrostatic chuck 1 and an upper surface 303 facing the upper electrode and the wafer to be processed, the upper surface 303 of the first semiconductor material layer 32 includes a first surface 321 and a second surface 322, the first surface 321 is perpendicular to the thickness direction of the first semiconductor material layer 32, and the distance between each position of the second surface 322 and the lower surface 302 from the outside to the inside along the radial direction of the focus ring gradually decreases; The second semiconductor material layer 33 is formed on the upper surface 303 of the first semiconductor material layer 32 by an epitaxial growth process. The crystal orientation of the grains in the second semiconductor material layer 33 is perpendicular to the upper surface 303 . The second semiconductor material layer 33 is a homoepitaxial layer of the first semiconductor material layer 32 .

[0047] It can be understood that the second semiconductor material layer 33 is formed on the upper surface 303 of the first semiconductor material layer 32 through an epitaxial growth process, so the upper surface 303 of the first semiconductor material layer 32 is the growth surface of the second semiconductor material layer 33. According to the principle of crystal growth, the grains in the second semiconductor material layer 33 are perpendicular to their respective growth surfaces, and the grain size of the grains at various locations on the surface of the second semiconductor material layer 33 is the diameter of the grain cross section. Therefore, the grains at various locations on its surface are evenly arranged and have consistent grain sizes; and the thickness of the second semiconductor material layer 33 is consistent at various locations, and the upper surface 303 of the second semiconductor material layer 33 away from the first semiconductor material layer 32 is the same shape as the upper surface 303 of the first semiconductor material layer 32, and the grains at various locations on the surface of the second semiconductor material layer 33 are basically in the same growth stage, which further ensures that the grain size is basically consistent.

[0048] The crystal orientation of the grains in the first semiconductor material layer 32 is the thickness direction of the first semiconductor material layer 32, and the first surface 321 is perpendicular to the thickness direction of the first semiconductor material layer 32. The crystal orientation of the grains at the first surface 321 is perpendicular to the first surface 321, and the grain size is the diameter of the cross section of the grain; while the distance between each position from the outside to the inside along the radial direction of the focusing ring in the second surface 322 and the lower surface 302 gradually decreases, the second surface 322 is not perpendicular to the thickness direction of the first semiconductor material layer 32, and the crystal orientation of the grains at the second surface 322 is obviously not perpendicular to the second surface 322, and the grain size is not the diameter of the cross section of the grain. Therefore, the arrangement and grain size of the grains at the first surface 321 and the second surface 322 are different. It can be seen that the arrangement uniformity and particle size consistency of the grains in the second semiconductor material layer 33 are higher than the arrangement uniformity and particle size consistency of the grains in the surface layer on the upper surface 303 side of the first semiconductor material layer 32. This also makes the surface grains of the focusing ring exposed to the plasma etching environment uniformly arranged and consistent in particle size. Therefore, in actual use, the etching consumption at various locations on the surface of the focusing ring can be kept consistent, so that the electric field at the edge of the wafer remains balanced, avoiding uneven etching at the edge of the wafer.

[0049] Alternatively, if Figure 8 and Fig. 9 As shown, the upper surface 303 of the first semiconductor material layer 32 further includes a third surface 323, the third surface 323 is perpendicular to the thickness direction of the first semiconductor material layer 32, and the distance between the third surface 323 and the first semiconductor material layer 32 is different from the distance between the first surface 321 and the first semiconductor material layer 32. It can be understood that Figure 8 and Fig. 9It is only schematically shown that the first surface 321, the second surface 322 and the third surface 323 are sequentially connected from the outside to the inside along the radial direction of the focus ring, wherein the first surface 321 faces the upper electrode, and the third surface 323 faces the upper electrode and the wafer to be processed; in some other embodiments, the first surface 321, the second surface 322 and the third surface 323 are sequentially connected from the inside to the outside along the radial direction of the focus ring, wherein the first surface 321 faces the upper electrode and the wafer to be processed, and the third surface 323 faces the upper electrode. This embodiment does not limit this.

[0050] Understandably, according to crystallographic theory, during the crystal growth process, atoms will be preferentially stacked on the crystal plane with the lowest crystal plane energy, thereby obtaining a dense structure, that is, the grain size gradually increases in the direction away from the growth surface, and the grain arrangement gradually becomes loose. Therefore, even if the third surface 323 is perpendicular to the thickness direction of the first semiconductor material layer 32, the grain size at the third surface 323 is also the cross-sectional diameter of the grain, and the grain orientation is also perpendicular to the third surface 323, but the first surface 321 and the third surface 323 are at different heights, and the grain size and arrangement of the grains at different heights are different, resulting in different grain sizes and arrangements of the grains at the first surface 321 and the third surface 323.

[0051] In an optional embodiment, the second surface 322 may be an inclined surface. Figure 8 As shown, the included angle between the second surface 322 and the first surface 321 is an obtuse angle, and the second surface 322 extends toward the direction close to the lower surface 302. Fig. 9 In another optional embodiment, the second surface 322 may be an arc surface. It is understandable that in some other embodiments, the second surface 322 may also be a vertical surface, the second surface 322 is perpendicular to the first surface 321, or in other words, the direction of the plane where the second surface 322 is located is the thickness direction of the first semiconductor material layer 32.

[0052] In yet another optional embodiment, please refer to Fig.10 The second surface 322 extends toward the direction close to the lower surface 302 until it is connected to the lower surface 302, and the second surface 322 is an inclined surface. In this optional embodiment, the longitudinal section of the first semiconductor material layer 32 is in the shape of a right-angled trapezoid. It can be understood that Fig.10 The second surface 322 is only described as an inclined surface. In some other embodiments, the second surface 322 may also be an arc surface.

[0053] It should be noted that the first semiconductor material layer 32 is an annular structure having an inner diameter and an outer diameter. Therefore, the first semiconductor material layer 32 has an outer surface 304 corresponding to the outer diameter and an inner surface 305 corresponding to the inner diameter. Of the two, the outer surface 304 of the first semiconductor material layer 32 is neither facing the upper electrode nor the wafer to be processed. Therefore, the outer surface 304 is not part of the upper surface 303. Figures 8 to 10 In the embodiment shown, the direction of the plane where the outer surface 304 is located is perpendicular to the wafer to be processed and the upper electrode, and the outer surface 304 does not belong to the upper surface 303. As for the inner surface 305 of the first semiconductor material layer 32, in some embodiments, the distance between each position of the inner surface from the outside to the inside along the radial direction of the focus ring and the lower surface 302 gradually decreases, for example Fig.10 In another optional embodiment shown, the inner surface 305 faces the wafer to be processed, and the inner surface 305 is the second surface 322; in some other embodiments, the inner surface 305 faces neither the upper electrode nor the wafer to be processed, for example Figure 8 An alternative embodiment shown or Fig. 9 In another optional embodiment shown, the inner surface 305 faces the electrostatic chuck, ie, the lower electrode, and the direction of the plane where the inner surface 305 is located is perpendicular to the wafer to be processed and the upper electrode, and the inner surface 305 does not belong to the upper surface 303 .

[0054] In some embodiments, the first semiconductor material layer 32 is a silicon carbide material layer. Since the second semiconductor material layer 33 is a homoepitaxial layer of the first semiconductor material layer 32, the second semiconductor material layer 33 is also a silicon carbide material layer. At this time, the focus ring is still a silicon carbide focus ring, and the arrangement and particle size of the grains on the surface of the focus ring can be improved without changing the material of the focus ring. In addition, the stress between the first semiconductor material layer 32 and the second semiconductor material layer 33 is small, and the bonding force is good, which effectively prevents the material layer from falling off during other processing procedures.

[0055] In this embodiment, the first semiconductor material layer 32 can be referred to as a "focus ring body", and the second semiconductor material layer 33 can be referred to as an "epitaxial layer". It can be understood that the first semiconductor material layer 32, as the main body of the focus ring, presents the basic shape of the focus ring, and is basically similar in surface shape to the first material layer 31 used as the focus ring in the related art. The present application further processes the first material layer 31 in the related art to obtain the second semiconductor material layer 33. The upper surface 303 of the second semiconductor material layer 33 away from the first semiconductor material layer 32 is the same shape as the upper surface 303 of the first semiconductor material layer 32, and the second semiconductor material layer 33 is an epitaxial layer covering the focus ring body.

[0056] Optionally, the resistivity of the second semiconductor material layer 33 is less than the resistivity of the first semiconductor material layer 32. In this embodiment, the diameter of the inner edge of the first surface 321 of the first semiconductor material layer 32 is larger than the diameter of the wafer 2 to be processed, and the diameter of the outer edge of the third surface 323 is larger than the diameter of the wafer 2 to be processed. Therefore, only a portion of the third surface 323 is covered by the wafer 2 to be processed. From the perspective of the entire focusing ring 3, as shown in FIG. Figure 7 As shown, the inner side 313a of the lower step surface of the focus ring 3 is covered by the wafer 2 to be processed, and the outer side 313b of the lower step surface of the focus ring 3 is exposed outside the wafer 2 to be processed. Therefore, when the plasma etching process is performed, the outer side 313b of the lower step surface is more easily etched, and the outer side 313b of the lower step surface shows a larger etching consumption than the inner side 313a of the lower step surface, and a larger etching groove is presented in appearance (such as Figure 7 The groove reflects the polymer produced by the plasma etching process, and the polymer gathers at the edge of the wafer to form an attachment 21. Under a high-frequency electric field, arcs are very likely to occur at the attachments 21 and the corners of the etched grooves, and once an arc occurs, the entire wafer will fail. Therefore, the resistivity of the second semiconductor material layer 33 is set to be smaller than the resistivity of the first semiconductor material layer 32, so that the conductivity of the surface of the focusing ring 3 is better. In actual use, it is helpful to avoid the accumulation of charges on the surface of the focusing ring 3, especially to avoid the accumulation of charges at the corners of the etched grooves, thereby reducing the risk of arcs.

[0057] Optionally, the resistivity of the second semiconductor material layer 33 is 8%-12% of the resistivity of the first semiconductor material layer 32. Further, the resistivity of the second semiconductor material layer 33 is 10% of the resistivity of the first semiconductor material layer 32. Thus, a better effect can be achieved. In this embodiment, the resistivity of the first semiconductor material layer 32 is 0.1Ω×cm, and the resistivity of the second semiconductor material layer 33 is 0.01Ω×cm.

[0058] In some embodiments, the thickness of the second semiconductor material layer 33 is 5%-10% of the thickness of the focus ring; wherein the thickness of the focus ring is the sum of the thickness of the first semiconductor material layer 32 and the thickness of the second semiconductor material layer 33, and the thickness of the first semiconductor material layer 32 is the maximum value of the distance between the upper surface 303 and the lower surface 302. It can be understood that if the thickness of the second semiconductor material layer 33 is too small, its bonding with the first semiconductor material layer 32 is poor, and it is easy to fall off during processing; if the thickness of the second semiconductor material layer 33 is too large, the uniformity of the arrangement of the grains and the consistency of the particle size are difficult to control. Therefore, the expected effect can be achieved within this range. In this embodiment, the thickness of the first semiconductor material layer 32 can be understood as the distance between the first surface 321 and the lower surface 302.

[0059] In this embodiment, the second semiconductor material layer 33 is a silicon carbide material layer, and the thickness of the second semiconductor material layer 33 is 0.5 mm. When the thickness of the silicon carbide material is 0.5 mm, the grain size is small and closely arranged, and the grain size has not increased.

[0060] Optionally, the particle size of the grains in the second semiconductor material layer 33 is smaller than the particle size of the grains in the first semiconductor material layer 32. As a result, the particle size of the grains on the surface of the focusing ring 3 is smaller, which can better resist plasma erosion. Specifically, the particle size of the grains in the second semiconductor material layer 33 is less than or equal to 3μm. It can be understood that the first semiconductor material layer 32 is a silicon carbide material layer. In the first semiconductor material layer 32, the particle size of the grains close to the growth surface 401 is 5μm-10μm, and the particle size of the grains away from the growth surface 401 is greater than 10μm. Controlling the particle size of the grains in the second semiconductor material layer 33 to be less than or equal to 3μm can achieve the desired effect.

[0061] The present application also provides a method for preparing the focusing ring 3. Figure 1 The focusing ring 3 is used in a semiconductor etching device. The semiconductor etching device includes an electrostatic chuck 1 as a lower electrode and carrying a wafer 2 to be processed, and an upper electrode (not shown in the figure) arranged corresponding to the electrostatic chuck 1. The focusing ring 3 is arranged on the periphery of the electrostatic chuck 1. Please refer to Fig.11 , the preparation method comprises: Step S1: providing a substrate; Step S2: growing a layer of material to be processed on the surface of the substrate; Step S3: removing the substrate; Step S4: removing a portion of the material layer to be processed from the side of the material layer to be processed facing the substrate to form a first semiconductor material layer, the first semiconductor material layer being in a ring shape, the first semiconductor material layer comprising a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the wafer to be processed, the upper surface of the first semiconductor material layer comprising a first surface and a second surface, the first surface being perpendicular to the thickness direction of the first semiconductor material layer, and the distance between each position of the second surface and the lower surface along the radial direction of the first semiconductor material layer from the outside to the inside gradually decreases; Step S5: epitaxially grow a second semiconductor material layer on the upper surface of the first semiconductor material layer to form a focus ring, wherein the crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface, and the second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer.

[0062] Thus, by epitaxially growing a homogeneous epitaxial layer, i.e., a second semiconductor material layer, on the upper surface of the first semiconductor material layer, the surface of the focusing ring is the surface of the second semiconductor material layer, and the crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. Then, the crystal orientation of the grains on the surface of the focusing ring is perpendicular to the surface of the focusing ring, and the grain size is the diameter of the cross section of the grain, i.e., the arrangement of the grains on the surface of the focusing ring is uniform and the grain size is consistent. Without changing the material of the focusing ring, the arrangement uniformity and grain size consistency of the grains on the surface of the focusing ring are improved, avoiding the problem of uneven arrangement and inconsistent grain size of the grains on the surface when only the first semiconductor material layer is used as the focusing ring in the related art, thereby avoiding different etching consumption in actual use, and keeping the electric field at the edge of the wafer balanced, avoiding uneven etching at the edge of the wafer.

[0063] First, step S1 is performed: providing a substrate 4 .

[0064] The material of the substrate 4 may include graphite or sintered silicon carbide.

[0065] Please refer to Figure 2 , perform step S2: grow a material layer 30 to be processed on the surface of the substrate 4. Optionally, the material of the material layer 30 to be processed is silicon carbide, specifically, the material layer 30 to be processed can be a polycrystalline silicon carbide solid material layer. The process of growing the material layer 30 to be processed can include a chemical vapor deposition process.

[0066] Next, step S3 is performed: removing the substrate 4 .

[0067] The process of removing the substrate 4 may be any achievable process well known to those skilled in the art, and will not be elaborated herein.

[0068] Please refer to Fig.12 , execute step S4: remove part of the material layer 30 to be processed from the side of the material layer 30 to be processed facing the substrate 4 to form a first semiconductor material layer 32, the first semiconductor material layer 32 is annular, the first semiconductor material layer 32 includes a lower surface 302 for contacting the electrostatic chuck 1 and an upper surface 303 facing the upper electrode and the wafer 2 to be processed, the upper surface 303 of the first semiconductor material layer 32 includes a first surface 321 and a second surface 322, the first surface 321 is perpendicular to the thickness direction of the first semiconductor material layer 32, and the distance between each position of the second surface 322 and the lower surface 302 along the radial direction of the first semiconductor material layer 32 from the outside to the inside gradually decreases.

[0069] The crystal orientation of the grains in the first semiconductor material layer 32 is the thickness direction of the first semiconductor material layer 32, and the first surface 321 is perpendicular to the thickness direction of the first semiconductor material layer 32. The crystal orientation of the grains at the first surface 321 is perpendicular to the first surface 321, and the grain size is the diameter of the cross section of the grain; while the distance between each position from the outside to the inside along the radial direction of the focusing ring in the second surface 322 and the lower surface 302 gradually decreases, and the second surface 322 is not perpendicular to the thickness direction of the first semiconductor material layer 32. The crystal orientation of the grains at the second surface 322 is obviously not perpendicular to the second surface 322, and the grain size is not the diameter of the cross section of the grain. Therefore, the arrangement and grain size of the grains at the first surface 321 and the second surface 322 are different.

[0070] It can be understood that according to crystallographic theory, during the crystal growth process, atoms will preferentially accumulate on the crystal plane with the lowest crystal plane energy to obtain a dense structure. Therefore, processing from the side of the material layer 30 to be processed facing the substrate 4 can make the grain size of the grains at the upper surface 303 of the first semiconductor material layer 32 smaller and more densely arranged.

[0071] Please refer to Figure 3 and Fig.12 Optionally, a portion of the material layer 30 to be processed is removed to form a first semiconductor material layer 32, including: removing a portion of the material layer 30 to be processed to form a first material layer 31, the first material layer 31 is annular, the first material layer 31 includes a lower surface 302 and a step surface 301 away from the lower surface 302, the step surface 301 includes a first step surface 311 and a second step surface 312, the first step surface 311 is perpendicular to the thickness direction of the first material layer 31, and the distance between each position of the second step surface 312 and the lower surface 302 along the radial direction of the first material layer 31 from the outside to the inside gradually decreases; remove the first material layer 31 of the first thickness to form a first semiconductor material layer 32, and the upper surface 303 is the same shape as the step surface 301.

[0072] It should be noted that Figure 2 and Figure 3 It is a schematic diagram of the cross-sectional structure of the focusing ring during the preparation process in the related technology. In the related technology, the first material layer 31 obtained by processing is directly used as the focusing ring. On this basis, the present application further processes the first material layer 31 to eliminate part of the thickness to obtain the first semiconductor material layer 32, so as to avoid the second semiconductor material layer 33 obtained by subsequent epitaxial growth from having a significant impact on the thickness of the focusing ring 3, thereby changing the distance between the focusing ring 3 and the wafer 2 to be processed. The distance between the focusing ring 3 and the wafer 2 to be processed will affect the electric field at the edge of the wafer, thereby affecting the etching effect at the edge of the wafer.

[0073] Specifically, the removal of the first material layer 31 having the first thickness may be achieved by using a CNC (Computer Numerical Control) machining center.

[0074] In some embodiments, please refer to Fig.13 Before executing step S4, the preparation method may further include: placing the first semiconductor material layer 32 in a carrier 5, wherein the carrier 5 covers other surfaces of the first semiconductor material layer 32 except the upper surface 303. Thus, the growth of material layers on other surfaces of the first semiconductor material layer 32 can be avoided.

[0075] The material of the carrier 5 may include graphite or sintered silicon carbide. Further, the material of the carrier 5 includes graphite. After the second semiconductor material layer 33 is grown, the carrier 5 needs to be removed. Graphite is easier to remove and has a lower material cost.

[0076] Please refer to the following Figure 8 , perform step S5: epitaxially grow a second semiconductor material layer 33 on the upper surface 303 of the first semiconductor material layer 32 to form a focus ring, the crystal orientation of the grains in the second semiconductor material layer 33 is perpendicular to the upper surface 303, and the second semiconductor material layer 33 is a homogeneous epitaxial layer of the first semiconductor material layer 32. At this time, the surface of the focus ring is the surface of the second semiconductor material layer 33, and the crystal orientation of the grains in the second semiconductor material layer 33 is perpendicular to the upper surface 303, then the crystal orientation of the grains at all locations on the focus ring surface is perpendicular to the focus ring surface, and the grain size is the diameter of the grain cross section, that is, the grains at all locations on the focus ring surface are evenly arranged and have the same grain size; and the thickness of the second semiconductor material layer 33 is consistent at all locations, the surface of the second semiconductor material layer 33 is the same shape as the upper surface 303 of the first semiconductor material layer 32, and the grains at all locations on the surface of the second semiconductor material layer 33 are basically in the same growth stage, which further ensures that the grain size is basically consistent.

[0077] In an optional embodiment where the first material layer 31 of the first thickness is removed, the thickness of the second semiconductor material layer 33 is equal to the first thickness. Thus, the thickness of the focus ring is kept consistent with the thickness of the first material layer 31, which is more conducive to ensuring that the distance between the focus ring 3 and the wafer 2 to be processed does not change.

[0078] In some embodiments, epitaxially growing a second semiconductor material layer 33 on the upper surface 303 of the first semiconductor material layer 32 to form the focus ring 3 may include: epitaxially growing a second semiconductor material (not shown in the figure) on the upper surface 303 of the first semiconductor material layer 32; removing the second semiconductor material of the second thickness to obtain the second semiconductor material layer 33 to form the focus ring. In this embodiment, the thickness of the second semiconductor material layer 33 is 0.5 mm, and the thickness of the second semiconductor material is greater than 1.2 mm.

[0079] Optionally, the thickness of the second semiconductor material layer 33 is 5%-10% of the thickness of the focus ring 3; wherein the thickness of the focus ring 3 is the sum of the thickness of the first semiconductor material layer 32 and the thickness of the second semiconductor material layer 33, and the thickness of the first semiconductor material layer 32 is the maximum value of the distance between the upper surface 303 and the lower surface 302. Within this range, the uniformity of grain arrangement and the consistency of grain size in the second semiconductor material layer 33 are better, and the bonding property with the first semiconductor material layer 32 is better, and it is not easy to fall off, and the process time for preparing the second semiconductor material layer 33 is controllable to avoid affecting the production efficiency. In actual preparation, the growth rate can be controlled to be reduced to obtain a second semiconductor material layer 33 with better crystal quality.

[0080] In this embodiment, the second semiconductor layer material layer is a silicon carbide material layer, and the thickness of the second semiconductor material layer 33 is 0.5 mm. When the silicon carbide material is 0.5 mm thick, the grain size is small and closely arranged, and the grain size has not changed, which is more conducive to ensuring the uniformity of grain arrangement and uniformity of grain size in the second semiconductor material layer 33.

[0081] Optionally, the particle size of the grains in the second semiconductor material layer 33 is smaller than the particle size of the grains in the first semiconductor material layer 32. As a result, the particle size of the grains on the surface of the focusing ring 3 is smaller, which can better resist plasma erosion. Specifically, the particle size of the grains in the second semiconductor material layer 33 is less than or equal to 3μm. It can be understood that the first semiconductor material layer 32 is a silicon carbide material layer. In the first semiconductor material layer 32, the particle size of the grains close to the growth surface 401 is 5μm-10μm, and the particle size of the grains away from the growth surface 401 is greater than 10μm. Controlling the particle size of the grains in the second semiconductor material layer 33 to be less than or equal to 3μm can achieve the desired effect.

[0082] The process of epitaxially growing the second semiconductor material layer 33 may include a chemical vapor deposition process.

[0083] Optionally, the growth conditions for growing the material layer to be processed include a first growth temperature; the growth conditions for growing the second semiconductor material layer include a second growth temperature; wherein the second growth temperature is lower than the first growth temperature. It can be understood that by controlling the growth temperature of the second semiconductor material layer to be lower than the growth temperature of the first semiconductor material layer, the second semiconductor material layer grows in a low temperature environment, so that the grain size of the grown second semiconductor material layer is smaller and the crystallinity is better, which is beneficial to ensure the uniformity of grain arrangement and grain size consistency at various locations on the surface of the second semiconductor material layer, and is more beneficial for the focusing ring to resist etching damage and maintain electric field balance during actual use.

[0084] Further, the difference between the second growth temperature and the first growth temperature ranges from 50°C to 100°C.

[0085] Optionally, the growth conditions for growing the material layer to be processed include a first growth pressure; the growth conditions for growing the second semiconductor material layer include a second growth pressure; wherein the second growth pressure is less than the first growth pressure. Thus, by controlling the growth pressure of the second semiconductor material layer to be less than the growth pressure of the first semiconductor material layer, the second semiconductor material layer grows under a low-pressure environment, so that the grain size of the grown second semiconductor material layer is smaller and the crystallinity is better, which is beneficial to ensuring the uniformity of grain arrangement and the consistency of grain size at various locations on the surface of the second semiconductor material layer, and is more beneficial to resisting etching damage and maintaining electric field balance in actual use.

[0086] It is understandable that the process for growing the material layer to be treated can be a normal pressure growth process, and the process for growing the second semiconductor material layer can be a low pressure growth process. It should be noted that the specific pressure ranges of normal pressure and low pressure here are generally known to those skilled in the art and will not be elaborated here.

[0087] In some embodiments, the second growth temperature is lower than the first growth temperature, and the second growth pressure is lower than the first growth pressure, so that the second semiconductor material layer grows in a low temperature and low pressure environment, and the crystal quality of the second semiconductor material layer is better, the grains are evenly arranged and the grain size is consistent.

[0088] Optionally, the growth conditions for growing the material layer to be processed include the introduction of a first doping gas; the growth conditions for growing the second semiconductor material layer include the introduction of a second doping gas; wherein the content of nitrogen atoms in the total doping amount of the second doping gas is greater than the content of nitrogen atoms in the total doping amount of the first doping gas. It can be understood that controlling the content of nitrogen atoms in the total doping amount of the second doping gas to be greater than the content of nitrogen atoms in the total doping amount of the first doping gas means that in the process of growing the second semiconductor material layer, the nitrogen atom content in the growth chamber is higher, and the increase in the nitrogen atom content reduces the resistivity of the grown material layer, that is, the resistivity of the second semiconductor material layer is less than that of the first semiconductor material layer, and the conductivity of the second semiconductor material layer is better. Therefore, in actual use, it is helpful to avoid the accumulation of charge on the surface of the focusing ring and reduce the risk of arcing.

[0089] Furthermore, the content of nitrogen atoms in the total doping amount of the second doping gas is 1.5 to 3 times the content of nitrogen atoms in the total doping amount of the first doping gas. Thus, the second semiconductor material layer with low resistivity can be better formed to achieve the expected effect.

[0090] Specifically, the amount of the second doping gas introduced is greater than the amount of the first doping gas introduced. By increasing the amount of the doping gas introduced when preparing the second semiconductor material layer, the content of nitrogen atoms in the growth chamber is increased, thereby making the resistivity of the second semiconductor material layer smaller than the resistivity of the first semiconductor material layer.

[0091] Or, specifically, the nitrogen atomic composition of the second doping gas is greater than the nitrogen atomic composition of the first doping gas. When growing the second semiconductor material layer, a doping gas different from that used to grow the first semiconductor material layer is selected, and the nitrogen atomic composition of the second doping gas is higher, so that the content of nitrogen atoms in the growth chamber increases, and then the resistivity of the second semiconductor material layer is lower than the resistivity of the first semiconductor material layer. For example, when growing the first semiconductor material layer, the doping gas is ammonia (NH3), and when growing the second semiconductor material layer, the doping gas is nitrogen (N2), which contains 2 nitrogen atoms, while ammonia has only 1 nitrogen atom, and the nitrogen atomic composition of nitrogen is higher.

[0092] In some embodiments, the amount of the second doping gas introduced is greater than that of the first doping gas, and the nitrogen atomic composition of the second doping gas is greater than that of the first doping gas, thereby achieving the desired effect better.

[0093] In an optional specific embodiment, the epitaxial growth conditions for epitaxially growing the second semiconductor material layer 33 on the upper surface 303 of the first semiconductor material layer 32 include: the growth temperature ranges from 1290°C to 1310°C; the growth pressure ranges from 195Torr to 205Torr; the flow rate of the growth precursor ranges from 4.5LPM to 5.5LPM; the flow rate of the carrier gas ranges from 29LPM to 31LPM; the flow rate of the dilution gas ranges from 4.5LPM to 5.5LPM; the flow rate of the second doping gas ranges from 4.9LPM to 5.1LPM. It can be understood that by controlling the growth conditions, the grain size, grain arrangement and resistivity of the second semiconductor material layer 33 can be adjusted.

[0094] The second semiconductor material layer 33 is a silicon carbide material layer. The growth precursor may include monomethyltrichlorosilane; the carrier gas may include hydrogen; the dilution gas may include argon; and the second doping gas may include nitrogen.

[0095] Specifically, the first semiconductor material layer 32 is a silicon carbide material layer; the growth conditions of the second semiconductor material layer 33 homoepitaxially grown on the first semiconductor material layer 32 may include: a growth temperature of 1300°C; a growth pressure of 200 Torr; a flow rate of 5 LPM of monomethyltrichlorosilane; a flow rate of 30 LPM of hydrogen; a flow rate of 5 LPM of argon; a flow rate of 5 LPM of nitrogen; and a growth rate of 30 μm / h. Thus, a second semiconductor material layer 33 with densely distributed grains, a high proportion of

[111] crystal orientation, and a resistivity of 0.01 Ω×cm can be obtained.

[0096] After executing step S4 , the preparation method may further include: removing the carrier 5 .

[0097] It should be noted that the focus ring and the embodiment of the method for preparing the focus ring provided in the present application belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the focus ring provided in the embodiment of the present application can already solve the technical problem to be solved by the present application; therefore, the focus ring provided in the embodiment of the present application may not be limited by the method for preparing the focus ring provided in the embodiment of the present application, and any focus ring prepared by the preparation method that can form the focus ring structure provided in the embodiment of the present application is within the scope of protection of the present application.

[0098] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A focusing ring, used in a semiconductor etching device, the semiconductor etching device comprising an electrostatic chuck as a lower electrode and carrying a wafer to be processed, and an upper electrode arranged corresponding to the electrostatic chuck, the focusing ring being arranged at the periphery of the electrostatic chuck, characterized in that: The focusing ring comprises: A first semiconductor material layer, the first semiconductor material layer comprising a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the wafer to be processed, the upper surface of the first semiconductor material layer comprising a first surface and a second surface, the first surface being perpendicular to a thickness direction of the first semiconductor material layer, and the spacing between each position of the second surface and the lower surface gradually decreases from the outside to the inside along the radial direction of the focus ring; The second semiconductor material layer is formed on the upper surface of the first semiconductor material layer through an epitaxial growth process. The crystal orientation of the grains in the second semiconductor material layer is perpendicular to the upper surface. The second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer.

2. The focusing ring according to claim 1, characterized in that: The resistivity of the second semiconductor material layer is lower than the resistivity of the first semiconductor material layer.

3. The focusing ring according to claim 1, characterized in that: The thickness of the second semiconductor material layer is 5%-10% of the thickness of the focusing ring; wherein the thickness of the focusing ring is the sum of the thickness of the first semiconductor material layer and the thickness of the second semiconductor material layer, and the thickness of the first semiconductor material layer is the maximum value of the distance between the upper surface and the lower surface.

4. A method for preparing a focusing ring, wherein the focusing ring is used in a semiconductor etching device, wherein the semiconductor etching device comprises an electrostatic chuck as a lower electrode and carrying a wafer to be processed, and an upper electrode arranged corresponding to the electrostatic chuck, wherein the focusing ring is arranged at the periphery of the electrostatic chuck, and wherein: The method comprises: providing a substrate; Growing a layer of material to be processed on the surface of the substrate; removing the substrate; A portion of the material layer to be processed is removed from a side of the material layer to be processed facing the substrate to form a first semiconductor material layer, wherein the first semiconductor material layer is annular, comprises a lower surface for contacting the electrostatic chuck and an upper surface facing the upper electrode and the wafer to be processed, and the upper surface of the first semiconductor material layer comprises a first surface and a second surface, wherein the first surface is perpendicular to the thickness direction of the first semiconductor material layer, and the distance between each position of the second surface and the lower surface along the radial direction of the first semiconductor material layer from the outside to the inside gradually decreases; A second semiconductor material layer is epitaxially grown on the upper surface of the first semiconductor material layer to form a focus ring, wherein the crystal orientation of grains in the second semiconductor material layer is perpendicular to the upper surface, and the second semiconductor material layer is a homoepitaxial layer of the first semiconductor material layer.

5. The method for preparing a focusing ring according to claim 4, characterized in that: The growth conditions for growing the material layer to be processed include a first growth temperature; the growth conditions for growing the second semiconductor material layer include a second growth temperature; wherein the second growth temperature is lower than the first growth temperature.

6. The method for preparing a focusing ring according to claim 4, characterized in that: The growth conditions for growing the material layer to be processed include a first growth pressure; the growth conditions for growing the second semiconductor material layer include a second growth pressure; wherein the second growth pressure is less than the first growth pressure.

7. The method for preparing a focusing ring according to claim 4, characterized in that: The growth conditions for growing the material layer to be processed include introducing a first doping gas; the growth conditions for growing the second semiconductor material layer include introducing a second doping gas; wherein the content of nitrogen atoms in the total doping amount of the second doping gas is greater than the content of nitrogen atoms in the total doping amount of the first doping gas.

8. The method for preparing a focusing ring according to claim 7, characterized in that: The amount of the second doping gas introduced is greater than the amount of the first doping gas introduced.

9. The method for preparing a focusing ring according to claim 7, characterized in that: The nitrogen atomic composition of the second doping gas is greater than the nitrogen atomic composition of the first doping gas.

10. The method for preparing a focusing ring according to claim 4, characterized in that: Before epitaxially growing the second semiconductor material layer on the upper surface of the first semiconductor material layer, the preparation method further comprises: placing the first semiconductor material layer in a carrier, the carrier covering other surfaces of the first semiconductor material layer except the upper surface; After epitaxially growing the second semiconductor material layer on the upper surface of the first semiconductor material layer, the preparation method further includes: removing the carrier.

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