Dry-type pollution-free method for patterning wafer-level two-dimensional semiconductor

Abstract

The invention discloses a method for patterning a wafer-level two-dimensional semiconductor in a dry-type pollution-free manner. The method comprises the following steps of: (1) manufacturing a latticed patterned three-dimensional seal; (2) manufacturing a metal modified latticed patterned three-dimensional seal; (3) pressing the metal-modified latticed patterned three-dimensional seal on a wafer-level two-dimensional semiconductor so as to form shape-preserving contact; and (4) separating the metal-modified latticed patterned three-dimensional seal from the wafer-level two-dimensional semiconductor, so as to obtain the dry-type pollution-free patterned wafer-level two-dimensional semiconductor. The method can be used for patterning the wafer-level two-dimensional semiconductor in a pollution-free, efficient and extensible manner.

Description

Technical Field

[0001] The invention relates to the field of semiconductors, and in particular to a method for dry, pollution-free, patterned wafer-level two-dimensional semiconductors. Background Art

[0002] Two-dimensional (2D) semiconductors, with their atomically thin thickness and dangling bond-free surfaces, have attracted great interest as channel materials for future transistors. Patterning of 2D semiconductors, which separates continuous monolayers into independent units, is essential for electrically isolating 2D semiconductors and further connecting them into complex integrated circuits. However, current 2D patterning techniques largely follow silicon-based methods, using photolithography as a mask and then using plasma (or reactive ions) to etch away unwanted 2D materials. During this process, photoresist residues are inevitably left on the 2D surface after photoresist removal, resulting in large device-to-device variability in 2D transistors. More importantly, randomly distributed polymer residues also exist in the metal contact area, resulting in non-uniform contact resistance and contact barrier, further amplifying the device-to-device variability and degrading their electrical performance. Since 2D materials have a single atomic layer thickness, 2D transistors are essentially "all-surface devices" whose overall device performance depends not only on their intrinsic properties but also, to a large extent, on their surface properties. Therefore, even a small amount of polymer residues (caused during the patterning process) can act as scattering or doping centers, reducing the uniformity and yield of wafer-scale devices.

[0003] In order to avoid polymer residues in traditional patterning processes and improve the uniformity of devices, people are committed to developing dry patterning processes. In other dry patterning processes, the two-dimensional monolayer is patterned (or cut) by pure mechanical force or thermomechanical indentation. The patterning process does not directly contact any polymer, so the patterned area presents a residue-free atomically clean surface. Similarly, lasers can also directly remove unwanted two-dimensional materials through simple local thermal effects, thereby achieving a lithography-free process and a residue-free two-dimensional surface. However, these methods are based on the slow movement of the probe tip or the laser spot, which is time-consuming and cannot be further expanded in size. In addition, the laser cutting process may cause local temperature increases, so that the edges may become oxidized.

[0004] In existing technologies, wafer-level patterning requires the use of photoresist as a mask. Currently, there is no method that can perform large-scale batch patterning of two-dimensional semiconductors without using a photoresist mask. Therefore, the development of a polymer-free, efficient and scalable wafer-level two-dimensional semiconductor patterning technology is crucial for its practical application. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and to provide a method for dry patterning wafer-level two-dimensional semiconductors, which can pattern wafer-level two-dimensional semiconductors in a pollution-free, efficient and scalable manner.

[0006] The technical problem solved by the present invention adopts the following technical solution:

[0007] A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors, comprising:

[0008] Step (1) making a grid-shaped patterned three-dimensional seal;

[0009] Step (2) making a metal-modified grid-shaped patterned three-dimensional stamp;

[0010] Step (3) pressing the metal-modified grid-shaped patterned three-dimensional stamp onto a wafer-level two-dimensional semiconductor to form a conformal contact;

[0011] Step (4) separates the metal-modified grid-shaped patterned three-dimensional stamp from the wafer-level two-dimensional semiconductor, thereby obtaining a dry, pollution-free, patterned wafer-level two-dimensional semiconductor.

[0012] When the metal-modified grid-shaped patterned 3D stamp is lifted, the 2D semiconductor in the contact area (the protruding area of ​​the stamp) will be taken away due to the strong interaction between the grid-shaped metal and the 2D semiconductor, while the 2D semiconductor material in the non-contact area (the recessed area of ​​the stamp) will remain on the original substrate. At this time, the patterning of the wafer-level 2D semiconductor is successfully completed through this metal-modified grid-shaped patterned 3D stamp. During the whole process, the 2D semiconductor retained on the original substrate does not contact any polymer or solution, realizing truly scalable dry and pollution-free patterning.

[0013] Furthermore, the step (1) of making a grid-shaped patterned three-dimensional stamp comprises: spin coating photoresist on a sacrificial substrate and preparing a grid-shaped patterned mold by a standard photolithography method, and making the grid-shaped patterned three-dimensional stamp by a reverse molding process.

[0014] Furthermore, the grid-like patterned shape is an orderly arrangement of a single figure or a combination of different figures.

[0015] Furthermore, the step (2) of making the metal-modified grid-shaped patterned three-dimensional stamp is: evaporating a metal film on the grid-shaped patterned three-dimensional stamp of the step (1). The metal film can increase the adhesion between the grid-shaped patterned three-dimensional stamp and the wafer-level two-dimensional semiconductor.

[0016] Furthermore, the step (3) of pressing the metal-modified grid-shaped patterned three-dimensional stamp onto the wafer-level two-dimensional semiconductor to form conformal contact is as follows: the metal-modified grid-shaped patterned three-dimensional stamp is bonded to the top of the wafer-level two-dimensional semiconductor, slowly pressed, and annealed at a low temperature, so that the metal-modified grid-shaped patterned three-dimensional stamp forms conformal contact with the wafer-level two-dimensional semiconductor.

[0017] Furthermore, in the step (3), the low temperature annealing treatment time is 3-10 minutes, and the temperature is 130° C.-150° C. The low temperature annealing treatment is to remove bubbles at the contact interface between the metal-modified grid-shaped patterned three-dimensional stamp and the top of the two-dimensional semiconductor, so that the metal-modified grid-shaped patterned three-dimensional stamp and the two-dimensional semiconductor form a close contact.

[0018] Furthermore, the three-dimensional stamp is polydimethylsiloxane (PDMS).

[0019] Furthermore, in step (2), the metal is a layer of adhesive metal and a layer of functional metal, the thickness of the adhesive metal is 5-10nm, and the thickness of the functional metal is 20-50nm; the rate of metal deposition is To ensure that a dense metal film is formed and the stamp will not wrinkle or deform.

[0020] Furthermore, the adhesive metal is Ti or Cr; and the functional metal is Au or Ag or Pd.

[0021] Furthermore, in the step (3), the two-dimensional semiconductor is fixed with an adhesive tape before pressing to ensure the subsequent rapid separation of the metal-modified grid-shaped patterned three-dimensional stamp and the two-dimensional semiconductor.

[0022] Furthermore, the height difference between the concave and convex parts of the patterned three-dimensional stamp needs to be greater than 5 μm to ensure that the concave part of the patterned three-dimensional stamp cannot contact the two-dimensional semiconductor at the bottom during contact. Only in this way can it be ensured to remain on the original substrate.

[0023] The beneficial effects of the present invention are as follows:

[0024] (1) The present invention demonstrates rapid wafer-level dry patterning of two-dimensional semiconductors by three-dimensional metal stamps.

[0025] (2) The two-dimensional array produced by the method of the present invention has an atomically flat surface and clean, uncontaminated edges, which is conducive to forming better electrical contact.

[0026] (3) The method of the present invention is scalable and can realize the etching of any customized pattern, such as circle, square, triangle, letter, etc.

[0027] (4) A great advantage of the present invention is that the dry patterning process does not involve any polymer or solution, thereby maintaining the inherent characteristics of the fine two-dimensional lattice.

[0028] (5) The method of the present invention has wide applicability and can be applied to common two-dimensional layered semiconductors such as MoS2, WSe2, MoSe2, and MoTe2.

[0029] (6) The method of the present invention is highly scalable and can be further extended to larger wafers, such as 8-inch or 12-inch or even larger 2D semiconductor patterning, with the size only depending on the CVD

[0030] The size of the growing material. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the process of preparing a metal-modified grid-shaped patterned three-dimensional stamp in a dry pollution-free patterned wafer-level two-dimensional semiconductor method in Example 1 of the present invention;

[0032] Figure 2 A schematic diagram of the process of conformal contact and separation between a metal-modified grid-shaped patterned three-dimensional stamp and a two-dimensional semiconductor in a dry non-polluting patterned wafer-level two-dimensional semiconductor method in Example 1 of the present invention, and a corresponding optical diagram;

[0033] Figure 3 These are atomic force microscope images and optical images of patterned two-dimensional semiconductors of different shapes in a dry, contamination-free patterned wafer-level two-dimensional semiconductor method in Example 1 of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, method and advantage of the present invention clearer, the technical scheme of the present invention will be completely and clearly described in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only part of the embodiments of the present invention, which are used to explain the present invention and are not used to limit all the embodiments of the present invention. It should be noted that the embodiments of the present invention and the features in the embodiments can be used in combination with each other without conflict. In addition, in all embodiments based on the present invention, all other embodiments obtained without the technical personnel in the field of technology making creative techniques belong to the scope of protection of the present invention.

[0035] Example 1

[0036] The method flow of Example 1 of the present invention is shown in the attached Figure 1 With attached Figure 2The two-dimensional semiconductor in the present invention is a two-dimensional layered semiconductor such as MoS2, WSe2, MoSe2, etc., which is a common chemical vapor deposition (CVD) wafer-level semiconductor. In this embodiment 1, the two-dimensional semiconductor is MoS2. The specific preparation method of this embodiment 1 includes the following steps:

[0037] Step (1) making a grid-shaped patterned three-dimensional seal;

[0038] 1.1 Spin-coat a layer of photoresist (SU8, 5 μm thick) on the sacrificial substrate (see Appendix Figure 1 a), a grid pattern is made by standard photolithography technology, the mold surface is properly cleaned with plasma after development, and treated with hexamethyldisilazane (HMDS). Through the above process, a grid-shaped three-dimensional stamp mold can be prepared (see Appendix Figure 1 b).

[0039] 1.2 PDMS elastomer (Sylgard 184, Dow Corning) was poured onto the mold, baked at 80 °C for 6 h, and then peeled off from the mold to form a grid-like patterned three-dimensional PDMS stamp (see Appendix Figure 1 c).

[0040] 1.3 The back of the grid-shaped patterned three-dimensional PDMS stamp was treated with oxygen plasma (power 100 W, time 10 s), and after the treatment, the back of the grid-shaped patterned three-dimensional PDMS stamp was attached to a hard quartz substrate.

[0041] The front side of the grid-patterned 3D PDMS stamp has an atomically flat surface because it replicates the surface flatness of the sacrificial substrate.

[0042] Step (2) making a metal-modified grid-shaped patterned three-dimensional stamp;

[0043] By high vacuum electron beam evaporation (speed ) first deposited a layer of chromium (10 nm thick) on the grid-shaped patterned 3D stamp, and then evaporation was performed by high vacuum electron beam evaporation (at a speed of ) A gold film (30 nm thick) is deposited on the chromium. The above process can produce a metal-modified grid-shaped patterned three-dimensional stamp for the next step of patterning. It should be noted that in order to ensure the cleanliness of the metal interface and avoid the adsorption of organic pollutants on the stamp surface, the subsequent step of patterning the two-dimensional semiconductor needs to be carried out within a few minutes after the metal film is evaporated (see Appendix Figure 1 d).

[0044] Step (3) pressing the metal-modified patterned three-dimensional stamp onto a wafer-level two-dimensional semiconductor to form a conformal contact;

[0045] First, fix the two-dimensional semiconductor with sticky tape, then transfer the metal-modified grid-shaped patterned three-dimensional stamp to the surface of the two-dimensional semiconductor MoS2, slowly press it to make it close contact, and then anneal it at 130°C for 3 minutes to make the gold and the two-dimensional semiconductor MoS2 more closely combined (see Appendix Figure 2 ab).

[0046] Step (4) separates the metal-modified grid-shaped patterned three-dimensional stamp from the two-dimensional semiconductor, thereby obtaining a dry, pollution-free, patterned wafer-level two-dimensional semiconductor.

[0047] The metal-modified grid-shaped patterned three-dimensional stamp is slowly lifted up to separate it from the two-dimensional semiconductor. When the three-dimensional stamp leaves the two-dimensional semiconductor wafer, the two-dimensional semiconductor in the contact area (convex area) is also picked up and taken away. Since the three-dimensional stamp has a patterned concave area, which is not in contact with the two-dimensional semiconductor, the area not in contact with the three-dimensional stamp (concave area) is retained on the substrate (see FIG. Figure 2 c). At this point, the 3D stamp has completed the dry and pollution-free patterning of the 2D semiconductor.

[0048] From the attached Figure 2 c It can be seen that after the three-dimensional stamp contacts, the stamp takes away the material in the contact area (to be etched), and the continuous two-dimensional film becomes a discrete two-dimensional array, retaining the material in the non-contact area, thereby replicating the pattern defined by the stamp. The two-dimensional semiconductor patterned by the three-dimensional gold stamp was further observed by AFM, and it can be seen that the patterned two-dimensional semiconductor has an atomically flat surface with a roughness of 0.28nm (see Appendix Figure 3 a, 3b), the edges are clear, and there is no polymer residue, which shows that the gold seal dry patterning technology can achieve pollution-free etching, and there is no glue contamination, retaining the intrinsic two-dimensional lattice structure.

[0049] The technical solution of the present invention can be used to design different patterns, and any pattern can be defined by traditional photolithography, such as squares, circles, triangles or letters (see the attached Figure 3 cf).

[0050] In summary, the present invention explores a method that can achieve dry patterning of wafer-level two-dimensional semiconductors. This method realizes patterning without polymer contact. The pattern obtained by this method has an atomically flat surface and clear edges, realizing fast, pollution-free and scalable wafer-level patterning.

[0051] The protection scope of the present invention is not limited to the above-mentioned examples. In the above description, the details that need attention are explained in order to better understand the invention. However, this is only a better example of the present invention. The present invention can be implemented in many other ways different from the above descriptions, so the present invention is not limited by the specific implementation disclosed above. At the same time, any technician familiar with the field can make some possible changes and modifications to the present invention using the methods and technical means disclosed above without actually departing from the limitations of the scheme of the present invention. All simple changes and equivalent modifications made to the above examples based on the technical essence of the present invention that do not depart from the content of the technical scheme of the present invention are still within the scope of protection of the technical scheme of the present invention.

Claims

1. A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors, characterized in that: include: Step (1) making a grid-shaped patterned three-dimensional seal; Step (2) making a metal-modified grid-shaped patterned three-dimensional stamp; Step (3) pressing the metal-modified grid-shaped patterned three-dimensional stamp onto a wafer-level two-dimensional semiconductor to form a conformal contact; Step (4) separates the metal-modified grid-shaped patterned three-dimensional stamp from the wafer-level two-dimensional semiconductor, thereby obtaining a dry, pollution-free, patterned wafer-level two-dimensional semiconductor.

2. A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors as claimed in claim 1, characterized in that: The grid-like patterned shape is an orderly arrangement of a single figure or a combination of different figures.

3. A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors as claimed in claim 1, characterized in that: The step (2) of making the metal-modified grid-shaped patterned three-dimensional stamp comprises: vapor-depositing a metal film on the grid-shaped patterned three-dimensional stamp of the step (1).

4. A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors as claimed in claim 1, characterized in that: The step (3) of pressing the metal-modified grid-shaped patterned three-dimensional stamp onto the wafer-level two-dimensional semiconductor to form conformal contact is as follows: the metal-modified grid-shaped patterned three-dimensional stamp is bonded to the top of the wafer-level two-dimensional semiconductor, slowly pressed, and annealed at a low temperature, so that the metal-modified grid-shaped patterned three-dimensional stamp forms conformal contact with the wafer-level two-dimensional semiconductor.

5. A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors as claimed in claim 4, characterized in that: In the step (3), the low temperature annealing treatment time is 3-10 minutes, and the temperature is 130°C-150°C.

6. A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors as claimed in claim 1, characterized in that: The three-dimensional stamp is polydimethylsiloxane (PDMS).

7. A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors as claimed in claim 1, characterized in that: In the step (2), the metal is a layer of adhesive metal and a layer of functional metal, the thickness of the adhesive metal is 5-10 nm, and the thickness of the functional metal is 20-50 nm.

8. A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors as claimed in claim 7, characterized in that: The adhesive metal is Ti or Cr; the functional metal is Au or Ag or Pd.

9. A method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors as claimed in claim 1, characterized in that: In the step (3), the two-dimensional semiconductor is fixed with an adhesive tape before pressing.

10. The method for dry, pollution-free patterning of wafer-level two-dimensional semiconductors according to claim 1, characterized in that: The height difference of the patterned three-dimensional stamp should be greater than 5 μm.

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