Side solderable leadless package

Abstract

The lead frame is formed by chemically half-etching a sheet of conductive material. The semi-etch exposes a first side surface of a first contact of the lead frame. A solder wettable layer is plated on the first side surface of the first contact. After plating the solder wettable layer, an encapsulant is deposited on the lead frame.

Description

[0001] This application is a divisional application of the invention patent application with application number 201810903525.4, application date August 9, 2018, and titled "Side-weldable leadless package".

[0002] Claiming priority

[0003] This application claims the benefit of U.S. Provisional Application No. 62 / 543,211, filed on August 9, 2017, which is incorporated herein by reference. Technical Field

[0004] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of forming side-solderable leadless packages (SLPs). Background Art

[0005] Semiconductor devices are common in modern electronic products. Semiconductor devices differ in the number and density of electrical components. Semiconductor devices perform a wide range of functions, such as analog and digital signal processing, sensors, sending and receiving electromagnetic signals, controlling electronic devices, power management, and audio / video signal processing. Discrete semiconductor devices typically contain one type of electrical component, such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, a diode, a rectifier, a thyristor, and a power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, application specific integrated circuits (ASICs), power conversion, standard logic, amplifiers, clock management, memory, interface circuits, and other signal processing circuits.

[0006] Quad flat no-lead (QFN) or dual flat no-lead (DFN) packages are becoming popular as competition for smaller devices benefits from packages that do not have leads extending from the package. Leadless packages typically have exposed contacts rather than leads extending from the sides or bottom of the encapsulant, the contacts being coplanar with or recessed within the surface of the encapsulant.

[0007] The leadless package is mounted to the substrate by reflowing solder between the contact pads on the substrate and the lead frame contacts. Manufacturers expect the contacts of the leadless package to have side solderable surfaces. The side solderable surfaces of the leadless package cause the reflowed solder to form a fillet between the side solderable surface and the substrate. The solder chamfer is useful for manufacturers of electronic devices because the proper interconnection between the package and the substrate can be visually verified by a person or by an automatic visual inspection device. If the visual inspection shows that one of the package contacts does not form a proper chamfer, an error is recorded. The device with the wrong connection can be repaired or discarded.

[0008] However, forming a solder chamfer for visual inspection relies on the side surfaces of the package contacts being wettable by solder. In order to facilitate the reflow of solder onto the side surfaces of the contacts, the manufacture of leadless packages will typically plate the contacts with a wettable material as part of the packaging process. Metal plating is typically achieved using various electroplating or electroless deposition methods. Electroplating is a more desirable plating method because thicker and faster metal deposition occurs. The thicker metal layer provided by electroplating provides a more reliable solder chamfer, especially after the parts have been left for a considerable period of time before soldering.

[0009] One plating method involves using a saw to cut only a portion of the leads that pass through the board of the device after the package is encapsulated. Cutting to a depth of about halfway through the contact of the package gives the contact a stepped appearance, which may be referred to as a step cut. The leads of adjacent devices remain electrically connected to each other through the uncut portion to pass current for plating. Step cutting with a saw blade and then plating creates additional manufacturing work and cost, which would be advantageous to eliminate.

[0010] Therefore, a need exists for a lead frame design that allows for the plating of the side surfaces of contacts without the need for step cutting and plating as part of the packaging process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1a-1h The process of forming SLP is shown;

[0012] Figure 2a and 2b A lead frame and SLP with straight leads are shown;

[0013] Figure 3a and 3b shows a lead frame and SLP with additional support structures; and

[0014] Figure 4a and 4b A side solderable package mounted on a PCB is shown. DETAILED DESCRIPTION

[0015] One or more embodiments are described below with reference to the accompanying drawings, in which like numerals represent the same or similar elements. Although the drawings are described according to the best mode for achieving certain objectives, the description is intended to cover alternatives, modifications, and equivalents as may be included in the spirit and scope of the present disclosure. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0016] Figure 1a A sheet of conductive base material 10 for forming a lead frame is shown. The base material is typically copper, but in other embodiments aluminum, gold, iron, nickel, combinations and alloys thereof, or other suitable lead frame materials are used. The sheet 10 is formed from a raw material by rolling, pressing, molding, or any other suitable means for forming a sheet having substantially planar top and bottom surfaces substantially parallel to each other. In one embodiment, a pre-plated frame (PPF) is used for the sheet 10. The PPF can be a sheet of copper in which the top and bottom surfaces are plated with one or more layers of other metals, such as tin, nickel, gold, or palladium. The sheet 10 comprises a uniform thickness in which the length and width are configured as desired for the number of semiconductor devices formed in a single board.

[0017] The lead frame is formed from the sheet 10 by performing chemical etching on the top and bottom surfaces of the sheet. The chemical etching is performed using a photolithography process. Each chemical etch is performed approximately halfway through the sheet 10, referred to as a half etch. A photomask layer is used to control which areas are etched from each side. The areas of the sheet 10 that are half-etched from both the bottom and top surfaces are completely etched through the sheet and become openings through the sheet. Areas that are half-etched from only one side or the other retain approximately half the thickness of the original sheet 10, and areas that are masked for both etching steps retain full thickness. In other embodiments, other half-etching mechanisms are used.

[0018] exist Figure 1a , bottom surface 12 is oriented upward toward the viewer because that is the side of the lead frame that is half-etched first in this embodiment. In other embodiments, the top of the lead frame is half-etched first. In many embodiments, the designation of a side of sheet 10 as top or bottom is arbitrary. Prior to etching, there is typically no difference between the top and bottom. Figure 1a The sheet 10 in will result in a view substantially the same as that shown.

[0019] Figure 1b Sheet 10 is shown after bottom surface 12 has been half-etched, but before top surface 12 has been etched. The half-etched area of ​​sheet 10 forms surface 20 that is oriented in substantially the same direction as bottom surface 12, but at a reduced height. The half-etch does not extend completely through sheet 10. Figure 1b Flipping sheet 10 at the stage shown in FIG. 1 still results in substantially the same view as in FIG. 1 , since the half-etch does not extend to the top surface.

[0020] Figure 1bThe half etching in is configured to form a three by three array of devices from the lead frame. Region 20a is half etched between the devices, and region 20b is half etched in the middle of each device. In other embodiments, hundreds or thousands of devices are formed from a single lead frame. Each device segment includes a pair of contacts 28, with region 20b between the two contacts of the device. The body of each contact 28 is not etched from the bottom surface 12 and remains at the full thickness of the sheet 10. Each contact 28 includes a side surface 30 that will be exposed and weldable in the final device. The side surface 30 is exposed by etching of region 20a. One contact 28 of each of the devices includes a notch 34 oriented toward the inside of the device to identify which of the contacts is pin one.

[0021] Each device includes a centrally located space above surface 20b and between contacts 28 that will be filled with encapsulant during device formation. Optionally, a dam 40 is formed around surface 20b to keep the encapsulant contained within the central region of each device. Dam 40 increases the structural integrity of the lead frame by physically coupling rows of devices to adjacent rows and also reduces the likelihood of encapsulant flowing out and covering side surfaces 30. The encapsulant is preferably contained only within the lead frame. Figure 1b 20a. Thus, the side surfaces 30 of the contacts 28 remain exposed from the encapsulant for subsequent solder connections. In some embodiments, ridges 42 are formed around the lead frame to block the encapsulant from invading through the sides of the lead frame and covering the side surfaces 30. Ridges 42 are not required in embodiments where other measures are taken to seal the perimeter of the lead frame from the encapsulant.

[0022] Support structures 46 are formed in the space between the devices for physical support during encapsulation. During the encapsulation process, the space below surface 20a adjacent to side surface 30 is substantially isolated, which may cause significant pressure to be applied to those areas of the lead frame. Support structures 46 act as pillars to support the lead frame, particularly surface 20a, against the pressure of the molding process.

[0023] The support structure 46 helps maintain the structural integrity of the lead frame during encapsulation. In addition, the support structure 46 is shaped as a cross or other shape to act as a reference mark. The support structure 46 is formed in the saw road between the units, so the specific shape of the support structure is generally irrelevant to the final device. The cross-shaped support structure 46 can extend to each other parallel to the rows of the device, and to the side surface 30 in a vertical direction. In other embodiments, the support structure 46 is circular or any other suitable shape for the pillar. Coding can be achieved by changing the shape of the support structure 46. The coding can then be used to locate specific rows and columns within the frame.

[0024] Side surface 30 is the side solderable surface upon which the final device will depend to produce a good solder chamfer. Figure 1b In the steps shown in FIG. 1 , the side surface is exposed. Figure 1b The structure shown in can be electroplated with a solder wettable layer, and the plating will remain in the final device and provide solder wettable contact flanks. In other embodiments, plating occurs at a later stage.

[0025] Contacts 28, dams 40, ridges 42, and support structures 46 are formed by forming a mask layer over those areas of bottom surface 12. The mask layer is removed over surfaces 20a and 20b and is retained in the shape of the full thickness area. Etching removes substrate material to reduce the substrate thickness in the areas of surfaces 20a and 20b, while the mask protects contacts 28, etc. from chemical etchants. The mask is removed after etching.

[0026] exist Figure 1c In the embodiment of the present invention, the sheet 10 is turned over so that the top surface 52 is oriented upward. The top surface 52 is generally the same as the bottom surface 20 of the sheet 10 before etching, but on the opposite side of the sheet. Figure 1c , top surface 52 is half-etched in substantially the same manner as bottom surface 20 to form openings 56 and recesses 58, but in a different pattern. Openings 56 are formed by half-etching surface 20b from the opposite side of sheet 10, which results in those locations being completely etched through the sheet. Surface 20a is not etched from rear surface 52, so surface 20a remains intact. The partially protected side surfaces 30 of sheet 10 that form surface 20a are not covered in encapsulant during packaging. Notches 34 can be etched from both sides, but are shown as being etched only from bottom surface 12. Having notches 34 that do not extend to top surface 52 increases the surface area of ​​the top surface for mounting the semiconductor die to the lead frame, and increases mold lock to contacts 28 when notches 34 are filled with encapsulant.

[0027] Recesses 58 are half-etched through top surface 52 within contact 28. Recesses 58 extend only partially through sheet 10. Encapsulant fills recesses 58 to increase mold lock, i.e., the grip of the encapsulant on contact 28. Increased mold lock reduces the likelihood that contact 28 will separate from the encapsulant. Any number and shape of recesses 58 may be formed in any suitable location, as appropriate. Recesses 58 may be multiple circles, such as Figure 1c In other embodiments, the depressions 58 are formed as depressions that extend across the entire top surface of the contact 28. In another embodiment, the depressions 58 are each elongated across a plurality of contacts 28, or are formed in any other desired shape.

[0028] Once the sheet 10 is half-etched on both the top surface 52 and the bottom surface 12, the sheet has been manufactured into a complete lead frame 60. The lead frame 60 can be plated at this stage of the manufacturing process because the side surface 30 to be plated with a wettable material is exposed. During the packaging process, the bar 40 will prevent the side surface 30 from being subsequently covered by an encapsulant. The plating applied to the lead frame 60 can include tin, palladium, nickel, gold, solder, another conductive material or a combination thereof. In one embodiment, three separate layers of palladium, nickel and gold are plated on the lead frame 60, respectively. The side surface 30 is covered in the plating material, which produces a contact 28 with a side solderable surface.

[0029] Semiconductor packaging companies typically order lead frame components from lead frame manufacturers. Figure 1c The lead frame is delivered in the state shown in FIG, where half etching and plating have been performed. Then, the semiconductor packaging company packages the semiconductor die in a Figure 1d-1h The side surface plating is performed on the lead frame shown. Performing the side surface plating by the lead frame manufacturer reduces the amount of work that the semiconductor packaging company must perform. The semiconductor packaging company does not have to perform sawing and plating steps as part of the packaging process in order to plate the side surfaces of the leads. In some cases, the same entity manufactures the lead frame, plates the lead frame, and then uses the lead frame to form a semiconductor package. In other cases, the semiconductor packaging company rather than the lead frame manufacturer performs the plating, but the process is still made easier by not having to perform step cutting before plating in order to obtain contacts with wettable flanks. The steps shown above and below can be performed by any combination of commercially suitable entities.

[0030] exist Figure 1d , a lead frame 60 is placed on a carrier 62, and a semiconductor die 64 is disposed on each pair of contacts 28. In some embodiments, the top surface of the carrier 62 includes a double-sided tape, a thermal release layer, an ultraviolet release layer, an adhesive layer, or another suitable interface layer to hold the lead frame 60 on the carrier 62 while also allowing for later release. The semiconductor die 64 includes contact pads 66 formed on the semiconductor die that are electrically connected and mechanically bonded to the contacts 28 of the lead frame 60 by soldering or other suitable means. The semiconductor die 64 is a two-terminal device, such as a transient voltage suppressor diode.

[0031] exist Figure 1eIn the embodiment of the present invention, an encapsulant or molding compound 70 is deposited on the substrate 60 and the semiconductor die 64 using slurry printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating or other suitable coating means. The encapsulant 70 can be a polymer composite material, such as epoxy resin, epoxy acrylate or any suitable polymer with or without filler. In other embodiments, any suitable molding compound is used for the encapsulant 70. The encapsulant 70 is non-conductive and protects the semiconductor device from external elements and pollutants in the environment. The encapsulant 70 also protects the semiconductor die 64 from degradation due to exposure to light. The semiconductor die 64 and the lead frame 60 with the encapsulant 70 form a board 74 of an unsingulated device.

[0032] Encapsulant 70 extends to the edge of carrier 62 to completely cover the top and sides of leadframe 60, including flowing through openings 56. However, encapsulant does not flow over side surfaces 30 of contacts 28. Bars 40 and ridges 42 block encapsulant from entering the void in leadframe 60 above surface 20a in which side surfaces 30 and support structure 46 are positioned.

[0033] Figure 1f A flipped board 74 is shown with the carrier 62 removed so that the leadframe 60 is visible. Encapsulant 70 has been filled in the openings 56 located below each semiconductor die 64. The side surfaces 30 of the contacts 28, including the plating applied at the leadframe manufacturer, remain exposed from the encapsulant. During the molding process, the dam 40 keeps the encapsulant 70 contained within the openings 56. For example, if the leadframe manufacturer does not perform plating, the leadframe 60 can still be plated after encapsulation if desired without having to saw through the contacts 28. The side surfaces 30 remain exposed and are each electrically connected through the leadframe 60 to allow electroplating to occur.

[0034] exist Figure 1g In the embodiment of the present invention, a saw blade, a laser cutting tool, a water jet cutting tool or another suitable means is used to singulate the board 74 through the saw streets 76 to form a plurality of individual SLPs 80. The singulation process removes the bars 40 to electrically isolate the contacts 28 of each device from each other. The support structures 46 and the ridges 42 are also removed during singulation. Although in Figure 1g Only a single SLP 80 is shown being separated from board 74 , but each saw street 76 is typically cut along the entire length and width of the board to separate each semiconductor die 64 into its own SLP.

[0035] Figure 1hThe SLP 80 after singulation is shown. Each contact 28 includes a plated side surface 30 that allows solder to reflow along the side surface. The side surface 30 is bent in a "U" shape, forming a spread-out chamfer that extends from the contact 28 in three directions and is easier to see with automated equipment. The side surface 30 is plated without the need to saw through the lead frame 60 prior to plating. An etching process is used to expose the side surface 30, which is more precise and less prone to problems such as copper burrs, copper tailing, and delamination than the sawing process used in the prior art.

[0036] Plating can be performed before or after deposition of encapsulant 70. In some embodiments, plating is performed by the lead frame manufacturer, which can reduce packaging time. SLP 80 is a substantially symmetrical semiconductor package in which notches 34 remain exposed from the encapsulant to indicate the polarity of the device, e.g., which terminal is pin one. Singulation of plate 74 occurs through recesses 58, so the recesses are visible at the sides of the package.

[0037] Figure 2a and 2b A second embodiment of forming a SLP is shown. Figure 2a Sheet 100 is shown, which begins with a sheet of conductive material substantially similar to sheet 10. Sheet 100 has a top surface 112 that is half-etched to be in contact with Figure 1b The sheet 100 includes two contacts 128 for each device. The contact 128 includes a side weldable surface 130 that is straight rather than U-shaped as in the first embodiment. One contact 128 for each device includes a notch 134. The notch 134 is formed at the corner of the contact 128 and is aligned with the contact 128. Figure 1b The notch 34 in the center of the contact is different. Both the notch 34 and the notch 134 can be formed at the corner, middle or any other position of their corresponding contact. The space 140 is optionally formed on the side of the contact 128. The space 140 allows the encapsulant to flow around the three side surfaces of the contact 128 to improve mold locking. In some embodiments, a bar 40 is used between each unit to help contain the encapsulant. The bar 40 can separate or replace the space 140.

[0038] Similar to Figure 1c , the sheet 100 is flipped over and half-etched on the opposite side, and then plated to complete the lead frame. The semiconductor die 64 is later placed on the contacts 128 and packaged as a board. Figure 2bA complete SLP 180 is shown with straight side solderable surfaces 130. The side solderable surfaces 130 are plated without having to be sawed through because the encapsulant 170 does not intrude into the space between adjacent side surfaces 130. The side solderable surfaces 130 can be plated by the lead frame manufacturer because manufacturing a package with a lead frame is accomplished without covering the side surfaces.

[0039] Figure 3a and 3b A third embodiment is shown, which is Figure 1a-1h The first embodiment is substantially the same as in, wherein a support structure 200 is added. Figure 3a In the embodiment shown in FIG. 4 , support structure 200 extends between adjacent side surfaces 30. In the case where support structure 46 alone is insufficient for support, support structure 200 supports the area of ​​surface 20a between side surfaces 30 from being crushed during the encapsulation process.

[0040] Figure 3b A complete SLP 202 is shown, wherein portions of the support structure 200 remain in the final device. The support structure 200 extends from the side surface 30, and thus portions of the support structure remain in the final SLP 202. The side surfaces of the support structure 200 are not plated during the same plating step as the side surfaces 30, because the support structure 200 extends completely between adjacent side surfaces. The surfaces of the support structure 200 that are not exposed during plating are exposed from the board singulation SLP 202. The "U" shape of the side surface 30 provides a wide chamfer overall, but the non-plated portion of the support structure 200 may separate the chamfer into two segments. Since it still extends out in three directions, the solder chamfer remains highly visible. If necessary, an automatic visual inspection machine is easily programmed to look for the separated chamfers.

[0041] Figure 4a and 4b The SLP is shown mounted on a printed circuit board (PCB). Figure 4a A cross-sectional view of package 80 is shown. Semiconductor die 64 has two contact pads 66 connected to contacts 28 by solder 210. In other embodiments, any suitable type or form factor of semiconductor die or electrical component may be used. Encapsulant 70 covers semiconductor die 64 and contacts 28, but leaves the bottom and side surfaces of the contacts exposed.

[0042] exist Figure 4a, a wettable conductive layer 211 plated on the contact 28 including the side surface 30 is visible. Depending on the stage of manufacturing when the plating occurs, the plated layer can extend on different surfaces. If the plating occurs before encapsulation, the conductive layer 211 can extend along the inner surface of the contact 28. The solder 212 mechanically bonds and electrically connects the SLP 80 to the PCB or other substrate 360. When reflowed, the solder 212 wets along the side surface 30 to form a chamfer 214 between the contact 28 and the conductive layer 362 of the PCB 360. The chamfer 214 extends outside the footprint of the SLP 80 so as to be visible using an external inspection system.

[0043] Figure 4b Three SLPs 80 are shown mounted on a PCB 360 as part of an electronic device 370. Multiple semiconductor packages are mounted on the surface of the PCB along with the SLPs 80. Depending on the application, the electronic device 370 may have one type of semiconductor package, or multiple types of semiconductor packages.

[0044] Electronic device 370 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 370 may be a subcomponent of a larger system. For example, electronic device 370 may be part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Electronic device 370 may also be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical component.

[0045] exist Figure 4b 360 provides a general base for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 362 are formed on the surface of PCB 360 or within the layers of PCB 360 using evaporation, electrolytic plating, electroless plating, screen printing or other appropriate metal deposition processes. Signal traces 362 provide electrical communication between each of the semiconductor package, the mounted components and other external system components. Traces 362 also provide power and ground connections to the semiconductor package as needed.

[0046] Although one or more embodiments have been shown and described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the present disclosure.

Claims

1. A method for manufacturing a lead frame, the method comprising: providing a sheet of conductive material; The first surface of the sheet is half-etched to form: a first half-etched region with a first contact, the first contact comprising a side surface of the first contact disposed within the first half-etched region, wherein the first half-etched region is completely surrounded by a portion of the first surface that remains intact after the half-etching, and a second half-etched region separated from the first half-etched region; and The second surface of the sheet is half-etched directly above the second half-etched region to form an opening that completely penetrates the sheet, wherein the second surface remains intact above the first half-etched region.

2. The method according to claim 1, wherein: The first surface is half-etched to form a support structure surrounded by the first half-etched area.

3. The method according to claim 1, wherein: The first surface is half-etched to form a second contact, wherein the second contact includes a side surface of the second contact exposed in the first half-etched region.

4. The method according to claim 3, wherein: A side surface of the first contact and a side surface of the second contact form a single continuous surface.

5. The method according to claim 3, wherein: The second contact is disposed on a side of the first half-etched region opposite to the first contact. 6 . The method of claim 1 , further comprising plating a solder wettable layer on a side surface of the first contact.

7. A method for manufacturing a semiconductor device, the method comprising: forming a lead frame by chemically half-etching a sheet of conductive material, wherein the half-etching exposes a first side surface of a first contact of the lead frame at a first portion of the lead frame, and wherein an opening is formed completely through a second portion of the lead frame separate from the first portion; and After the half-etching exposes the first side surface and forms the opening, a solder wettable layer is plated on the first side surface of the first contact. 8 . The method of claim 7 , further comprising depositing an encapsulant on the lead frame after plating the solder wettable layer and after the half-etching exposes the first side surface and forms the opening.

9. The method according to claim 7, wherein: The half etching exposes a second side surface of a second contact of the lead frame and forms a support structure between the first contact and the second contact, and wherein the support structure extends from the first contact to the second contact.

10. A lead frame, comprising: Sheets of conductive material; Wherein, the first surface of the sheet is half-etched to form: a first half-etched region with a first contact, the first contact including a side surface of the first contact exposed within the first half-etched region, wherein the first half-etched region is completely surrounded by a portion of the first surface that is not half-etched, and a second half-etched region separated from the first half-etched region; wherein the second surface of the sheet is half-etched directly above the second half-etched region to form an opening that completely penetrates the sheet, while the second surface remains intact above the first half-etched region; and The lead frame is maintained free of a semiconductor device mounted to the lead frame and a molding compound disposed on the lead frame.

11. The lead frame according to claim 10, the semiconductor package further comprising a third half-etched region formed into the first surface, the third half-etched region comprising a side surface of the second contact exposed within the third half-etched region, wherein The second contact and the first contact belong to the same unit of the lead frame.

12. The lead frame according to claim 11, wherein The opening is disposed between the first half-etched region and the third half-etched region. 13 . The lead frame according to claim 10 , further comprising a second contact, the second contact comprising a side surface of the second contact exposed in the first half-etched region.

14. The lead frame according to claim 13, wherein: A side surface of the first contact and a side surface of the second contact form a single continuous surface.

15. The lead frame according to claim 13, wherein: The second contact is disposed on a side of the first half-etched region opposite to the first contact.

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