Method of manufacturing semiconductor device and corresponding semiconductor device

Abstract

The invention relates to a method of manufacturing a semiconductor device and a corresponding semiconductor device. A semiconductor die is disposed at a die mounting region at a first surface of a die pad in the substrate. The die pad has a second surface opposite the first surface. Laser beam energy is applied to the second surface of the die pad to form a recessed peripheral portion in the second surface of the die pad, the peripheral portion surrounding a central portion opposite the die mounting area at the first surface. A package of electrically insulating material is molded onto a substrate. During molding, the electrically insulating material covers the recessed peripheral portion, and in response to the peripheral portion of the second surface of the die pad being recessed, leakage of the electrically insulating material on the central portion is suppressed.

Description

[0001] This application claims the benefit of priority from Italian application No. 102023000021597, filed on October 17, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0002] This specification relates to semiconductor devices.

[0003] One or more embodiments may be applied to, for example, a semiconductor device including an integrated circuit (IC). Background Art

[0004] Current manufacturing processes for integrated circuit (IC) semiconductor devices include molding an insulating molding compound onto the device to provide an insulating package therefor.

[0005] Resin leakage or flashes at the bottom surface of the die pad may be undesirably caused by the molding step and may result in insufficient plating of the bottom surface of the die pad.

[0006] For example, resin flash has been observed to result in the formation of so-called "tin islands" at the periphery of the bottom surface of the die pad; these masses of solder material may break away from the die pad and may cause undesirable shorts between leads.

[0007] Resin flash may be removed by a de-flash process such as dry de-flash via laser ablation or chemical de-flash.

[0008] However, conventional de-flashing processes have the disadvantage of undesirably promoting delamination between the metallic material (eg, copper) of the leadframe and the electrically insulating package.

[0009] Reference is made to U.S. Patent Application Publication Nos. 2020 / 0273813, 2011 / 0266662, 2022 / 0093494, and 2023 / 0187296, Japanese Patent Application No. 2017079229, and U.S. Patent Nos. 10,366,943, 10,784,186, and 7,262,491 (all of which are incorporated herein by reference), which provide background information in the relevant art.

[0010] There is a need in the art to overcome the shortcomings discussed above. Summary of the invention

[0011] One or more embodiments are directed to a method.

[0012] One or more embodiments relate to a corresponding (integrated circuit) semiconductor device.

[0013] In the solution described herein, laser beam energy is applied to the bottom surface of the die pad to form recessed portions therein that are subsequently filled with an electrically insulating mold compound.

[0014] In the solution described herein, a roughened surface is formed at the recessed portion of the die pad, which enhances the adhesion between the molding compound and the die pad.

[0015] In the solution described here, an adhesion promoting layer which may be provided at the bottom surface of the die pad is removed by laser ablation at the recessed portions of the die pad before molding the electrically insulating package.

[0016] For example, the solution described herein may be advantageously applied to (integrated circuit) semiconductor devices having a quad flat package (QFP) with exposed pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0018] Figure 1 is a cross-sectional view of a semiconductor device;

[0019] Figure 2 Yes Figure 1 Examples of possible aspects of a portion of the rear or bottom surface of the device shown;

[0020] Figure 3 is corresponding to Figure 2 An enlarged view of the portion indicated by arrow III;

[0021] Figure 4 yes Figure 1 An enlarged view of the portion indicated by arrow IV;

[0022] Figure 5A and Figure 5B are cross-sectional views of the same portion of a semiconductor device illustrating processing steps; and

[0023] Figure 6 is a cross-sectional view of a portion of a semiconductor device. DETAILED DESCRIPTION

[0024] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0025] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0026] The edges of a feature depicted in a figure do not necessarily indicate the end of the extent of the feature.

[0027] In the following description, one or more specific details are shown for the purpose of providing a deeper understanding of the examples of the embodiments of the present description. The embodiments may be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0028] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0029] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0030] The headings / references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0031] For simplicity and ease of explanation, throughout the specification, unless the context indicates otherwise, the same reference numerals are used to designate the same parts or elements in the various drawings, and the corresponding description will not be repeated for each drawing.

[0032] Figure 1 is a cross-sectional view showing an (integrated circuit, IC) semiconductor device 10 having a quad flat package (QFP).

[0033] Figure 1 The exemplary device 10 shown in the drawings includes a semiconductor die / chip 14 (the terms "chip" and "die / dies" are considered synonymous herein) attached to the top / front surface of a die pad 12A in a lead frame and an array of leads 12B arranged around the die pad 12A on which the die 14 is mounted.

[0034] The name "leadframe" (or "lead frame", "lead frame") is currently used (see, for example, the United States Patent and Trademark Office USPC Uniform Glossary) to refer to the metal frame that provides support for an integrated circuit chip or die and the electrical leads that interconnect the integrated circuit in the die or chip to other electrical components or contacts.

[0035] Essentially, the leadframe includes an array of conductive structures (or leads 12B) that extend inwardly from an outline position in the direction of the semiconductor chip or die 14, thereby forming an array of conductive structures from a die pad 12A that is configured to have at least one integrated circuit (IC) semiconductor die attached thereto. This can be achieved by conventional means, such as by means of a die attach adhesive (e.g., such as Figure 4 Die attach (DA) film shown).

[0036] like Figure 1 As illustrated in , the semiconductor device 10 may be provided with a die pad 12A having a (central) die mounting area 120A and a raised rim 122A surrounding the die mounting area, such that the die pad 12A has a vat-like shape.

[0037] As shown here by way of example, a (integrated circuit) semiconductor device such as device 10 may also include conductive structures 16 (e.g., wires) that couple the semiconductor die 14 to leads (external pads) 12B (e.g., providing input / output signals) and / or die pads 12A (e.g., providing ground levels).

[0038] An electrically insulating mold compound 20 , such as epoxy, is molded over the assembly to provide a protective, electrically insulating package for the semiconductor device 10 .

[0039] To obtain Figure 1 The fabrication process of the illustrated semiconductor device 10 is conventional in the art, such that a more detailed discussion need not be provided herein.

[0040] For example, Figure 1 The semiconductor device 10 shown is configured to be mounted on a support such as a printed circuit board (PCB). To this end, a solder material (eg, tin) may be provided at a bottom surface of the die pad 12A.

[0041] Figure 2 and Figure 3 (in Figure 3 yes Figure 2 ) shows an (IC) semiconductor device (e.g. Figure 1 1 ).

[0042] As shown, the molding step as described above may undesirably result in some leakage of the molding compound 20 covering the bottom surface of the die pad 12A at the peripheral region thereof (commonly referred to as molding / resin flash).

[0043] In order to prevent undesirable resin flash from covering a larger extension of the bottom surface of the die pad 12A, a groove G is provided in the bottom surface of the die pad 12A. Figure 2 and Figure 3 In the example shown, two grooves G are provided as grooves extending along the periphery of the chip mounting location 120A near its edge to accommodate resin flash.

[0044] Resin flash may result in insufficient plating of solder on the bottom surface of the die pad 12A, and thus may cause problems associated with mounting / soldering on a final substrate (eg, a PCB).

[0045] Furthermore, it is observed that e.g. Figure 3 The resin flash shown in FIG. 1 may result in the formation of so-called "tin islands" (where tin is mentioned only because it is a commonly used solder material). These tin islands are small amounts of solder material that are plated in areas of the bottom surface of the die pad 12A that are not covered by the mold compound 20 leak (e.g., at its periphery); these "lumps" of solder material are prone to detaching from the die pad 12A (e.g., during processing) and may result in, for example, undesired shorts between the leads 12B, leading to device failure.

[0046] According to conventional methods, the problems associated with such mold flash can be solved by a so-called flash removal process, which involves removing the resin flash formed at the bottom surface of the die pad 12A. However, the flash removal process, such as a chemical or dry flash removal process, may undesirably reduce the adhesion of the mold compound 20 to the metal (e.g., copper) lead frame, thereby possibly causing delamination of the mold compound 20.

[0047] Delamination of the mold compound 20 from the die pad 12A or the leads 12B may result in moisture or contaminants entering the package, potentially reaching the semiconductor die 14 and causing failure of the device 10 .

[0048] Furthermore, delamination caused by chemical deflashing may be more severe when an adhesion promoter, such as a non-etching adhesion promoter (NEAP), is used to enhance adhesion between the mold compound 20 and the leadframes 12A, 12B.

[0049] Figure 4 yes Figure 1 FIG. 1 is an enlarged view of the portion indicated by arrow IV in FIG. 1 , which shows an adhesion promoter (eg, NEAP) layer 100 provided at the interface between the mold compound 20 and the lead frames 12A, 12B.

[0050] When device 10 is processed in deflashing, adhesion promoting layer 100 may at least partially dissolve, possibly leading to delamination issues. Delamination is observed to be more likely to start at line D, the point at the interface between die pad 12A and mold compound 20 exposed to the deflashing bath.

[0051] According to another conventional method, a dry de-flashing process may be used to remove the molding compound flash at the bottom surface of the die pad 12A.

[0052] Dry de-flashing may include applying laser beam energy to the bottom surface of the die pad 12A to remove unwanted resin flash by laser ablation.

[0053] However, to combat undesirable ablation of the encapsulation molding compound, laser ablation typically does not extend to the edge of the back / bottom surface of the die pad 12A exposed at the bottom of the device 10 .

[0054] In other words, laser beam energy is not applied to the periphery of the back / bottom surface of the die pad 12A exposed at the bottom surface of the device 10 (at Figure 4 A “safety” zone S (e.g., about 100 microns) is defined to the right of the interface line D in FIG. 1 ) so as not to undesirably ablate the mold compound 20 (in FIG. 1 ) forming the electrically insulating package. Figure 4 to the left of the interface line D in ).

[0055] The solution described herein involves applying laser beam energy to the bottom surface of the die pad to form a recessed portion therein, which is subsequently filled with an electrically insulating material during molding.

[0056] In the solution described herein, a roughened surface may be formed on the recessed portion of the die pad, which enhances adhesion between the molding compound and the die pad.

[0057] In the solution described here, an adhesion promoting layer which may be provided at the bottom surface of the die pad is removed by laser ablation at the recessed portions of the die pad before molding the electrically insulating package.

[0058] For example, the solution described here can be advantageously applied to Figure 1 A (integrated circuit) semiconductor device having a quad flat package (QFP) with exposed pads, such as the semiconductor device 10 shown in FIG.

[0059] Figure 5A and Figure 5B According to the embodiments of the present specification, the invention is applied to Figure 1 1 is a diagram illustrating processing steps of a semiconductor device 10 of an example embodiment.

[0060] As is known to those skilled in the art, multiple semiconductor devices (e.g., Figure 1 The individual lead frames may be held together via tie bars (or dam bars) extending around the periphery of each (individual) lead frame. A final singulation step removes the tie bars (dam bars) to obtain a plurality of individual semiconductor devices.

[0061] For simplicity and ease of explanation, the following description will refer to the fabrication of a single device.

[0062] It should be understood that the structural details of the device 10 discussed herein are merely examples of devices to which the solutions described herein may be advantageously applied and should not be construed as limiting.

[0063] For example, those skilled in the art will appreciate that the solution described herein may also be applied in other packages having an exposed die pad, such as a quad flat no-lead package (QFN) and / or a lead frame having no depression between the die pad 12A and the lead 12B and / or a die pad 12A having no raised edge 122A.

[0064] Figure 5A is an illustrative diagram of the semiconductor die 14 mounted (eg, by a die attach material DA) on the top / front side of the die pad 12A, at the die mounting region 120A thereof.

[0065] As shown, laser beam energy LB is applied to the back / bottom surface of the chip pad 12A at the periphery of the bottom surface of the chip pad 12A to form a recessed portion 1000 therein. That is, the metal material (e.g., copper) of the die pad 12A (i.e., a portion of the copper die pad) is removed from the back / bottom surface of the die pad 12A by laser ablation to form the recessed portion 1000 along the periphery of the back / bottom surface of the die pad 12A.

[0066] As shown, the recessed peripheral portion 1000 surrounds a central portion of the rear / bottom surface opposite the die mounting area 120A at the front / top surface of the die pad 12A.

[0067] The recessed peripheral portion 1000 of the back / bottom surface of the die pad 12A may be formed with a depth, for example, in the range of 25 to 35 microns. Figure 5A In the figure, it is indicated by the reference symbol T.

[0068] exist Figure 5AIn the exemplary case shown, an adhesion promoting layer (eg, NEAP layer) is disposed on the surface of the lead frame (ie, the die pad 12A and the leads 12B).

[0069] As shown, application of laser beam energy LB to form a peripheral recessed region 1000 of the backside / bottom surface of the die pad 12A results in the adhesion promoting layer 100 being removed (ablated) at the peripheral recessed region 1000 .

[0070] Figure 5B A molding step is shown in which an electrically insulating encapsulating material 20 (eg, epoxy) is molded onto the substrate (eg, leadframe) 12A, 12B having the semiconductor die 14 mounted thereon after the recessed portion 1000 is formed as described above.

[0071] As shown, the (electrically insulating) molding compound 20 fills the recessed peripheral portion 1000 of the back / bottom surface of the die pad 12A, thereby forming a layer of packaging material 20 covering the back / bottom surface of the die pad 12A at the recessed portion 1000 (having a thickness theoretically equal to the depth T of the recessed portion 1000).

[0072] In other words, after the molding step, the bottom surface of the device 10 includes: a central inner area (inside the boundary line D') of the bottom surface of the die pad 12A, where the metal material of the die pad 12A is not covered by the packaging material 20; and a peripheral outer area of ​​the bottom surface of the die pad 12A, i.e., the peripheral recessed portion 1000, where the metal material of the die pad 12A is covered by the packaging material 20.

[0073] As shown, in devices where the die pad 12A includes a raised rim 122A surrounding the die mounting area 120A, the peripheral rim 122A is embedded in the encapsulation material 20 .

[0074] It can be observed that the peripheral recessed area 1000 formed at the die mounting area 120A prevents undesirable leakage of the molding material on the central portion of the back / bottom surface of the die pad 12A.

[0075] Furthermore, applying the laser beam energy LB to form the peripheral recessed portion 1000 as shown has the effect of roughening the back / bottom surface of the chip mounting region 120A at the peripheral recessed portion 1000 .

[0076] As used herein, a "roughened" surface means that the surface is made rough, in accordance with common usage.

[0077] It has been found that the roughened surface promotes adhesion between the encapsulation material 20 and the die pad 12A, thereby reducing the risk of delamination.

[0078] In short, as here about Figure 5A , Figure 5B and Figure 6 The described solution involves molding a package 20 of an electrically insulating material, such as epoxy, onto a substrate, such as a lead frame including a die pad 12A and leads 12B, on which at least one semiconductor die 14 is arranged.

[0079] As shown, the semiconductor die 14 is disposed in a die mounting area 120A of a substrate at a first (top / front) surface of a die pad 12A, wherein the die pad 12A has a second (bottom / back) surface opposite the first surface.

[0080] Laser beam energy LB is applied to the second surface of the chip base 12A to form therein a recessed peripheral portion 1000 (preferably having a depth between 25 and 35 micrometers) surrounding a central portion opposite to the chip mounting region 120A at the first surface.

[0081] During molding, the electrically insulating material 20 covers the recessed peripheral portion 1000 , and in response to the peripheral portion 1000 of the second surface of the die pad 12A being recessed, leakage of the electrically insulating material 20 on the central portion is suppressed.

[0082] Advantageously, the recessed peripheral portion 1000 of the second surface of the die pad 12A is roughened in response to the laser beam energy LB applied thereto, thereby promoting adhesion of the electrically insulating material 20 to the recessed peripheral portion.

[0083] Figure 6 An embodiment of the present description is shown in which adhesion between the metal material of the die pad 12A and the mold compound 20 can be further promoted by forming (via laser ablation LB) an engraving 1100 in a peripheral recessed portion 1000 of the die mounting portion such as a notch or groove 1100 extending along the recessed peripheral portion 1000.

[0084] Figure 6 It is also shown that in addition to the (otherwise conventional) groove G, a peripheral recessed portion 1000 may be provided at the back / bottom side of the die pad 12A, thereby further reducing the risk of resin leakage that undesirably covers a central portion of the second surface of the die pad 12A.

[0085] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described purely by way of example, without departing from the scope of the embodiments.

[0086] The claims are an integral part of the technical teaching provided with respect to the embodiments.

[0087] The scope of protection is determined by the appended claims.

Claims

1. A method comprising: forming a lead frame including a die pad having a first surface and a second surface opposite the first surface; providing an adhesion promoting layer on at least a second surface of the die pad; applying laser beam energy to the second surface of the die pad to selectively remove the adhesion promoting layer at a peripheral portion surrounding a central portion and further selectively remove material of the die pad at the peripheral portion to form a recessed peripheral portion surrounding the central portion in the second surface of the die pad; mounting a semiconductor die to a die mounting area at the first surface of the die pad; as well as molding a package of electrically insulating material onto the lead frame and the semiconductor die disposed on the die pad; The electrically insulating material covers a peripheral portion of the recess. 2 . The method of claim 1 , wherein the recessed peripheral portion of the second surface of the die pad has a depth in the range of 25 to 35 microns. 3 . The method of claim 1 , further comprising roughening a surface at a peripheral portion of the recess of the die pad, and wherein adhesion of the electrically insulating material to the peripheral portion of the recess is facilitated by the roughened surface.

4. The method of claim 1 , wherein forming the lead frame comprises providing the die pad with a raised edge at a periphery of the die pad, wherein the raised edge is embedded in the electrically insulating material, and wherein a peripheral portion of the recess is located between the raised edge and the central portion. 5 . The method of claim 1 , further comprising engraving features of the recess at a surface of a peripheral portion of the recess, and wherein the electrically insulating material fills the features of the recess.

6. A device comprising: a lead frame including a die pad having a first surface and a second surface opposite the first surface; an adhesion promoting layer on the first surface and the second surface of the die pad; wherein the die pad includes a recessed peripheral portion surrounding a central portion at the second surface, wherein the adhesion promoting layer is absent at a surface of the recessed peripheral portion; a semiconductor die disposed at the first surface of the die pad; as well as An electrical insulating material encapsulating the lead frame and the semiconductor die; The electrically insulating material covers a peripheral portion of the recess. 7 . The device of claim 6 , wherein the adhesion promoting layer completely covers all surfaces of the die pad except for a surface of a peripheral portion of the recess. 8 . The device of claim 6 , wherein a peripheral portion of the recess of the die pad has a depth in a range of 25 to 35 microns. 9 . The device of claim 6 , wherein the surface of the peripheral portion of the recess of the die pad is roughened.

10. The device of claim 6, wherein the die pad comprises a raised rim at a periphery of the die pad, wherein the raised rim is embedded in the electrically insulating material, and wherein a peripheral portion of the recess is located between the raised rim and the central portion.

11. The device of claim 6, wherein the surface of the peripheral portion of the recess comprises a groove or notch feature, and wherein the electrically insulating material fills the groove or notch feature. 12 . The device of claim 6 , further comprising a groove disposed in the second surface of the die pad at the central portion.

13. A method comprising: mounting a semiconductor die to a die mounting area at a first surface of a die pad in a substrate, wherein the die pad has a second surface opposite to the first surface; applying laser beam energy to the second surface of the die pad to form a recessed peripheral portion surrounding a central portion in the second surface of the die pad, the central portion of the second surface of the die pad being opposite the die mounting area at the first surface; as well as molding a package of electrically insulating material onto the substrate and the semiconductor die disposed on the substrate; During the molding, the electrically insulating material covers a peripheral portion of the recess, wherein in response to the recessing of the peripheral portion of the second surface of the die pad, leakage of the electrically insulating material on the central portion is offset. 14 . The method of claim 13 , wherein the recessed peripheral portion of the second surface of the die pad has a depth in the range of 25 to 35 microns.

15. The method of claim 13, wherein a surface at a peripheral portion of the recess of the second surface of the die pad is roughened by the applied laser beam energy, and wherein adhesion of the electrically insulating material to the peripheral portion of the recess is promoted by the roughened surface.

16. The method of claim 13, wherein the die pad includes a raised edge surrounding the die mounting area at the first surface of the die pad, wherein the raised edge is embedded in the electrically insulating material during the molding, and wherein a peripheral portion of the recess is located between the raised edge and the central portion.

17. The method according to claim 13, further comprising: providing an adhesion promoting layer on the second surface of the die pad; as well as Wherein applying laser beam energy to form a peripheral portion of the depression of the second surface of the die pad includes removing a portion of the adhesion promoting layer and the die pad to form the peripheral portion of the depression. 18 . The method of claim 13 , further comprising forming an engraving at a peripheral portion of the recess of the second surface of the die pad, wherein adhesion of the electrically insulating material to the peripheral portion of the recess is facilitated by the engraving.

19. A device comprising: a substrate having a die mounting area at a first surface of a die pad, wherein the die pad has a second surface opposite the first surface; A semiconductor chip is arranged at the chip mounting area; wherein the die pad includes a recessed peripheral portion formed by laser beam energy applied to the second surface of the die pad, the recessed peripheral portion surrounding a central portion opposite a die mounting area at the first surface; as well as a package of electrically insulating material molded onto the substrate and the semiconductor die; The electrically insulating material covers a peripheral portion of the recess, wherein in response to the peripheral portion of the second surface of the die pad being recessed, leakage of the electrically insulating material on the central portion is suppressed.

20. The device of claim 19, wherein the recessed peripheral portion of the second surface of the die pad has a depth in the range of 25 to 35 microns. 21 . The device of claim 19 , wherein a surface of a peripheral portion of the recess of the second surface of the die pad is roughened, wherein the electrically insulating material adheres to the roughened surface.

22. The device of claim 19, wherein the die pad comprises a raised rim surrounding the die mounting area at the first surface of the die pad, wherein the raised rim is embedded in the electrically insulating material, and wherein a peripheral portion of the recess is located between the raised rim and the central portion.

23. The device of claim 19, further comprising an engraving in a surface at a peripheral portion of the recess of the die pad. 24 . The device of claim 19 , further comprising a groove disposed at the central portion of the second surface of the die pad.

25. The device of claim 19, wherein an outer surface of the die pad is covered by an adhesion promoting layer except at a peripheral portion of the recess.

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