Semiconductor device preparation method and semiconductor device prepared based on semiconductor device preparation method

Abstract

The invention provides a preparation method of a semiconductor device. The preparation method of the semiconductor device comprises the following steps in sequence: (1) a transistor structure forming step, (2) a shallow trench forming step and (3) an electrical isolation structure forming step. The preparation method of the transistor comprises the following steps: providing a substrate, forming a double-well region on the substrate, and preparing a transistor structure in the double-well region; the double-well region comprises a first well region and a second well region which are adjacent to each other, and the first well region and the second well region are constantly kept uninterruptedly connected before the shallow trench forming step is carried out; the shallow trench forming step comprises the following operations: forming a shallow trench at the boundary between the first well region and the second well region; the step of forming the electrical isolation structure comprises the following operations: depositing an isolation oxide on the surface of the double-well region to form a shallow trench isolation structure and an electrical isolation layer. The first well region and the second well region are kept in uninterrupted connection, so that diffusion of well ions in other regions in the first well region / the second well region to the boundary between the first well region and the second well region is inhibited, and the uniformly doped region of the well ions in the first well region and the second well region is widened; therefore, the effect of inhibiting the threshold voltage drop of the semiconductor device is achieved. Meanwhile, the operation is also beneficial to simplifying the processing procedure of the semiconductor device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular, relates to a method for preparing a semiconductor device and a semiconductor device prepared based on the method. Background Art

[0002] The shallow trench isolation (STI) process is a commonly used process in integrated circuit manufacturing. The STI process refers to the use of isolation oxide to fill the grooves set in the active area to embed very thick oxide between the active areas of the device, thereby forming electrical isolation in the active area, and dividing the active area into well areas with different electrical properties through the STI structure.

[0003] When the manufacturing process of integrated circuits develops to deep submicron process technology, the electrical characteristics of the area near the edge of the well region will be affected by the distance from the groove area of ​​the device to the well boundary. This phenomenon is called the well proximity effect (WPE). The reason for the WPE effect is that during the well ion implantation process, the ions accelerated by the electric field are scattered and emitted at the photoresist boundary and side. The scattered and reflected ions will enter the surface of the STI structure, affecting the doping concentration of the area near the well boundary, resulting in the well ion doping concentration near the well boundary being non-uniform. The well ion doping concentration will change with the distance from the well boundary. The well ion doping concentration of the area near the well boundary is greater than that of the well ion doping concentration in the middle area of ​​the well region. In particular, the diffusion of boron ions doped in the P well region is more obvious, because boron ions are lighter. In addition, with the development of integrated circuit manufacturing technology, more and more types of well ions are injected into the well region, resulting in more and more significant uneven diffusion of well ions. The existence of the WPE effect causes the threshold voltage of the device to decrease. As the manufacturing process of integrated circuits further develops to nano-process technology, the impact of the WPE effect becomes more and more serious, and its impact on devices can no longer be ignored. Summary of the invention

[0004] In order to suppress the uneven diffusion of trapped ions, the present invention provides a method for preparing a semiconductor device and a semiconductor device prepared based on the method.

[0005] According to a first aspect of the present invention, a method for preparing a semiconductor device is provided, the method comprising the following steps performed in sequence: (1) a transistor structure forming step, (2) a shallow trench forming step, and (3) an electrical isolation structure forming step; the transistor forming step comprising the following operations: providing a substrate, performing an ion implantation process on the substrate to form a dual-well region, and preparing a transistor structure in the dual-well region; the dual-well region comprises a first well region and a second well region adjacent to each other, the first well region being of a first conductivity type, the second well region being of a second conductivity type, and before the shallow trench forming step is performed, the first well region and the second well region are always kept in uninterrupted connection; the shallow trench forming step comprising the following operations: forming a shallow trench at a boundary between the first well region and the second well region, the shallow trench being a groove for preparing a shallow trench isolation structure; the electrical isolation structure forming step comprising the following operations: depositing an isolation oxide on the surface of the dual-well region, at least a portion of the isolation oxide filling the interior of the shallow trench to form a shallow trench isolation structure, and at least a portion of the isolation oxide covering the transistor structure to form an electrical isolation layer on the surface of the transistor structure.

[0006] In the above-mentioned semiconductor device preparation method provided by the present invention, when the first well region and the second well region are in an uninterrupted connection state, the area near the boundary between the first well region and the second well region is doped with trap ions (called "boundary trap ions"), and the presence of boundary trap ions inhibits the diffusion of trap ions in other areas of the first well region / second well region to the above-mentioned boundary, reduces the diffusion dose of trap ions to the above-mentioned boundary, thereby widening the area where the trap ions are uniformly doped in the first well region and the second well region. As described above, before the shallow trench forming step is performed, the first well region and the second well region are always kept in uninterrupted connection. Based on this, it is beneficial for the first well region and the second well region to still maintain good trap ion doping uniformity after multiple annealing during the preparation of the transistor structure. Of course, to a certain extent, the trap ion doping concentration in the area near the boundary between the first well region and the second well region may still be slightly higher than the trap ion doping concentration in other areas of the first well region and the second well region. However, when entering the shallow trench forming step, the shallow trench is formed by etching the boundary between the first well region and the second well region, and the area with a higher trap ion doping concentration is removed by the above-mentioned etching operation. Therefore, after forming the shallow trench, the doped well ions in the first well region and the second well region that are still retained in the device can be evenly distributed in the well region to which they belong, thereby suppressing the threshold voltage drop of the semiconductor device. In the prior art, the shallow trench is generally formed before forming the well region with different electrical properties. Compared with the well region, the content of well ions in the shallow trench region is lower, which promotes the diffusion of well ions into the shallow trench. In the subsequent process of forming the transistor structure, it is necessary to undergo multiple annealing treatments, which will further aggravate the diffusion of well ions, causing the concentration of well ions in the working area of ​​the device to decrease, and ultimately leading to a significant decrease in the threshold voltage of the semiconductor device.

[0007] On the other hand, in the semiconductor device preparation method provided by the present invention, a shallow trench isolation structure and an electrical isolation layer can be formed at one time by depositing an isolation oxide in the electrical isolation structure forming step, which is equivalent to integrating the STI process for preparing a shallow trench isolation structure and the ILD process for preparing an electrical isolation layer in the prior art into a one-step process, which not only simplifies the process steps, but also reduces the process cost and improves the economic benefits of the process.

[0008] Preferably, a stress covering layer preparation step is provided between the shallow trench forming step and the electrical isolation structure forming step; the stress covering layer preparation step includes the following operations: S1. forming a stress covering layer on the surface of the double well region, so that the surface of the transistor structure and the inner groove wall surface of the shallow trench are covered by the stress covering layer; S2. annealing the device provided with the stress covering layer. Based on the stress memory effect, the above-mentioned stress covering layer transfers the stress to the area covered by it through annealing, and the stress will be directly memorized by these areas, so that the effective mass and scattering probability of the electron conductivity along the shallow trench direction can be reduced, thereby effectively improving the carrier mobility and the speed of the semiconductor device. In the above scheme, since the stress covering layer directly covers the inner groove wall surface of the shallow trench, the stress of the stress covering layer can be more fully transferred to the shallow trench. On the other hand, the stress covering layer can also act as an etching barrier layer, play a role in surface protection of transistors and shallow trenches, and can hinder the diffusion of trap ions in the area near the boundary of the shallow trench to the shallow trench, which is conducive to further improving the uniformity of trap ion doping in the first well region and the second well region, and plays a role in regulating the threshold voltage of the semiconductor device. In summary, the setting of the above-mentioned stress covering layer can play a role equivalent to stress memory technology (Street Memorization Technique, SMT) for the device, so there is no need for additional SMT processing during the device processing, the process flow is simplified, and the performance of the semiconductor device can be improved.

[0009] Preferably, the stress covering layer preparation step includes a tensile stress covering area preparation step and / or a compressive stress covering area preparation step; the stress covering layer prepared by the tensile stress covering area preparation step satisfies that the stress covering layer transmits tensile stress to the device structure covered by it after annealing; the stress covering layer prepared by the compressive stress covering area preparation step satisfies that the stress covering layer transmits compressive stress to the device structure covered by it after annealing. The type of stress that the stress covering layer can provide can be adjusted by adjusting the preparation process of the stress covering layer and the raw materials used. For example, in the tensile stress covering area preparation process, SiH4 and NH3 are used as film-forming raw materials to prepare Si3N4 thin film as the above-mentioned stress covering layer through PECVD process, and the stress covering layer obtained can transmit tensile stress to the device structure through annealing. For example, in the preparation process of the compressive stress covering area, a Si3N4 thin film is prepared as the above-mentioned stress covering layer through a PECVD process with a dual-frequency RF power supply, using SiH4, NH3, H2 and Ar (or N2) as film-forming raw materials. The stress covering layer thus obtained can transfer compressive stress to the device structure through annealing treatment.

[0010] Preferably, in the above-mentioned annealing treatment involving the stress covering layer transferring compressive stress to the device structure covered by it through annealing treatment, the annealing treatment is performed by laser annealing, the annealing temperature is 1200℃~1300℃, and the annealing time is 300μs~500μs. In actual situations, single-beam laser annealing or double-beam laser annealing can be selected based on actual conditions. Preferably, during the annealing process, an electrostatic micro-disk (E-chuck 400C) is used to fix the wafer. More preferably, the annealing temperature is 1250℃ and the annealing time is 400μs.

[0011] Preferably, in the shallow trench forming step, the shallow trench is formed by combining lithography technology with dry etching.

[0012] Preferably, a carbon-containing polymer is filled on the surface of the wafer to form a flat carbon coating (ODL layer), and then a photoresist layer is arranged on the surface of the ODL layer, and a notch corresponding to a preset position of the shallow groove is formed in the photoresist layer by lithography technology, and then dry etching is further performed along the formed notch to complete the formation of the shallow groove, and finally the photoresist layer and the mask are removed.

[0013] Preferably, an anti-reflection layer is provided between the ODL layer and the photoresist layer, and when the photoresist layer is removed, the anti-reflection layer is removed together. Preferably, the anti-reflection layer is a bottom anti-reflection layer.

[0014] Preferably, in the shallow trench forming step, after the shallow trench is formed, an oxide protective layer is formed on the inner groove wall surface of the shallow trench. The provision of the above oxide protective layer can repair the damage to the inner groove wall surface of the shallow trench caused by the etching operation involved in the shallow trench forming step.

[0015] Preferably, in the transistor structure forming step, the preparation of the transistor structure includes the following operations in sequence: a gate dielectric layer process, forming a gate dielectric layer on the surface of the double well region; a gate process, forming a gate on the surface of the gate dielectric layer; a lightly doped ion implantation process, forming a diffusion region in the well region below the boundary of the gate by using an ion implantation process; an outer sidewall process, forming a first sidewall structure on the side of the gate, the first sidewall structure covering the side of the gate; a source-drain ion implantation process, forming a source region and a drain region below the boundary of the gate by using an ion implantation process; and a salicide process, forming a metal silicide covering layer on the surfaces of the gate, the source region, and the drain region.

[0016] Preferably, the gate dielectric layer covers the surface of the double well region.

[0017] Preferably, the gate process includes the following operations: a polycrystalline silicon gate material layer, a first oxide layer, a Si3N4 thin film layer, a second oxide layer, an amorphous carbon layer, and an anti-reflective layer are sequentially arranged on the surface of the gate dielectric layer; a mask is placed on the surface of the anti-reflective layer, the mask covers the position where the gate needs to be formed, and the polycrystalline silicon gate material layer, the first oxide layer, the Si3N4 thin film layer, the second oxide layer, the amorphous carbon layer, and the anti-reflective layer are removed by lithography technology except for the position corresponding to the gate; the mask is removed and the remaining parts of the second oxide layer, the amorphous carbon layer, and the anti-reflective layer above the polycrystalline silicon gate material retained on the surface of the gate dielectric layer are removed, so that the polycrystalline silicon gate material retained on the surface of the gate dielectric layer is used as the gate.

[0018] Preferably, the anti-reflection layer includes a first anti-reflection layer and a second anti-reflection layer which are stacked, wherein the second anti-reflection layer is arranged close to the mask, and the second anti-reflection layer is a bottom anti-reflection layer.

[0019] Preferably, an inner sidewall process is included between the gate process and the lightly doped ion implantation process; the inner sidewall process includes the following operations: forming a second sidewall structure on the side of the gate, the second sidewall structure is arranged between the side of the gate and the first sidewall structure.

[0020] Preferably, the inner sidewall process includes the following operations: first forming a SiO2 thin film layer on the side of the gate, removing the Si3N4 thin film layer on the upper surface of the gate, then depositing a Si3N4 thin film layer on the surface of the double well region to completely cover the outer surface of the gate, removing the portion of the Si3N4 thin film layer except for the area covering the side of the gate, thereby forming a SiO2 thin film layer and a Si3N4 thin film layer stacked in sequence on the side of the gate, and these two thin film layers together constitute a second sidewall structure, and the second sidewall structure covers the side of the gate.

[0021] Preferably, the first sidewall structure includes a SiO2 thin film layer and a Si3N4 thin film layer stacked in sequence on the surface of the second sidewall structure.

[0022] Preferably, in the stress cover layer preparation step, in the shallow trench forming step, after forming the oxide protection layer, an ion implantation process is performed on the area of ​​the double well region adjacent to the shallow trench at the location of the shallow trench to control the threshold voltage of the semiconductor device.

[0023] Preferably, after the electrical isolation structure forming step is completed, a contact hole forming step is further included; the contact hole forming step includes the following operations: forming a through hole perpendicular to the substrate in the electrical isolation layer, and filling tungsten in the through hole.

[0024] According to a second aspect of the present invention, there is provided a semiconductor device manufactured by the above semiconductor device manufacturing method.

[0025] Based on the above-mentioned semiconductor device preparation method, the threshold voltage of the semiconductor device provided by this solution is highly controllable, so that the semiconductor device has good electrical properties.

[0026] According to the third aspect of the present invention, a semiconductor device is provided, which includes a substrate, a dual-well region, a transistor structure, and an isolation oxide. The dual-well region is arranged on the surface of the substrate, and the dual-well region includes an adjacent first well region and a second well region, the first well region is of a first conductivity type, and the second well region is of a second conductivity type. A groove is provided at the junction of the first well region and the second well region, and the groove is a shallow trench; at least a portion of the isolation oxide fills the interior of the shallow trench, and the portion of the isolation oxide forms a shallow trench isolation structure; at least a portion of the isolation oxide covers the surface of the transistor structure, and the portion of the isolation oxide forms an electrical isolation layer; the shallow trench isolation structure and the electrical isolation layer are integrally formed. Based on the above-mentioned semiconductor device preparation method provided by the present invention, since the shallow trench isolation structure and the electrical isolation layer are formed in one step by depositing the isolation oxide, in the semiconductor device obtained thereby, the shallow trench isolation structure and the electrical isolation layer are integrally formed.

[0027] Preferably, the semiconductor device further comprises a stress covering layer, wherein the stress covering layer is provided between the inner groove wall of the shallow groove and the shallow trench isolation structure filling the shallow groove, and the stress covering layer is provided between the transistor structure and the electrical isolation layer covering the same. Since the stress covering layer is extended to the inner groove wall of the shallow groove, the shallow groove can be subjected to more sufficient stress, and the stress covering layer is consistent with the movement direction of the carriers, thereby effectively improving the speed of the semiconductor device.

[0028] Preferably, an oxide protection layer is further provided between the inner groove wall of the shallow groove and the stress covering layer.

[0029] Preferably, the material of the stress cover layer includes at least one of Si3N4 and SiCN.

[0030] Preferably, the stress covering layer includes at least one of a tensile stress covering area and a compressive stress covering area, the tensile stress covering area transfers tensile stress to the area covered by it after annealing, and the compressive stress covering area transfers compressive stress to the area covered by it after annealing.

[0031] The tensile stress coverage area will generate uniaxial tensile stress in the

[100] direction of the N-type transistor structure (NMOS) channel, thereby reducing the effective mass and scattering probability of electron conduction in the channel direction and improving the speed of NMOS. The compressive stress coverage area will generate uniaxial compressive stress in the

[100] direction of the P-type transistor structure (PMOS) channel. The compressive stress in this direction can cause the valence band energy band to split, the heavy hole band leaves the top of the valence band, and the light hole band occupies the top of the valence band, thereby reducing the effective mass of the conduction of holes in the channel direction and improving the speed of PMOS.

[0032] Preferably, the stress covering layer includes a tensile stress covering region, the transistor structure includes an N-type transistor structure, and at least a portion of the stress covering layer covering the surface of the N-type transistor structure is the tensile stress covering region.

[0033] Preferably, the semiconductor device satisfies at least one of the following a, b, c, d, and e: a. The transistor structure includes an N-type transistor structure, the N-type transistor structure includes an N-type transistor structure I, and the stress covering layer covering the surface of the N-type transistor structure I is a tensile stress covering area; b. The transistor structure includes a P-type transistor structure, the P-type transistor structure includes a P-type transistor structure I, and the stress covering layer covering the surface of the P-type transistor structure I is a compressive stress covering area; c. The transistor structure includes an N-type transistor structure, the N-type transistor structure includes an N-type transistor structure II, and the stress covering layer covering the side surface of the N-type transistor structure II includes a tensile stress covering region and a compressive stress covering region; d. The transistor structure includes a P-type transistor structure, the P-type transistor structure includes a P-type transistor structure II, and the stress covering layer covering the side surface of the P-type transistor structure II includes a tensile stress covering region and a compressive stress covering region; e. The transistor structure includes a P-type transistor structure, the P-type transistor structure includes a P-type transistor structure III, and the stress covering layer covering the surface of the P-type transistor structure III is a tensile stress covering area.

[0034] Preferably, on a plane parallel to the substrate, the arrangement direction of the adjacent first well region and the second well region is the L direction, and the direction perpendicular to the L direction is the W direction; and the semiconductor device satisfies at least one of the following f and g: f. The semiconductor device satisfies c, and the stress covering layer covering the side surface of the N-type transistor structure II includes a longitudinal covering layer extending along the L direction and a transverse covering layer extending along the W direction, the longitudinal covering layer is a tensile stress covering region, and the transverse covering layer is a compressive stress covering region; g. The semiconductor device satisfies condition d, and the stress covering layer covering the side surface of the P-type transistor structure II includes a longitudinal covering layer extending along the L direction and a transverse covering layer extending along the W direction, the longitudinal covering layer is a tensile stress covering area, and the transverse covering layer is a compressive stress covering area.

[0035] In summary, compared with the prior art, the present invention has the following unexpected beneficial technical effects: 1. The present invention processes semiconductor devices according to the steps of first preparing a well region, then forming a shallow trench, and forming an electrical isolation structure in the shallow trench. Based on this, the well ions in different well regions of the semiconductor device can be evenly distributed in the well regions to which they belong, thereby avoiding the decrease in the semiconductor threshold voltage caused by the diffusion of the well ions into the shallow trench.

[0036] 2. Since the preparation of the well region has been completed before the shallow trench is prepared, the preparation of the shallow trench isolation structure and the electrical isolation layer can be completed at one time during the step of forming the electrical isolation structure, thereby simplifying the semiconductor preparation process and reducing the cost of semiconductor preparation.

[0037] 3. In the preferred embodiment of the present invention, by covering the inner groove wall surface of the shallow groove with a stress covering layer, the stress of the stress covering layer is more fully transferred to the shallow groove, which can effectively improve the speed of the semiconductor device. At the same time, the stress covering layer can also hinder the diffusion of trap ions in the area near the boundary of the shallow trench into the shallow trench, which is beneficial to further improve the uniformity of trap ion doping in the first well region and the second well region.

[0038] 4. In the preferred embodiment of the present invention, the conductivity type of the transistor and the equipment requirements are comprehensively considered, and a stress covering layer applying different types of stress is set on the surface of the transistor and on the inner surface of the shallow trench arranged around the transistor, so that the speed of the semiconductor device is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A process flow chart of the semiconductor device manufacturing method used in Example 1; Figure 2 is a process flow chart of the transistor forming step involved in Example 1; Figure 3 Schematic diagram of the wafer structure obtained after the gate dielectric process involved in Example 1 is completed; Figure 4Schematic diagram of the wafer structure obtained after S2 in the gate process involved in Example 1 is completed; Figure 5 Schematic diagram of the wafer structure obtained after the gate process involved in Example 1 is completed; Figure 6 Schematic diagram of the wafer structure obtained after the inner sidewall process involved in Example 1 is completed; Figure 7 This is a schematic diagram of the wafer structure obtained after the outer wall process involved in Example 1 is completed; Figure 8 Schematic diagram of the wafer structure obtained after the transistor forming step involved in Example 1 is completed; Fig. 9 Schematic diagram of forming a shallow groove in the shallow groove forming step involved in Example 1; Fig.10 Schematic diagram of the wafer structure obtained after the shallow trench forming step S2 involved in Example 1 is completed; Fig.11 Schematic diagram of the wafer structure obtained after the shallow trench forming step S3 involved in Example 1 is completed; Fig.12 Schematic diagram of the wafer structure obtained after the stress cover layer preparation step involved in Example 1 is completed; Fig.13 A schematic diagram of a wafer structure obtained after the electrical isolation structure forming step involved in Example 1 is completed; Fig.14 A schematic diagram of the wafer structure obtained after the contact hole forming step involved in Example 1 is completed; Fig.15 is a schematic top cross-sectional view of a wafer structure obtained after the stress cover layer preparation step is completed in Example 1; Fig.16 is a schematic top cross-sectional view of a wafer structure obtained after the stress cover layer preparation step is completed in Example 2; Fig.17 is a schematic top cross-sectional view of a wafer structure obtained after the stress cover layer preparation step is completed in Example 3; Fig.18 Schematic diagram of a top cross-section of a wafer structure obtained after the stress cover layer preparation step is completed in Example 4.

[0040] In the above drawings, the corresponding relationship of each reference numeral is as follows: 1-11, first well region; 1-12, second well region; 1-2, gate dielectric layer; 1-3, PLDD region; 1-4, NLDD region; 1-5, p+ heavily doped region; 1-6, n+ heavily doped region; 1-7, P-type transistor structure; 1-8, N-type transistor structure; 2. Gate; 2-1. Polysilicon gate material layer; 2-2. First oxide layer; 2-3. Si3N4 thin film layer; 2-4. Second oxide layer; 2-5. Amorphous carbon layer; 2-6. ARC anti-reflection layer; 2-7. BARC bottom anti-oxidation layer; 2-8. Mask; 3-1, first sidewall structure; 3-2, second sidewall structure; 3-3, metal silicide covering layer; 4. Shallow trench; 4-1. ODL layer; 4-2. Bottom anti-reflection layer; 4-3. Photoresist layer; 4-4. Oxide protection layer; 5-1, compressive stress covering layer; 5-2, tensile stress covering layer; 6-1. Shallow trench isolation structure; 6-2. Electrical isolation layer; 7-1, through hole; 7-2, tungsten. DETAILED DESCRIPTION

[0041] Below, the present invention is further described in conjunction with the accompanying drawings and specific embodiments: In the description of the present invention, it should be noted that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0043] Example 1 This embodiment provides a method for preparing a semiconductor device. Figure 1 As shown, the semiconductor device manufacturing method includes a transistor structure forming step, a shallow trench forming step, a stress covering layer preparation step, an electrical isolation structure forming step and a contact hole forming step which are performed in sequence.

[0044] like Figure 2 As shown, the transistor forming steps include the preparation of the transistor structure, which includes, in sequence, a gate dielectric layer process, a gate process, an inner sidewall process, a lightly doped ion implantation process, an outer sidewall process, a source-drain ion implantation process, and a Salicide process.

[0045] In the gate dielectric layer process, an oxide layer is deposited on the surface of the substrate, and then ion implantation is performed on the wafer to form a double-well region in the substrate area below the oxide layer. The oxide layer on the upper surface of the double-well region is removed, and then an oxide layer with a thickness of about 55A is re-deposited on the surface of the double-well region to serve as the gate dielectric layer 1-2. The wafer structure obtained is as follows: Figure 3 As shown. Figure 3 In the embodiment, the double well region includes a first well region 1-11 and a second well region 1-12 adjacent to each other, the first well region 1-11 is an N well, and the second well region 1-12 is a P well. Figure 3 Indicates.

[0046] In the gate process, a gate is formed on the surface of the gate dielectric layer. The gate process specifically includes the following operations: S1. On the surface of the gate dielectric layer 1-2, a polysilicon gate material layer 2-1 covering the gate dielectric layer, a first oxide layer 2-2, a Si3N4 thin film layer 2-3, a second oxide layer 2-4, an amorphous carbon layer 2-5, an ARC anti-reflection layer 2-6, and a BARC bottom anti-oxidation layer 2-7 are sequentially arranged. Figure 4 shown.

[0047] S2. A photoresist and a mask are disposed on the surface of the BARC bottom anti-oxidation layer 2 - 7 at a position corresponding to the molded gate 2 , and the pattern of the mask matches the position where the photoresist is disposed.

[0048] S3. Remove the polysilicon gate material layer 2-1, the first oxide layer 2-2, the Si3N4 thin film layer 2-3, the second oxide layer 2-4, the amorphous carbon layer 2-5, the ARC anti-reflective layer 2-6, and the BARC bottom anti-oxidation layer 2-7 except for the position corresponding to the gate 2 by lithography technology; S4. Remove the mask 2-8, and remove the remaining portion of the second oxide layer 2-4, the amorphous carbon layer 2-5, the ARC anti-reflection layer 2-6, and the BARC bottom anti-oxidation layer 2-7 above the polysilicon gate material remaining on the surface of the gate dielectric layer 1-2, so that the polysilicon gate material remaining on the surface of the gate dielectric layer 1-2 is used as the gate 2, and the wafer structure obtained is as follows: Figure 5 shown.

[0049] In the inner wall process, the following operations are specifically included: S1. First, a SiO2 thin film layer is generated on the side of the gate 2; S2. Then remove the Si3N4 thin film structure originally belonging to the Si3N4 thin film layer 2-3 on the upper surface of the gate 2; S3. Depositing a Si3N4 thin film layer on the surface of the double well region to completely cover the outer surface of the gate 2; S4. Remove the Si3N4 thin film layer except for the area covering the side of the gate, thereby forming a stacked SiO2 thin film layer and a Si3N4 thin film layer on the side of the gate, and these two thin film layers together constitute the second sidewall structure 3-2, such as Figure 6 shown.

[0050] like Figure 7 In the lightly doped ion implantation process, an ion implantation process is used to form a diffusion region in the well region below the boundary of the gate. Specifically, an ion implantation process is performed on the first well region 1-11 to sequentially implant Ge, C, AS, and BF2 into the first well region 1-11 to form a PLDD region 1-3, and an ion implantation process is performed on the second well region 1-12 to sequentially implant Ge, C, B, N, P, and AS into the second well region to form a NLDD region 1-4.

[0051] In the outer sidewall process, referring to the inner sidewall process, a SiO2 thin film layer and a Si3N4 thin film layer are sequentially stacked on the surface of the second sidewall structure 3-2 on the side of the gate, and these two thin film layers together constitute the first sidewall structure 3-1. Figure 7 shown.

[0052] In the source-drain ion implantation process, the source region and the drain region are formed below the boundary of the gate by using the ion implantation process. The first well region 1-11 is implanted with Ge, B, and BF2 in sequence in the first well region 1-11 to form the source region and the drain region of the PMOS tube, which are marked as p+ heavily doped regions 1-5, and the second well region 1-12 is implanted with P, Ge, P, As, and F in sequence in the second well region to form the source region and the drain region of the NMOS tube, which are marked as n+ heavily doped regions 1-6.

[0053] In the Salicide process, a metal silicide capping layer 3 - 3 is formed on the surfaces of the gate 2 , the p+ heavily doped regions 1 - 5 , and the n+ heavily doped regions 1 - 6 .

[0054] After the transistor forming step is completed, the wafer structure obtained is as follows Figure 8 As shown. Figure 3 to Figure 8 In the figure, it can be clearly seen that after the first well region 1-11 and the second well region 1-12 are formed, until the transistor forming step is completed, the first well region 1-11 and the second well region 1-12 always remain uninterruptedly connected. In fact, before the shallow trench 4 is formed, the first well region 1-11 and the second well region 1-12 always remain uninterruptedly connected.

[0055] When the first well region 1-11 and the second well region 1-12 are in an uninterrupted connection state, the area near the boundary between the first well region 1-11 and the second well region 1-12 is doped with trap ions (called "boundary trap ions"). The presence of boundary trap ions inhibits the diffusion of trap ions in other areas of the first well region 1-11 / the second well region 1-12 to the above boundary, reduces the diffusion dose of trap ions to the above boundary, and thus widens the area where the trap ions in the first well region 1-11 and the second well region 1-12 are uniformly doped. As described above, since the first well region and the second well region are always in uninterrupted connection, based on this, it is beneficial for the first well region 1-11 and the second well region 1-12 to maintain good uniformity of trap ion doping even after multiple annealings during the preparation of the transistor structure.

[0056] In the shallow trench forming step, the shallow trench is formed by combining lithography technology with dry etching. In this embodiment, the shallow trench forming step specifically includes the following operations: S1. Fill the surface of the wafer structure with a carbon-containing polymer to form a flat carbon coating (ODL layer 4-1), then sequentially set a bottom anti-reflection layer 4-2 and a photoresist layer 4-3 on the surface of the ODL layer 4-1, and form a notch corresponding to the preset position of the shallow trench 4 in the photoresist layer by lithography technology, such as Fig. 9 .

[0057] S2. Further dry etching is performed along the formed gap to complete the formation of the shallow trench 4, and finally the ODL layer 4-1, the bottom anti-reflection layer 4-2 and the photoresist layer 4-3 are removed. The shallow trench 4 is formed as shown in FIG. Fig.10 shown.

[0058] S3. The inner groove wall of the shallow groove 4 is subjected to in-situ oxidation treatment by using an ISSG process (In-Situ Steam Generation), so as to form an oxide protective layer 4-4 on the inner groove wall surface of the shallow groove 4, such as Fig.11 The above-mentioned oxide protection layer 4-4 can repair the damage to the inner wall surface of the shallow trench 4 caused by the etching operation involved in the shallow trench forming step.

[0059] To a certain extent, after the transistor forming step is completed, the well ion doping concentration of the area near the boundary between the first well region 1-11 and the second well region 1-12 that is kept uninterruptedly connected may still be slightly higher than the well ion doping concentration of other areas of the first well region 1-11 and the second well region 1-12. However, when entering the shallow trench forming step, by etching the boundary between the first well region 1-11 and the second well region 1-12 to form the shallow trench 4, the area with a higher well ion doping concentration is removed by the above etching operation. Therefore, after forming the shallow trench 4, with respect to the first well region 1-11 and the second well region 1-12 that are still retained in the device, the doped well ions can be evenly distributed in the well region to which they belong, thereby suppressing the threshold voltage drop of the semiconductor device.

[0060] Next, a stress covering layer preparation step is performed, and the stress covering layer preparation step includes a tensile stress covering area preparation process, a compressive stress covering area preparation process, and an annealing treatment. The compressive stress covering area preparation process includes the following operations: a Si3N4 film is prepared as a compressive stress covering layer 5-1 on the surface of the first well region 1-11 by a PECVD process with a dual-frequency radio frequency power supply, using SiH4, NH3, H2 and Ar as film-forming raw materials, and the compressive stress covering layer 5-1 covers the transistor structure located in the first well region 1-11 and the inner groove wall surface area of ​​the shallow trench 4 adjacent to the edge of the first well region 1-11. The tensile stress covering area preparation process includes the following operations: SiH4 and NH3 are used as film-forming raw materials to prepare Si3N4 thin film as tensile stress covering layer 5-2 on the surface of the second well area 1-12 by PECVD process directly above the second well area 1-12, and the tensile stress covering layer 5-2 thus obtained covers the transistor structure located in the second well area 1-12 and the inner groove wall surface area of ​​the shallow groove 4 adjacent to the edge of the second well area 1-12. Finally, the wafer structure with the stress covering layer is annealed, and the compressive stress covering layer 5-1 transmits compressive stress to the transistor structure of the first well area 1-11 and the inner groove wall surface area of ​​the shallow groove 4 covered by it (the direction of action of the compressive stress is as shown in FIG. Fig.12 The tensile stress covering layer 5-2 transmits tensile stress to the transistor structure of the second well region 1-12 covered by it and the inner wall surface area of ​​the shallow trench 4 (the direction of tensile stress is shown in FIG. Fig.12 (as indicated by the direction of the arrow marked below the medium tensile stress covering layer 5-2).

[0061] Based on the stress memory effect, the stress covering layer transfers the stress to the area it covers through annealing treatment, and the stress will be directly memorized by these areas, so that the effective mass and scattering probability of the electron conductivity along the shallow groove 4 direction can be reduced, thereby effectively improving the carrier mobility and the speed of the semiconductor device. In the above scheme, since the stress covering layer directly covers the inner groove wall surface of the shallow groove 4, the stress of the stress covering layer can be more fully transferred to the shallow groove 4. On the other hand, the stress covering layer can also act as an etching barrier layer, which plays a role in surface protection of the transistor and the shallow groove 4, and can prevent the trap ions in the area near the boundary of the shallow groove 4 from diffusing into the shallow groove 4, which is conducive to further improving the uniformity of the trap ion doping of the first well region 1-11 and the second well region 1-12, and plays a role in regulating the threshold voltage of the semiconductor device. In summary, the setting of the above stress covering layer can play a role equivalent to the stress memory technology (Street Memorization Technique, SMT) for the device, so there is no need to perform additional SMT treatment during the device processing, the process flow is simplified, and the performance of the semiconductor device can be improved.

[0062] Then, the wafer structure obtained after the stress covering layer preparation step is processed by the electrical isolation structure forming step. The electrical isolation structure forming step specifically includes the following operations: depositing isolation oxide (tetraethoxysilane, TEOS) on the surface of the dual-well region of the wafer structure, a portion of the isolation oxide fills the inside of the shallow trench 4 to form a shallow trench isolation structure 6-1, and a portion of the isolation oxide fills the gap between the transistor structures, gradually forming an electrical isolation layer 6-2 (HarpTEOS), and then continuing to deposit isolation oxide to thicken the electrical isolation layer 6-2 (PE TEOS), and then planarizing the electrical isolation layer 6-2 obtained after the above operation through a CMP process, and adjusting its thickness to about 2100A, and then continuing to deposit isolation oxide to thicken the electrical isolation layer 6-2 (Recap TEOS), until the thickness of the electrical isolation layer 6-2 reaches about 2700A, thereby completing the preparation of the electrical isolation layer 6-2. The wafer structure obtained after the electrical isolation structure forming step is as shown Fig.13 shown.

[0063] In the step of forming the electrical isolation structure, the shallow trench isolation structure 6-1 and the electrical isolation layer 6-2 are formed at one time by depositing an isolation oxide, which is equivalent to integrating the STI process for preparing the shallow trench isolation structure and the ILD process for preparing the electrical isolation layer in the prior art into a one-step process, which not only simplifies the process steps, but also reduces the process cost and improves the economic benefits of the process. Based on the above process characteristics, in the wafer structure thus obtained, the shallow trench isolation structure 6-1 and the electrical isolation layer 6-2 are formed in one piece.

[0064] Next, the wafer structure is subjected to a contact hole forming step, specifically comprising forming a through hole 7-1 perpendicular to the substrate in the electrical isolation layer 6-2, and filling the through hole with tungsten 7-2, to obtain a contact hole 7-1. Fig.14 Finally, the wafer structure is subjected to the back-end process to complete the preparation of the semiconductor device.

[0065] In actual situations, a semiconductor device sample can be obtained by preparing a sample after a series of processes of semiconductor device processing are completed, and then the threshold voltage of the semiconductor device sample is measured. If the threshold voltage measured by the sample deviates from the preset value, it can be considered that in the process of preparing the semiconductor device by the same process, after the preparation of the oxide protection layer 4-4 is completed in the groove forming step, an ion implantation process is performed on the first well region 1-11 and the second well region 1-12 adjacent to the shallow groove 4 at the location of the shallow groove 4, and then the stress cover layer preparation step is performed, so that the threshold voltage of the semiconductor device thus prepared is less than the preset value. If the threshold voltage measured by the sample is basically at the same level as the preset value through testing the sample, there is no need to perform the above-mentioned additional ion implantation operation.

[0066] In this embodiment, based on the stress covering layer preparation steps adopted, in the semiconductor device prepared, the transistor structure located in the first well region 1-11 (recorded as P-type transistor structure 1-7) and the inner groove wall surface area of ​​the shallow groove 4 adjacent to the edge of the first well region 1-11 are covered by the compressive stress covering layer 5-1, and the transistor structure located in the second well region 1-12 (recorded as N-type transistor structure 1-8) and the inner groove wall surface area of ​​the shallow groove 4 adjacent to the edge of the second well region 1-12 are covered by the tensile stress covering layer 5-2. For clear display, in the process of preparing the semiconductor device in Example 1, the top view cross-sectional visual schematic diagram of the wafer structure obtained after the stress covering layer preparation step is completed is as follows Fig.15 shown.

[0067] In other specific implementations, a semiconductor device is prepared by referring to the above method provided in this embodiment, and the preparation of the stress covering layer may be omitted according to actual conditions.

[0068] Example 2 This embodiment prepares a semiconductor device with reference to the semiconductor device preparation method adopted in Embodiment 1. In the operation of preparing the semiconductor device in this embodiment, the difference from Embodiment 1 is that in the stress covering layer preparation step, this embodiment prepares a tensile stress covering layer 5-2 covering the first well region 1-11 and the second well region 1-12 on the surface of the first well region 1-11 and the second well region 1-12, so that the surface of the P-type transistor structure 1-7 located in the first well region 1-11, the surface of the N-type transistor structure 1-8 located in the second well region 1-12, and the inner groove wall surface of the shallow trench 4 located at the interface between the first well region 1-11 and the second well region 1-12 are all covered by the tensile stress covering layer 5-2, wherein the process of preparing the tensile stress covering layer 5-2 in this embodiment is consistent with the process of preparing the tensile stress covering region recorded in Embodiment 1. Except for the above differences, the other operations of preparing the semiconductor device in this embodiment are consistent with the corresponding operations in Embodiment 1.

[0069] For the purpose of clear demonstration, a top view cross-sectional visual diagram of the wafer structure obtained after the stress cover layer preparation step is completed in this embodiment is shown in FIG. Fig.16 shown.

[0070] Example 3 This embodiment prepares a semiconductor device with reference to the semiconductor device preparation method adopted in Embodiment 1. In the operation of preparing the semiconductor device in this embodiment, the difference from Embodiment 1 is that in the step of preparing the stress covering layer, this embodiment forms a stress covering layer on the side surface and top surface extending in the W direction of the P-type transistor structure 1-7 located in the first well region 1-11, the side surface and top surface extending in the W direction of the N-type transistor structure 1-8 located in the second well region 1-12, and the inner groove wall surface of the shallow trench 4 located at the interface between the first well region 1-11 and the second well region 1-12. A compressive stress covering layer 5-1 is formed on the surface, and a tensile stress covering layer 5-2 is formed on the side surface extending along the L direction of the P-type transistor structure 1-7 located in the first well region 1-11 and the side surface extending along the L direction of the N-type transistor structure 1-8 located in the second well region 1-12, wherein the process of preparing the compressive stress covering layer 5-1 in this embodiment is consistent with the process of preparing the compressive stress covering area recorded in Example 1, and the process of preparing the tensile stress covering layer 5-2 in this embodiment is consistent with the process of preparing the tensile stress covering area recorded in Example 1. Except for the above differences, other operations of preparing the semiconductor device in this embodiment are consistent with the corresponding operations in Example 1.

[0071] For the purpose of clear demonstration, a top view cross-sectional visual diagram of the wafer structure obtained after the stress cover layer preparation step is completed in this embodiment is shown in FIG. Fig.17 As shown. Fig.17In the plane parallel to the substrate, the arrangement direction of the adjacent first well regions 1-11 and second well regions 1-12 is the L direction, and the direction perpendicular to the L direction is the W direction.

[0072] Example 4 This embodiment prepares a semiconductor device with reference to the semiconductor device preparation method adopted in Embodiment 1. In the operation of preparing the semiconductor device in this embodiment, the difference from Embodiment 1 is that in the stress covering layer preparation step, this embodiment forms a compressive stress covering layer 5-1 on the side surface and top surface of the P-type transistor structure 1-7 located in the first well region 1-11 extending in the W direction and the inner groove wall surface area of ​​the shallow trench 4 adjacent to the edge of the first well region 1-11, and forms a tensile stress covering layer 5-2 on the side surface of the P-type transistor structure 1-7 located in the first well region 1-11 extending in the L direction, the surface of the N-type transistor structure 1-8 located in the second well region 1-12, and the inner groove wall surface area of ​​the shallow trench 4 adjacent to the edge of the second well region 1-12, wherein the process of preparing the compressive stress covering layer 5-1 in this embodiment is consistent with the process of preparing the compressive stress covering area recorded in Embodiment 1, and the process of preparing the tensile stress covering layer 5-2 in this embodiment is consistent with the process of preparing the tensile stress covering area recorded in Embodiment 1. Except for the above differences, other operations of preparing the semiconductor device in this embodiment are consistent with the corresponding operations in Embodiment 1.

[0073] For the purpose of clear demonstration, a top view cross-sectional visual diagram of the wafer structure obtained after the stress cover layer preparation step is completed in this embodiment is shown in FIG. Fig.18 As shown. Fig.18 In the plane parallel to the substrate, the arrangement direction of the adjacent first well regions 1-11 and second well regions 1-12 is the L direction, and the direction perpendicular to the L direction is the W direction.

[0074] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the protection scope of the present invention. Although the present invention is described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the technical solutions of the present invention can be modified or equivalently replaced, but these modifications or replacements are all within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The semiconductor device manufacturing method comprises the following steps performed in sequence: (1) a transistor structure forming step, (2) a shallow trench forming step, and (3) an electrical isolation structure forming step; The transistor preparation step includes the following operations: providing a substrate, performing an ion implantation process on the substrate to form a double-well region, and preparing a transistor structure in the double-well region; the double-well region includes a first well region and a second well region adjacent to each other, the first well region is of a first conductivity type, the second well region is of a second conductivity type, and before the shallow trench forming step is performed, the first well region and the second well region are always kept in uninterrupted connection; The shallow trench forming step includes the following operations: forming a shallow trench at a boundary between the first well region and the second well region, wherein the shallow trench is a groove for preparing a shallow trench isolation structure; The step of forming the electrical isolation structure includes the following operations: depositing an isolation oxide on the surface of the dual well region, at least a portion of the isolation oxide filling the interior of the shallow trench to form a shallow trench isolation structure, and at least a portion of the isolation oxide covering the transistor structure to form an electrical isolation layer on the surface of the transistor structure.

2. The method for preparing a semiconductor device according to claim 1, wherein: A stress covering layer preparation step is also provided between the shallow trench forming step and the electrical isolation structure forming step; The stress covering layer preparation step comprises the following operations: S1. forming a stress covering layer on the surface of the double well region, so that the surface of the transistor structure and the inner wall surface of the shallow trench are covered by the stress covering layer; S2. Performing annealing treatment on the device provided with the stress covering layer.

3. A semiconductor device manufactured by the semiconductor device manufacturing method according to any one of claims 1 or 2.

4. A semiconductor device, characterized in that: The semiconductor device comprises a substrate, a double well region, a transistor structure, and an isolation oxide, wherein the double well region is arranged on the surface of the substrate, the double well region comprises a first well region and a second well region adjacent to each other, the first well region is of a first conductivity type, the second well region is of a second conductivity type, a groove is arranged at the junction of the first well region and the second well region, and the groove is a shallow trench; At least a portion of the isolation oxide fills the interior of the shallow trench, and the portion of the isolation oxide forms a shallow trench isolation structure; At least a portion of the isolation oxide covers the surface of the transistor structure, and the portion of the isolation oxide forms an electrical isolation layer; The shallow trench isolation structure and the electrical isolation layer are integrally formed.

5. The semiconductor device according to claim 4, wherein: The semiconductor device also includes a stress covering layer, which is arranged between the inner groove wall of the shallow trench and the shallow trench isolation structure filling the shallow trench, and between the transistor structure and the electrical isolation layer covering it.

6. The semiconductor device according to claim 5, wherein: An oxide protection layer is also provided between the inner groove wall of the shallow groove and the stress covering layer.

7. The semiconductor device according to claim 5, wherein: The stress covering layer includes at least one of a tensile stress covering area and a compressive stress covering area. The tensile stress covering area transfers tensile stress to the area covered by it after annealing treatment, and the compressive stress covering area transfers compressive stress to the area covered by it after annealing treatment.

8. The semiconductor device according to claim 7, wherein: The stress covering layer includes the tensile stress covering region, the transistor structure includes an N-type transistor structure, and at least a portion of the stress covering layer covering the surface of the N-type transistor structure is the tensile stress covering region.

9. The semiconductor device according to claim 7, wherein: Satisfy at least one of the following a, b, c, d, e: a. The transistor structure includes an N-type transistor structure, the N-type transistor structure includes an N-type transistor structure I, and the stress covering layer covering the surface of the N-type transistor structure I is the tensile stress covering area; b. The transistor structure includes a P-type transistor structure, the P-type transistor structure includes a P-type transistor structure I, and the stress covering layer covering the surface of the P-type transistor structure I is the compressive stress covering area; c. the transistor structure comprises an N-type transistor structure, the N-type transistor structure comprises an N-type transistor structure II, and the stress covering layer covering the side surface of the N-type transistor structure II comprises the tensile stress covering region and the compressive stress covering region; d. The transistor structure includes a P-type transistor structure, the P-type transistor structure includes a P-type transistor structure II, and the stress covering layer covering the side surface of the P-type transistor structure II includes the tensile stress covering region and the compressive stress covering region; e. The transistor structure includes a P-type transistor structure, the P-type transistor structure includes a P-type transistor structure III, and the stress covering layer covering the surface of the P-type transistor structure III is the tensile stress covering area.

10. The semiconductor device according to claim 9, wherein: On a plane parallel to the substrate, an arrangement direction of the adjacent first well regions and the second well regions is defined as an L direction, and a direction perpendicular to the L direction is defined as a W direction; The semiconductor device satisfies at least one of the following f and g: f. The semiconductor device satisfies the above condition c, wherein the stress covering layer covering the side surface of the N-type transistor structure II includes a longitudinal covering layer extending along the L direction and a transverse covering layer extending along the W direction, the longitudinal covering layer is the tensile stress covering area, and the transverse covering layer is the compressive stress covering area; g. The semiconductor device satisfies d, and the stress covering layer covering the side surface of the P-type transistor structure II includes a longitudinal covering layer extending along the L direction and a transverse covering layer extending along the W direction, the longitudinal covering layer is the tensile stress covering area, and the transverse covering layer is the compressive stress covering area.

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