Preparation method of hybrid bonding structure and semiconductor device

Abstract

The invention provides a preparation method of a hybrid bonding structure and a semiconductor device, and the method comprises the steps: providing at least two to-be-bonded structures, and enabling the top of each to-be-bonded structure to comprise a dielectric layer and a metal lead-out structure which penetrates through the dielectric layer in a first direction perpendicular to the top surface of the dielectric layer; executing a first chemical mechanical polishing process to enable the top surface of the metal lead-out structure to protrude out of the top surface of the dielectric layer; executing a second chemical mechanical polishing process to enable the two ends of the metal lead-out structure to be flush with the top surface of the dielectric layer and enable the top surface of the metal lead-out structure to form a dish-shaped recess; performing plasma processing on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain an intermediate bonding structure; and carrying out hybrid bonding on the at least two middle bonding structures to form a hybrid bonding structure. According to the method, an unbonded area and bubbles are prevented from being formed in the bonding process, and the yield of hybrid bonding is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a preparation method of a hybrid bonding structure and a semiconductor device. Background Art

[0002] As the development of ultra-large-scale integrated circuits approaches the physical limit, three-dimensional integrated circuits, which have advantages in both physical size and cost, are an effective way to extend Moore's Law and solve advanced packaging problems. Among them, hybrid bonding technology can realize the internal interconnection of thousands of chips while bonding two wafers, which can greatly improve chip performance and save costs.

[0003] The difficulty of hybrid bonding technology lies in achieving internal metal interconnection and maintaining a high yield of such interconnection. Since hybrid bonding technology interconnects multiple chips on a wafer at the same time, and there is a height difference in the bonding interface, in which the metal in one area is higher than the bonding interface, resulting in bonding failure and forming an un-bonded area, and the metal in another area is lower than the bonding interface, resulting in bubbles after bonding. Both of these lead to a reduction in the yield of hybrid bonding. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a hybrid bonding structure and a semiconductor device to address the problems in the above-mentioned background technology, which can at least avoid the formation of unbonded areas and bubbles during hybrid bonding and improve the yield of hybrid bonding.

[0005] To achieve the above-mentioned and other related purposes, one aspect of the present application provides a method for preparing a hybrid bonding structure, comprising the following steps:

[0006] Providing at least two structures to be bonded, wherein the top of the structures to be bonded comprises a dielectric layer, and a metal lead-out structure penetrating the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer;

[0007] Performing a first chemical mechanical polishing process to make the top surface of the metal lead-out structure protrude from the top surface of the dielectric layer;

[0008] Performing a second chemical mechanical polishing process to make both ends of the metal lead-out structure flush with the top surface of the dielectric layer and to form a dish-shaped depression on the top surface of the metal lead-out structure;

[0009] Performing plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain an intermediate bonding structure;

[0010] At least two of the intermediate bonding structures are hybrid-bonded to form a hybrid bonding structure.

[0011] In one embodiment, during the execution of the first chemical mechanical polishing process, the removal rate of the dielectric layer is greater than the removal rate of the metal lead-out structure; during the execution of the second chemical mechanical polishing process, the removal rate of the metal lead-out structure is greater than the removal rate of the dielectric layer.

[0012] In one embodiment, the selection ratio of the first polishing liquid of the first chemical mechanical polishing process to the dielectric layer and the metal lead-out structure ranges from 5:1 to 7:1, and the selection ratio of the second polishing liquid of the second chemical mechanical polishing process to the dielectric layer and the metal lead-out structure ranges from 2:1 to 4:1; the selection ratio of the first polishing liquid to the dielectric layer and the metal lead-out structure is higher than the selection ratio of the second polishing liquid to the dielectric layer and the metal lead-out structure.

[0013] In one embodiment, the H2O2 content in the first polishing liquid of the first chemical mechanical polishing process is not higher than 0.8%, and the H2O2 content in the second polishing liquid of the second chemical mechanical polishing process is not lower than 1.2%; the H2O2 content in the second polishing liquid is higher than the H2O2 content in the first polishing liquid.

[0014] In one embodiment, the dielectric layer includes a first tetraethyl orthosilicate layer, a nitrogen-doped silicon carbide layer, and a second tetraethyl orthosilicate layer stacked in sequence along the first direction, and the first chemical mechanical polishing process is used to remove the second tetraethyl orthosilicate layer and remove a portion of the nitrogen-doped silicon carbide layer.

[0015] In one embodiment, performing plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain the intermediate bonding structure includes: performing plasma treatment on the top surface of the dielectric layer to form an open chemical bond for bonding on the top surface of the dielectric layer; and performing plasma treatment on the top surface of the metal lead-out structure to adjust the depth of the dished recess.

[0016] In one embodiment, the height of the top surface of the metal lead-out structure protruding from the top surface of the dielectric layer ranges from 300 angstroms to 400 angstroms, and the depth of the dished recess ranges from 10 angstroms to 30 angstroms.

[0017] In one embodiment, after the hybrid bonding structure is formed, the following step is further included: performing annealing treatment on the hybrid bonding structure to expand the metal lead-out structure and fill the dished recess.

[0018] In one embodiment, the polishing speeds of the first chemical mechanical polishing process and the second chemical mechanical polishing process are 30 rpm to 80 rpm.

[0019] Another aspect of the present application further provides a hybrid bonding structure, which is prepared by any of the above hybrid bonding structure preparation methods.

[0020] According to the preparation method of the hybrid bonding structure and the semiconductor device provided by the present invention, the unexpected technical effect of the present application is: for a bonding interface with a height difference, firstly, the top surface of the metal lead-out structure is made to protrude from the top surface of the dielectric layer through a first chemical mechanical polishing process, and then the two ends of the metal lead-out structure are made flush with the top surface of the dielectric layer through a second chemical mechanical polishing process, thereby avoiding the formation of an unbonded area in the subsequent bonding process. At the same time, the top surface of the metal lead-out structure is formed into a dish-shaped depression through the second chemical mechanical polishing process and the depth of the dish-shaped depression is controlled to ensure that the dish-shaped depression is filled after the hybrid bonding structure is formed, thereby avoiding the formation of a bubble area and improving the yield of the hybrid bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to better describe and illustrate the embodiments and / or examples of those applications disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, and the best modes of these applications currently understood.

[0022] Figure 1 A schematic diagram of a process for preparing a hybrid bonding structure provided in an embodiment;

[0023] Figure 2 It is a schematic diagram of the cross-sectional structure of a structure obtained after a metal lead-out structure is formed in a method for preparing a hybrid bonding structure provided in an embodiment;

[0024] Figure 3 A schematic diagram of a cross-sectional structure of a structure obtained after a first chemical mechanical polishing process is performed in a method for preparing a hybrid bonding structure provided in an embodiment;

[0025] Figure 4 It is a schematic diagram of the cross-sectional structure of a structure obtained after performing a second chemical mechanical polishing process in a method for preparing a hybrid bonding structure provided in an embodiment;

[0026] Figure 5 A schematic cross-sectional structure diagram of performing plasma treatment in a method for preparing a hybrid bonding structure provided in an embodiment;

[0027] Figure 6 A schematic cross-sectional structure diagram of a structure obtained after hybrid bonding is performed in a method for preparing a hybrid bonding structure provided in an embodiment;

[0028] Figure 7The cross-sectional structure schematic diagram of a structure obtained after annealing is performed in a method for preparing a hybrid bonding structure provided in an embodiment.

[0029] Description of reference numerals:

[0030] 100, wafer; 110, dielectric layer; 110a, first tetraethyl orthosilicate layer; 110b, nitrogen-doped silicon carbide layer; 110c, second tetraethyl orthosilicate layer; 120, barrier layer; 130, metal lead structure. DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0034] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing, and the zones shown in the figures are schematic in nature, and their shapes are not intended to display the actual shapes of the zones of the device and are not intended to limit the scope of the application.

[0037] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0038] The difficulty of hybrid bonding technology lies in achieving internal metal interconnection and maintaining a high yield of such interconnection. Since hybrid bonding technology interconnects multiple chips on a wafer at the same time, and there is a height difference in the bonding interface, in which the metal in one area is higher than the bonding interface, resulting in bonding failure and forming an un-bonded area, and the metal in another area is lower than the bonding interface, resulting in bubbles after bonding. Both of these lead to a reduction in the yield of hybrid bonding.

[0039] In view of the above problems, the present invention provides a method for preparing a hybrid bonding structure, such as Figure 1 As shown, the following steps are included:

[0040] Step S101: providing at least two structures to be bonded, wherein the top of the structures to be bonded comprises a dielectric layer, and a metal lead-out structure penetrating the dielectric layer in a first direction perpendicular to the top surface of the dielectric layer;

[0041] Step S102: performing a first chemical mechanical polishing process to make the top surface of the metal lead-out structure protrude from the top surface of the dielectric layer;

[0042] Step S103: performing a second chemical mechanical polishing process to make both ends of the metal lead-out structure flush with the top surface of the dielectric layer, and to form a dish-shaped depression on the top surface of the metal lead-out structure;

[0043] Step S104: performing plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain an intermediate bonding structure;

[0044] Step S105: hybrid bonding is performed on at least two of the intermediate bonding structures to form a hybrid bonding structure.

[0045] In one embodiment, two wafers 100 are provided, and a plurality of chips are formed in each wafer 100. A dielectric layer 110 is formed on the top of each wafer 100, and a metal lead-out structure 130 is formed in the dielectric layer 110 and penetrates the dielectric layer in a first direction perpendicular to the top surface of the dielectric layer, so as to form two structures to be bonded.

[0046] In one embodiment, the dielectric layer 110 includes a first tetraethyl orthosilicate layer 110a (TEOS), a nitrogen-doped silicon carbide layer 110b (NDC), and a second tetraethyl orthosilicate layer 110c (TEOS) stacked sequentially on the wafer 100. Specifically, the thickness of the first tetraethyl orthosilicate layer 110a ranges from 4000Å to 6000Å, such as 4000Å, 5000Å, 6000Å, and preferably 5000Å. The thickness of the nitrogen-doped silicon carbide layer 110b ranges from 800Å to 1200Å, such as 800Å, 1000Å, 1200Å, and preferably 1000Å. The thickness of the second tetraethyl orthosilicate layer 110c ranges from 200Å to 400Å, such as 200Å, 300Å, 400Å, and preferably 300Å. The method of forming the first tetraethyl orthosilicate layer 110a, the nitrogen-doped silicon carbide layer 110b and the second tetraethyl orthosilicate layer 110c can adopt chemical vapor deposition (CVD), such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy (MBE).

[0047] In one embodiment, the metal lead-out structure 130 penetrates the dielectric layer 110 along a first direction perpendicular to the top surface of the dielectric layer 110. To form the metal lead-out structure 130, a photolithography process is first used to form a through hole penetrating the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer. Specifically, a patterned mask layer is formed on the dielectric layer 110, and the dielectric layer 110 is etched using the patterned mask layer as a mask until the surface of the wafer 100 is exposed, thereby forming a through hole penetrating the dielectric layer 110. The method for etching the dielectric layer 110 includes an anisotropic dry etching process, and the dry etching process includes but is not limited to: reactive ion etching (RIE), ion beam etching, plasma etching or laser ablation, and a single etching method can be used, or more than one etching method can be used. Next, a barrier layer 120 is formed on the bottom and sidewalls of the through hole. Specifically, a barrier layer 120 covering the top surface of the dielectric layer 110, the sidewall of the through hole and the bottom of the through hole can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The material of the barrier layer 120 includes but is not limited to tantalum (Ta), tantalum nitride (TaN), etc. Then, a metal material layer is formed to fill the through hole to form a metal lead-out structure 130 in the through hole, and the metal lead-out structure 130 is connected to the interconnection layer of the wafer chip. Specifically, a metal material layer covering the top surface of the dielectric layer 110 and filling the through hole can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The metal material layer includes but is not limited to copper. Then, chemical mechanical polishing (CMP) is used for bulk polishing to remove the metal material layer and the barrier layer 120 located on the top surface of the dielectric layer 110. Since a large amount of metal material needs to be removed in the bulk polishing stage, in order to speed up the removal speed, the chemical mechanical polishing adopts a high rotation speed, for example, greater than 80rpm, preferably 93rpm, 97rpm. However, high-speed grinding can easily lead to uneven grinding effects in different areas of the wafer. Figure 2 As shown, there is a height difference problem in the bonding interface of different areas. The top surface of a part of the metal lead-out structure 130 is higher than the top surface of the dielectric layer 110. If directly bonded, an un-bonded area will be formed. The top surface of another part of the metal lead-out structure 130 is lower than the top surface of the dielectric layer 110. If directly bonded, bubbles will be formed.

[0048] Next, execute step S102, referring to Figure 3 As shown, a first chemical mechanical polishing process is performed to make the top surface of the metal lead-out structure 130 protrude from the top surface of the dielectric layer 110 .

[0049] In one embodiment, during the first chemical mechanical polishing process, the removal rate of the dielectric layer 110 is made greater than the removal rate of the metal lead-out structure 130, so that the top surfaces of all the metal lead-out structures 130 protrude from the top surface of the dielectric layer 110. In order to achieve a removal rate of the dielectric layer 110 greater than the removal rate of the metal lead-out structure 130, the first polishing liquid of the first chemical mechanical polishing process has a selectivity range of 5:1 to 7:1 to the dielectric layer 110 and the metal lead-out structure 130, such as 5:1, 6:1 or 7:1, preferably 6:1. In order to achieve the above selectivity, the H2O2 content in the first polishing liquid of the first chemical mechanical polishing process is not higher than 0.8%, such as 0.6%, 0.7%, 0.8%, etc., preferably 0.8%.

[0050] In one embodiment, when the top surfaces of all metal lead-out structures 130 protrude from the top surface of the dielectric layer 110, the height of the metal lead-out structures 130 can be uniformed by mechanically polishing the top surfaces of the metal lead-out structures 130 at different heights through the first chemical mechanical polishing process. The polishing speed of the first chemical mechanical polishing process ranges from 30rpm to 80rpm, such as 30rpm, 50rpm, 80rpm, preferably 50rpm, 53rpm. By using a low speed in the first chemical mechanical polishing process, the polishing effect of different regions of the wafer can be made more uniform, not only achieving the top surface of the metal lead-out structure 130 protruding from the top surface of the dielectric layer 110, but also ensuring that the top surface of the metal lead-out structure 130 protrudes from the top surface of the dielectric layer 110 at the same or similar height.

[0051] Further, for the dielectric layer 110 composed of the first tetraethyl orthosilicate layer 110a, the nitrogen-doped silicon carbide layer 110b and the second tetraethyl orthosilicate layer 110c, the first chemical mechanical polishing process completely removes the first tetraethyl orthosilicate layer 110a and partially removes the nitrogen-doped silicon carbide layer 110b, and the thickness of the nitrogen-doped silicon carbide layer 110b removed is in the range of 150Å to 200Å. Thus, after the first chemical mechanical polishing process is performed, the height of the top surface of the metal lead-out structure 130 protruding from the top surface of the dielectric layer 110 ranges from 300Å to 400Å.

[0052] By performing the first chemical mechanical polishing process, the bonding interfaces with height differences existing in different regions of the wafer are all formed into bonding interfaces in which the top surface of the metal lead-out structure 130 protrudes from the top surface of the dielectric layer 110, and the height range of the metal lead-out structure 130 protruding from the dielectric layer 110 is controlled to be the same or similar. Although the bonding interface formed after performing the first chemical mechanical polishing process cannot be directly used for bonding, and direct bonding will lead to un-bonded problems, it achieves uniform processing of the bonding interface with height differences.

[0053] Next, execute step S103, referring to Figure 4 As shown, a second chemical mechanical polishing process is performed to make both ends of the metal lead-out structure flush with the top surface of the dielectric layer and to form a dish-shaped recess on the top surface of the metal lead-out structure.

[0054] In one embodiment, during the second chemical mechanical polishing process, the removal rate of the metal lead-out structure 130 and the dielectric layer 110 is greater than the removal rate of , so that the top surface of the metal lead-out structure 130 can be made flush with the top surface of the dielectric layer 110 at both ends by protruding from the top surface of the dielectric layer 110. In order to achieve a removal rate of the metal lead-out structure 130 and the dielectric layer 110 greater than the removal rate of , the selectivity of the second polishing liquid to the dielectric layer 110 and the metal lead-out structure 130 is lower than the selectivity of the first polishing liquid to the dielectric layer 110 and the metal lead-out structure 130. Specifically, the selectivity of the second polishing liquid in the second chemical mechanical polishing process to the nitrogen-doped silicon carbide layer 110b in the dielectric layer 110 and the metal lead-out structure 130 ranges from 2:1 to 4:1, for example, 2:1, 2.7:1, 3.8:1 or 4:1, preferably 2.7:1 or 3.8:1. In order to achieve the above selection ratio, the H2O2 content in the second polishing liquid is higher than the H2O2 content in the first polishing liquid, and the H2O2 content in the second polishing liquid of the second chemical mechanical polishing process is not less than 1.2%, for example, 1.2%, 1.3%, 1.4%, etc., preferably 1.2%.

[0055] In one embodiment, the grinding speed of the second chemical mechanical polishing process includes 30rpm~80rpm, such as 30rpm, 50rpm, 80rpm, preferably 50rpm, 53rpm. By using a low rotation speed in the second chemical mechanical polishing process, the grinding effect of different regions of the wafer can be made more uniform, not only to achieve that both ends of the metal lead-out structure 130 are flush with the top surface of the dielectric layer 110, but also to make the depth of the dish-shaped depression formed on the top surface of the metal lead-out structure 130 the same or similar. Specifically, the depth range of the dish-shaped depression includes 10Å~30Å, such as 10Å, 20Å, 30Å, etc.

[0056] By performing the second chemical mechanical polishing process, the situation where the top surface of the metal lead-out structure 130 in different regions of the wafer protrudes from the top surface of the dielectric layer 110 is eliminated, and the un-bonded problem in the subsequent bonding is avoided. The second chemical mechanical polishing process makes the two ends of the metal lead-out structure 130 flush with the top surface of the dielectric layer 110. It is to further uniformize the bonding interface with a high and low drop on the basis of the uniformization treatment of the bonding interface with a high and low drop in the first chemical mechanical polishing process. Its control accuracy is higher than that of the first chemical mechanical polishing step. Therefore, it can not only achieve the goal of making the two ends of the metal lead-out structure 130 flush with the top surface of the dielectric layer 110, but also control the depth range of the dished depression of the metal lead-out structure 130.

[0057] Next, execute step S104, referring to Figure 5 As shown, plasma treatment is performed on the top surface of the dielectric layer 110 and the top surface of the metal lead structure 130 to obtain an intermediate bonding structure. The plasma treatment is performed for: (1) performing plasma treatment on the top surface of the dielectric layer 110 to form an open chemical bond for bonding on the top surface of the dielectric layer 110; (2) performing plasma treatment on the top surface of the metal lead structure 130 to adjust the depth of the dished recess.

[0058] In one embodiment, the gas used for plasma treatment includes nitrogen, oxygen, hydrogen, etc. It is preferred to use nitrogen plasma to treat the top surface of the dielectric layer 110, and then use deionized water (DIW) to rinse the plasma-treated surface to form an open chemical bond (-OH) for bonding. Since the bonding performance of the NDC layer after plasma treatment is better than that of the TEOS layer after plasma treatment, the dielectric layer 110 adopts a stacked structure of a first tetraethyl orthosilicate layer 110a, a nitrogen-doped silicon carbide layer 110b, and a second tetraethyl orthosilicate layer 110c, and in step S102, the second tetraethyl orthosilicate layer 110c and a portion of the nitrogen-doped silicon carbide layer 110b are removed to expose the nitrogen-doped silicon carbide layer 110b as a bonding surface, which is plasma-treated for subsequent bonding.

[0059] In one embodiment, the depth of the dished depression can be adjusted by performing plasma treatment on the top surface of the metal lead-out structure 130. Before performing plasma treatment on the top surface of the metal lead-out structure 130, the depth of the dished depression on the top surface of the metal lead-out structure 130 is first measured. Specifically, the depth of the dished depression on the top surface of the metal lead-out structure 130 can be measured using an atomic force microscope (AFM). Then, the number of plasma treatments or the time of plasma treatment is determined based on the depth of the dished depression on the top surface of the metal lead-out structure 130. Specifically, the duration of each plasma treatment is about 10 seconds, and each plasma treatment can increase the depth of the dished depression on the top surface of the metal lead-out structure 130 by about 5Å. When the depth of the dished depression on the top surface of the metal lead-out structure 130 reaches a preset depth, for example, the dished depression depth is measured to be 20Å, then there is no need to adjust the depth of the dished depression on the top surface of the metal lead-out structure 130 by plasma treatment, and only one plasma treatment may be performed or the time of the plasma treatment may be set to 5s to 15s to form an open chemical bond for bonding on the top surface of the dielectric layer 110. When the depth of the dished depression on the top surface of the metal lead-out structure 130 does not reach the preset depth, for example, the depth of the dished depression is measured to be 5Å, two plasma treatments may be performed or the time of the plasma treatment may be set to 15s to 25s to further deepen the depth of the dished depression to a depth range of 10Å to 30Å. After performing the plasma treatment, the step of measuring the depth of the dished depression on the top surface of the metal lead-out structure 130 again may be included to confirm that the depth of the dished depression on the top surface of the metal lead-out structure 130 reaches the preset depth.

[0060] By performing plasma treatment, not only can a bonding interface with good bonding performance be formed, but also the bonding interface can be homogenized again on the basis of the homogenization treatment of the bonding interface by the first chemical mechanical polishing and the second chemical mechanical polishing. The control accuracy is higher than that of the first chemical mechanical polishing and the second chemical mechanical polishing steps. The top surface of the metal lead-out structure 130 is controlled again to ensure that both ends of the metal lead-out structure 130 are flush with the top surface of the dielectric layer 110, and the depth of the dished depression of the metal lead-out structure 130 is within a preset range.

[0061] Next, execute step S105, referring to Figure 6 As shown, at least two of the intermediate bonding structures are hybrid bonded to form a hybrid bonding structure.

[0062] In one embodiment, hybrid bonding of at least two intermediate bonding structures includes bonding metal lead structures of the two intermediate bonding structures to each other, and bonding dielectric layer regions to each other. Since the top surface of the metal lead structure 130 protrudes from the top surface of the dielectric layer 110 through the second chemical mechanical polishing process in step S103, the formation of un-bonded regions is avoided. However, since a dish-shaped groove is formed on the top surface of the metal lead structure 130, micro bubbles are formed in the hybrid bonding structure formed after hybrid bonding, such as Figure 6 Further, the bubbles can be eliminated by heat treating the hybrid bonding structure to form Figure 7 The structure shown. Specifically, annealing treatment is performed to expand the metal lead-out structure 130 to fill the dished depression. The temperature range of the annealing treatment includes 300°C to 400°C, such as 300°C, 350°C, 400°C, preferably 350°C. The time range of the annealing treatment includes 100min to 150min, such as 100min, 120min, 150min, preferably 120min. After the annealing treatment, the metal lead-out structure expands and fills the micro-bubbles formed by the dished depression, and the micro-bubbles are eliminated. In this embodiment, the depth of the dished depression is controlled by step S103 and step S104, so that the micro-bubbles formed by the dished depression are small enough to ensure that the thermal expansion of the metal caused by the annealing treatment can fill the dished depression to eliminate the micro-bubbles.

[0063] So far, the introduction of the relevant steps of the method for preparing the hybrid bonding structure of the embodiment of the present invention has been completed. It can be understood that the method for preparing the hybrid bonding structure of the present embodiment not only includes the above steps, but also may include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of the present embodiment.

[0064] The present invention further provides a semiconductor device, comprising a hybrid bonding structure, wherein the hybrid bonding structure can be prepared by the above-mentioned method for preparing the hybrid bonding structure.

[0065] like Figure 7 As shown, the hybrid bonding structure includes at least two intermediate bonding structures that are hybrid bonded to each other, the top of the intermediate bonding structure includes a dielectric layer, and a metal lead-out structure that penetrates the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer, wherein both ends of the metal lead-out structure in the intermediate bonding structure are flush with the top surface of the dielectric layer.

[0066] In one embodiment, the hybrid bonding structure includes two wafers 100, each of which has multiple chips formed therein. A dielectric layer 110 is formed on the top of each wafer 100, and a metal lead-out structure 130 is formed in the dielectric layer 110 and penetrates the dielectric layer in a first direction perpendicular to the top surface of the dielectric layer. The dielectric layer 110 includes a first tetraethyl orthosilicate layer 110a and a plasma-treated nitrogen-doped silicon carbide layer 110b sequentially stacked along the first direction on the wafer 100, wherein the plasma-treated nitrogen-doped silicon carbide layer 110b serves as a bonding interface.

[0067] In one embodiment, the metal lead-out structure 130 is connected to the interconnection layer of the wafer chip. The metal lead-out structure 130 includes but is not limited to copper. A barrier layer 120 is also formed between the metal lead-out structure 130 and the dielectric layer 110. The material of the barrier layer 120 includes but is not limited to tantalum (Ta) or tantalum nitride (TaN).

[0068] In one embodiment, in the hybrid bonding structure, the metal lead structures of the two intermediate bonding structures are bonded to each other, and the dielectric layer regions are bonded to each other. Both ends of the metal lead structures in the intermediate bonding structures are flush with the top surface of the dielectric layer, thereby avoiding the formation of un-bonded regions in the hybrid bonding structure.

[0069] The specific structure of the hybrid bonding structure can refer to the description of the corresponding part in the above text, and will not be repeated here for the sake of brevity.

[0070] According to the preparation method of the hybrid bonding structure and the semiconductor device provided by the present invention, for a bonding interface with a height difference, the top surface of the metal lead-out structure is first protruded from the top surface of the dielectric layer by a first chemical mechanical polishing process, and then the two ends of the metal lead-out structure are made flush with the top surface of the dielectric layer by a second chemical mechanical polishing process, thereby avoiding the formation of an unbonded area in a subsequent bonding process. At the same time, a dish-shaped depression is formed on the top surface of the metal lead-out structure by the second chemical mechanical polishing process and the depth of the dish-shaped depression is controlled to ensure that the dish-shaped depression is filled after the hybrid bonding structure is formed, thereby avoiding the formation of a bubble area and improving the yield of the hybrid bonding.

[0071] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0072] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0073] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a hybrid bonding structure, characterized in that: The following steps are involved: Providing at least two structures to be bonded, wherein the top of the structures to be bonded comprises a dielectric layer, and a metal lead-out structure penetrating the dielectric layer along a first direction perpendicular to the top surface of the dielectric layer; Performing a first chemical mechanical polishing process to make the top surface of the metal lead-out structure protrude from the top surface of the dielectric layer; Performing a second chemical mechanical polishing process to make both ends of the metal lead-out structure flush with the top surface of the dielectric layer and to form a dish-shaped depression on the top surface of the metal lead-out structure; Performing plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain an intermediate bonding structure; At least two of the intermediate bonding structures are hybrid-bonded to form a hybrid bonding structure.

2. The method for preparing a hybrid bonding structure according to claim 1, characterized in that: During the execution of the first chemical mechanical polishing process, a removal rate of the dielectric layer is greater than a removal rate of the metal lead-out structure; During the second chemical mechanical polishing process, a removal rate of the metal lead-out structure is greater than a removal rate of the dielectric layer.

3. The method for preparing a hybrid bonding structure according to claim 2, characterized in that: The selectivity of the first polishing liquid in the first chemical mechanical polishing process to the dielectric layer and the metal lead-out structure ranges from 5:1 to 7:1, and the selectivity of the second polishing liquid in the second chemical mechanical polishing process to the dielectric layer and the metal lead-out structure ranges from 2:1 to 4:1; The selectivity of the first polishing liquid to the dielectric layer and the metal lead-out structure is higher than the selectivity of the second polishing liquid to the dielectric layer and the metal lead-out structure.

4. The method for preparing a hybrid bonding structure according to claim 3, characterized in that: The H2O2 content in the first polishing liquid of the first chemical mechanical polishing process is not higher than 0.8%, and the H2O2 content in the second polishing liquid of the second chemical mechanical polishing process is not lower than 1.2%; The H2O2 content in the second polishing liquid is higher than the H2O2 content in the first polishing liquid.

5. The method for preparing a hybrid bonding structure according to claim 4, characterized in that: The dielectric layer includes a first tetraethyl orthosilicate layer, a nitrogen-doped silicon carbide layer, and a second tetraethyl orthosilicate layer stacked in sequence along the first direction, and the first chemical mechanical polishing process is used to remove the second tetraethyl orthosilicate layer and remove a portion of the nitrogen-doped silicon carbide layer.

6. The method for preparing a hybrid bonding structure according to claim 1, characterized in that: The performing plasma treatment on the top surface of the dielectric layer and the top surface of the metal lead-out structure to obtain the intermediate bonding structure comprises: performing plasma treatment on a top surface of the dielectric layer to form open chemical bonds for bonding on the top surface of the dielectric layer; and, Plasma treatment is performed on a top surface of the metal lead-out structure to adjust a depth of the dished recess.

7. The method for preparing a hybrid bonding structure according to claim 1, characterized in that: The height of the top surface of the metal lead-out structure protruding from the top surface of the dielectric layer ranges from 300 angstroms to 400 angstroms, and the depth of the dished depression ranges from 10 angstroms to 30 angstroms.

8. The method for preparing a hybrid bonding structure according to claim 7, characterized in that: After forming the hybrid bonding structure, the following steps are further included: The hybrid bonding structure is annealed to expand the metal lead structure and fill the dished recess.

9. The method for preparing a hybrid bonding structure according to claim 1, characterized in that: The polishing speeds of the first chemical mechanical polishing process and the second chemical mechanical polishing process range from 30 rpm to 80 rpm.

10. A semiconductor device, characterized in that: include: The hybrid bonding structure is prepared by the method for preparing a hybrid bonding structure according to any one of claims 1 to 9.

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