Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the same are disclosed. The semiconductor package includes: a first semiconductor chip; a second semiconductor chip on a top surface of the first semiconductor chip and having a width smaller than that of the first semiconductor chip; and a molding layer on the first semiconductor chip and surrounding the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first circuit layer on a top surface of the first semiconductor substrate. The first semiconductor substrate includes a first portion adjacent to a top surface of the first semiconductor substrate and a second portion adjacent to a bottom surface of the first semiconductor substrate. The first portion and the second portion include the same semiconductor material. The first portion has a single crystal structure. The second portion may have a polycrystalline structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0137914 filed on October 16, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a semiconductor package and a method for manufacturing the same, and more particularly to a stacked semiconductor package and a method for manufacturing the same. Background Art

[0004] In the semiconductor industry, integrated circuit packaging technology has been developed to meet the requirements for small-size devices and high package reliability. For example, packaging technology that can achieve chip-size packaging to meet the requirements for small-size devices is being actively developed, and packaging technology that can improve packaging process efficiency and improve the mechanical and electrical reliability of packaged products has attracted considerable attention in terms of high package reliability.

[0005] In the semiconductor industry, high-capacity, thin, and small-sized semiconductor packages and electronic products using them are required, so various packaging technologies have been proposed. One of the various packaging technologies is a packaging technology that vertically stacks multiple semiconductor chips to achieve high-density chip stacking. Compared with a conventional package consisting of one semiconductor chip, this packaging technology has the advantage of being able to integrate semiconductor chips with various functions on a small area. Summary of the invention

[0006] Provided are a method for manufacturing a semiconductor package that is less prone to failure and a semiconductor package manufactured by the method.

[0007] Furthermore, a method of manufacturing a semiconductor package with improved process efficiency and a semiconductor package manufactured by the method are provided.

[0008] According to one aspect of the present disclosure, a semiconductor package includes: a first semiconductor chip; a second semiconductor chip, on the top surface of the first semiconductor chip, the width of the second semiconductor chip is smaller than the width of the first semiconductor chip; and a molding layer, on the first semiconductor chip and surrounding the second semiconductor chip, wherein the first semiconductor chip includes: a first semiconductor substrate; and a first circuit layer, on the top surface of the first semiconductor substrate, wherein the first semiconductor substrate includes: a first part, adjacent to the top surface of the first semiconductor substrate; and a second part, adjacent to the bottom surface of the first semiconductor substrate, wherein the first part and the second part include semiconductor material, wherein the first part includes a single crystal structure, and wherein the second part includes a polycrystalline structure.

[0009] According to one aspect of the present disclosure, a semiconductor package includes: a first semiconductor chip; a second semiconductor chip on a top surface of the first semiconductor chip; a molding layer on the first semiconductor chip and surrounding the second semiconductor chip; a redistribution substrate on the molding layer and the second semiconductor chip; a conductive column vertically penetrating the molding layer and connecting the redistribution substrate to the first semiconductor chip; and an external terminal coupled to the redistribution substrate, wherein the first semiconductor chip includes: a first semiconductor substrate; a first circuit layer on a top surface of the first semiconductor substrate; and a first pad on a top surface of the first circuit layer, wherein the first semiconductor substrate includes a thermal shielding layer in the first semiconductor substrate, and wherein the thermal shielding layer is spaced apart from the top surface of the first semiconductor substrate by a distance of about 100 nanometers to about 500 nanometers.

[0010] According to one aspect of the present disclosure, a method for manufacturing a semiconductor package includes: setting a first semiconductor chip, the first semiconductor chip including a first semiconductor substrate and a first circuit layer on a top surface of the first semiconductor substrate; forming a heat shielding layer in the first semiconductor substrate; forming a conductive column coupled to the first circuit layer on the first semiconductor chip; setting a second semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second circuit layer on a top surface of the second semiconductor substrate; performing an annealing process to mount the second semiconductor chip on the first semiconductor chip; forming a molding layer on the first semiconductor chip, wherein the molding layer surrounds the second semiconductor chip; and forming a redistribution substrate on the molding layer and the second semiconductor chip, wherein the heat shielding layer and the first semiconductor substrate include semiconductor materials, wherein the first semiconductor substrate includes a single crystal structure, and wherein the heat shielding layer includes an amorphous structure or a polycrystalline structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0013] Figure 2 and Figure 3 It shows Figure 1 A diagram of the crystal structure of portion A shown;

[0014] Figure 4 , Figure 5 and Figure 6 is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure;

[0015] Figure 7 and Figure 8 It shows Figure 6 A diagram of the crystal structure of portion B is shown;

[0016] Fig. 9 is a cross-sectional view showing a semiconductor package according to one or more embodiments of the present disclosure; and

[0017] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 and Fig. 20 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] Now, the semiconductor package according to the present disclosure will be described below with reference to the accompanying drawings.

[0019] In the following description, the same reference numerals refer to the same elements throughout the specification. Depending on the embodiment, multiple "units", "modules", "elements" and "blocks" may be implemented as a single component, or a single "unit", "module", "element" and "block" may include multiple components.

[0020] It will be understood that when an element is referred to as being “connected to” another element, it can be directly or indirectly connected to the other element.

[0021] Furthermore, when a component “includes” or “comprises” an element, unless there is a specific description to the contrary, the component may further include other elements, rather than excluding other elements.

[0022] Throughout the description, when a member is “on” another member, this includes not only a case where the member is in contact with the other member but also a case where another member exists between the two members.

[0023] Here, the expressions "at least one of a, b or c" and "at least one of a, b and c" mean "only a", "only b", "only c", "both a and b", "both a and c", "both b and c" and "all of a, b and c".

[0024] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, the present disclosure should not be limited by these terms. These terms are only used to distinguish one element from another.

[0025] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0026] With respect to any method or process described herein, identification codes may be used to facilitate description, but are not intended to indicate the order of each step or operation. Each step or operation may be implemented in an order different from the order shown, unless the context clearly indicates otherwise.

[0027] Figure 1 is a cross-sectional view illustrating a semiconductor package according to one or more embodiments of the present disclosure. Figure 2 and Figure 3 It shows Figure 1 A diagram of the crystal structure of portion A is shown.

[0028] Reference Figure 1 , a redistribution substrate 100 may be provided. The redistribution substrate 100 may include one or more substrate wiring layers stacked on each other. Each substrate wiring layer may include a redistribution dielectric layer 110 and a redistribution conductive pattern 120 in the redistribution dielectric layer 110. When a plurality of substrate wiring layers are provided, the redistribution conductive pattern 120 of one substrate wiring layer may be electrically connected to the redistribution conductive pattern 120 of an adjacent substrate wiring layer. The redistribution dielectric layer 110 and the redistribution conductive pattern 120 of a single substrate wiring layer will be described below.

[0029] The redistribution dielectric layer 110 may include a photoimageable dielectric (PID). For example, the photoimageable dielectric may include at least one selected from photosensitive polyimide (PI), polybenzoxazole (PBO), phenolic polymer, and benzocyclobutene polymer. Alternatively, the redistribution dielectric layer 110 may include a dielectric material. For example, the redistribution dielectric layer 110 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a dielectric polymer.

[0030] The redistribution conductive pattern 120 may be disposed on the redistribution dielectric layer 110. The redistribution conductive pattern 120 may extend horizontally on the redistribution dielectric layer 110. The redistribution conductive pattern 120 may be a component for redistribution in the redistribution substrate 100. The redistribution conductive pattern 120 may include a conductive material. For example, the redistribution conductive pattern 120 may include copper (Cu) or aluminum (Al).

[0031] The redistribution conductive pattern 120 may have a damascene structure. For example, the redistribution conductive pattern 120 may have a head and a tail connected into a single integral piece. The head and the tail of the redistribution conductive pattern 120 may have an inverted T-shaped cross section.

[0032] The head of the redistribution conductive pattern 120 may be a wiring or pad portion for horizontal extension of the wiring line in the redistribution substrate 100. The head may be provided on the bottom surface of the redistribution dielectric layer 110. For example, the head may protrude onto the bottom surface of the redistribution dielectric layer 110. The redistribution conductive pattern 120 of the lowest substrate wiring layer may be exposed on the bottom surface of the lowest redistribution dielectric layer 110 or on the bottom surface of the redistribution substrate 100. The exposed redistribution conductive pattern 120 may be a substrate pad to which the external terminal 130 is coupled. Alternatively, the redistribution substrate 100 may be provided with a bump or pad coupled to the external terminal 130 on its bottom surface, and the pad may be coupled to the exposed redistribution conductive pattern 120.

[0033] The tail of the redistribution conductive pattern 120 may be a via portion for vertical connection of a wiring line in the redistribution substrate 100. The tail may be coupled to an overlying substrate wiring layer. For example, the tail of the redistribution conductive pattern 120 may extend from the top surface of the head and may penetrate the redistribution dielectric layer 110 to be coupled to the head of the redistribution conductive pattern 120 of the overlying substrate wiring layer. The tail of the redistribution conductive pattern 120 of the uppermost substrate wiring layer may penetrate the redistribution dielectric layer 110 to be exposed on the top surface of the redistribution substrate 100 or on the top surface of the redistribution dielectric layer 110 of the uppermost substrate wiring layer. The redistribution conductive pattern 120 of the uppermost substrate wiring layer may be electrically coupled to the first semiconductor chip 200 and the conductive pillar 450 to be discussed below.

[0034] The external terminal 130 may be disposed on the bottom surface of the redistribution substrate 100. The external terminal 130 may be coupled to the redistribution conductive pattern 120 of the lowermost substrate wiring layer. The external terminal 130 may include a solder ball or a solder bump, and based on the type and arrangement of the external terminal 130, the semiconductor package may be provided in the shape of one of a ball grid array (BGA) type, a fine ball grid array (FBGA) type, and a land grid array (LGA) type.

[0035] The first semiconductor chip 200 may be disposed on the redistribution substrate 100. The first semiconductor chip 200 may include an integrated element therein. For example, the first semiconductor chip 200 may be a wafer-level die formed of a semiconductor such as silicon (Si). The first semiconductor chip 200 may have a front surface and a rear surface. In the following description, the term "front surface" may be defined as indicating an active surface of an integrated element in a semiconductor chip, a surface on which a wiring line is formed, or a surface on which a pad of a semiconductor chip is formed, and the term "rear surface" may be defined as indicating a surface opposite to the front surface. The front surface of the first semiconductor chip 200 may face the redistribution substrate 100. For example, the first semiconductor chip 200 may be disposed on the redistribution substrate 100 in a face-down state.

[0036] The first semiconductor chip 200 may include a first semiconductor substrate 210 , a first circuit layer 220 , a first via 230 , and a redistribution layer 240 .

[0037] A first semiconductor substrate 210 may be provided. The first semiconductor substrate 210 may include a semiconductor material. For example, the first semiconductor substrate 210 may be a single crystal silicon substrate. The first semiconductor substrate 210 may have a top surface and a bottom surface opposite to each other. The bottom surface of the first semiconductor substrate 210 may be a front surface of the first semiconductor substrate 210, and the top surface of the first semiconductor substrate 210 may be a rear surface of the first semiconductor substrate 210. As used herein, the front surface of the first semiconductor substrate 210 may be defined as indicating a surface on which a semiconductor element is formed or mounted in the first semiconductor substrate 210, or a surface on which a wiring line and a pad are formed in the first semiconductor substrate 210, and the rear surface of the first semiconductor substrate 210 may be defined as indicating a surface opposite to the front surface. For example, the bottom surface of the first semiconductor substrate 210 may be an active surface.

[0038] The first semiconductor chip 200 may have a first circuit layer 220 disposed on a bottom surface of a first semiconductor substrate 210. The first circuit layer 220 may include a first semiconductor element 222 and a first device wiring portion 224.

[0039] The first semiconductor element 222 may include a transistor TR1 disposed on the bottom surface of the first semiconductor substrate 210. For example, the transistors TR1 may each include a source and a drain formed on the lower portion of the first semiconductor substrate 210, a gate electrode disposed on the bottom surface of the first semiconductor substrate 210, and a gate dielectric layer between the first semiconductor substrate 210 and the gate electrode. The first semiconductor element 222 may include a plurality of transistors TR1. The first semiconductor element 222 may include a memory circuit or a logic circuit. The first semiconductor element 222 may include a device isolation pattern, a logic unit, or a plurality of memory cells disposed on the bottom surface of the first semiconductor substrate 210. Alternatively, the first semiconductor element 222 may include a passive element, such as a capacitor.

[0040] The bottom surface of the first semiconductor substrate 210 may be covered with a first device interlayer dielectric layer 226. The first device interlayer dielectric layer 226 may bury the first semiconductor element 222. For example, the first device interlayer dielectric layer 226 may not expose the first semiconductor element 222. The first device interlayer dielectric layer 226 may include, for example, at least one selected from silicon oxide (SiO), silicon nitride (SiN) and silicon oxynitride (SiON). Alternatively, the first device interlayer dielectric layer 226 may include a low-k dielectric material. The first device interlayer dielectric layer 226 may have a single-layer structure or a multi-layer structure. When the first device interlayer dielectric layer 226 is set to the shape of a multi-layer structure, an etch stop layer may be between the dielectric layers. For example, the etch stop layer may be set on the bottom surface of each dielectric layer. The etch stop layer may include, for example, one of silicon nitride (SiN), silicon oxynitride (SiON) and silicon carbonitride (SiCN).

[0041] The first device interlayer dielectric layer 226 may be provided with a first device wiring portion 224 connected to the transistor TR1 therein. The first device wiring portion 224 may include a wiring pattern buried in the first device interlayer dielectric layer 226. For example, the wiring pattern may include a redistribution pattern for horizontal wiring and a via pattern for vertical connection. The first device wiring portion 224 may vertically penetrate the first device interlayer dielectric layer 226 to be connected to one of the source electrode, the drain electrode, and the gate electrode of the transistor TR1. Alternatively, the first device wiring portion 224 may be connected to each component of the first semiconductor element 222. The first device wiring portion 224 may be located between the top surface and the bottom surface of the first device interlayer dielectric layer 226. The first device wiring portion 224 may include, for example, copper (Cu) or tungsten (W).

[0042] The first device interlayer dielectric layer 226 may be provided with a first pad 228 at a lower portion thereof. The first pad 228 may have its bottom surface exposed on the bottom surface of the first device interlayer dielectric layer 226. The bottom surface of the first pad 228 may be coplanar with the bottom surface of the first device interlayer dielectric layer 226. The first pad 228 may be connected to the first device wiring portion 224. The first pad 228 may include, for example, copper (Cu) or tungsten (W).

[0043] The first via 230 may be provided to vertically penetrate the first semiconductor substrate 210 to connect with the first device wiring portion 224. The first via 230 may be a pattern for vertical wiring. The first via 230 may vertically penetrate the first device interlayer dielectric layer 226 to couple to the top surface of a portion of the first device wiring portion 224. The first via 230 may vertically penetrate the first device interlayer dielectric layer 226 and the first semiconductor substrate 210 to be exposed on the top surface of the first semiconductor substrate 210. The first via 230 may include, for example, tungsten (W).

[0044] The first device interlayer dielectric layer 226 may be provided with a conductive bump 250 thereon. The conductive bump 250 may be provided on the bottom surface of the first pad 228. The conductive bump 250 may be coupled to the bottom surface of the first pad 228 of the first device wiring portion 224. For example, the conductive bump 250 may be a bonding terminal protruding onto the bottom surface of the first pad 228. The conductive bump 250 may include a metal material. For example, the conductive bump 250 may include copper (Cu).

[0045] The front protective layer 252 may be disposed on the first circuit layer 220. On the bottom surface of the first device interlayer dielectric layer 226, the front protective layer 252 may surround the conductive bump 250. The conductive bump 250 may not be covered by the front protective layer 252 and may be exposed on the bottom surface of the front protective layer 252. The front protective layer 252 may include a dielectric material. For example, the front protective layer 252 may include a dielectric polymer material, such as an epoxy molding compound (EMC).

[0046] The redistribution layer 240 may be disposed on a top surface of the first semiconductor substrate 210. The redistribution layer 240 may include a redistribution wiring portion 244 and a redistribution dielectric layer 246.

[0047] The top surface of the first semiconductor substrate 210 may be covered by a redistribution dielectric layer 246. The redistribution dielectric layer 246 may include, for example, at least one selected from silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). Alternatively, the redistribution dielectric layer 246 may include a low-k dielectric material. The redistribution dielectric layer 246 may have a single-layer structure or a multi-layer structure. When the redistribution dielectric layer 246 is provided as a multi-layer structure, an etch stop layer may be interposed between the dielectric layers.

[0048] The redistribution dielectric layer 246 may be provided with a redistribution wiring portion 244 connected to the first via 230 therein. The redistribution wiring portion 244 may include a wiring pattern buried in the redistribution dielectric layer 246. For example, the wiring pattern may include a redistribution pattern for horizontal wiring and a via pattern for vertical connection. The redistribution wiring portion 244 may vertically penetrate the redistribution dielectric layer 246 to connect with the first via 230. The redistribution wiring portion 244 may be located between the top surface and the bottom surface of the redistribution dielectric layer 246. The redistribution wiring portion 244 may include, for example, copper (Cu) or tungsten (W).

[0049] The redistribution dielectric layer 246 may be provided with a second pad 248 at an upper portion thereof. The second pad 248 may have a top surface exposed on a top surface of the redistribution dielectric layer 246. The top surface of the second pad 248 may be coplanar with the top surface of the redistribution dielectric layer 246. The second pad 248 may be connected to the redistribution wiring portion 244. The second pad 248 may include, for example, copper (Cu) or tungsten (W).

[0050] The first semiconductor chip 200 may be mounted on the redistribution substrate 100. For example, the front protective layer 252 of the first semiconductor chip 200 may face the top surface of the redistribution substrate 100. The front protective layer 252 of the first semiconductor chip 200 may contact the top surface of the redistribution substrate 100. At the interface between the first semiconductor chip 200 and the redistribution substrate 100, the conductive bump 250 of the first semiconductor chip 200 may contact the redistribution conductive pattern 120 of the redistribution substrate 100. For example, the redistribution conductive pattern 120 of the uppermost substrate wiring layer of the redistribution substrate 100 may include a portion penetrating the redistribution dielectric layer 110 to be coupled to the conductive bump 250.

[0051] According to one or more embodiments, the first semiconductor chip 200 may not be in contact with the top surface of the redistribution substrate 100. For example, the first semiconductor chip 200 may be vertically spaced apart from the top surface of the redistribution substrate 100. In this case, portions of the redistribution conductive patterns 120 of the redistribution substrate 100 may penetrate the redistribution dielectric layer 110 to extend toward the first semiconductor chip 200, thereby being coupled to the conductive bumps 250.

[0052] The molding layer 400 may be disposed on the redistribution substrate 100. On the redistribution substrate 100, the molding layer 400 may surround the first semiconductor chip 200. The first semiconductor chip 200 may be exposed on the top surface of the molding layer 400. The top surface of the first semiconductor chip 200 may be coplanar with the top surface of the molding layer 400. The molding layer 400 may include a dielectric material. For example, the molding layer 400 may include a dielectric polymer material, such as an epoxy molding compound (EMC).

[0053] The redistribution substrate 100 may be provided with a conductive pillar 450 thereon. The conductive pillar 450 may be a configuration for connecting the second semiconductor chip 300 described later to a vertical connection terminal of the redistribution substrate 100. The conductive pillar 450 may be horizontally spaced apart from the first semiconductor chip 200. The conductive pillar 450 may have a pillar shape. The conductive pillar 450 may vertically penetrate the mold layer 400. For example, the conductive pillar 450 may extend toward the top surface of the mold layer 400 and may be exposed on the top surface of the mold layer 400. The top surface of the conductive pillar 450 may be coplanar with the top surface of the mold layer 400 and the top surface of the first semiconductor chip 200. The conductive pillar 450 may extend toward the bottom surface of the mold layer 400 to couple to the redistribution conductive pattern 120 of the redistribution substrate 100. For example, the redistribution conductive pattern 120 of the uppermost substrate wiring layer of the redistribution substrate 100 may include a portion penetrating the redistribution dielectric layer 110 to couple to the conductive pillar 450. The conductive pillar 450 may include a conductive material. The conductive pillar 450 may include a metal material, such as copper (Cu) or tungsten (W).

[0054] The second semiconductor chip 300 may be disposed on the first semiconductor chip 200 and the mold layer 400. The second semiconductor chip 300 may include an integrated element therein. For example, the second semiconductor chip 300 may be a wafer-level die formed of a semiconductor such as silicon (Si). The second semiconductor chip 300 may have a front surface and a rear surface. The front surface of the second semiconductor chip 300 may face the redistribution substrate 100. For example, the second semiconductor chip 300 may be disposed on the first semiconductor chip 200 and the mold layer 400 in a face-down state. The width of the second semiconductor chip 300 may be greater than the width of the first semiconductor chip 200. The entire first semiconductor chip 200 may vertically overlap with a portion of the second semiconductor chip 300. Another portion of the second semiconductor chip 300 may vertically overlap with the mold layer 400 located on one side of the first semiconductor chip 200. The side surface of the second semiconductor chip 300 may be aligned with the side surface of the mold layer 400.

[0055] The second semiconductor chip 300 may include a second semiconductor substrate 310 and a second circuit layer 320 .

[0056] A second semiconductor substrate 310 may be provided. The second semiconductor substrate 310 may include a semiconductor material. For example, the second semiconductor substrate 310 may be a single crystal silicon substrate. The second semiconductor substrate 310 may have a top surface and a bottom surface opposite to each other. The bottom surface of the second semiconductor substrate 310 may be a front surface of the second semiconductor substrate 310, and the top surface of the second semiconductor substrate 310 may be a rear surface of the second semiconductor substrate 310. As used herein, the front surface of the second semiconductor substrate 310 may be defined as indicating a surface on which a semiconductor element is formed or mounted in the second semiconductor substrate 310, or a surface on which a wiring line and a pad are formed in the second semiconductor substrate 310, and the rear surface of the second semiconductor substrate 310 may be defined as indicating a surface opposite to the front surface. For example, the bottom surface of the second semiconductor substrate 310 may be an active surface.

[0057] Refer to Figure 1 and Figure 2 , the second semiconductor substrate 310 may have a first portion P1 and a second portion P2. The first portion P1 may be a portion adjacent to the front surface of the second semiconductor substrate 310 or the bottom surface of the second semiconductor substrate 310. For example, the first portion P1 of the second semiconductor substrate 310 may be a portion on which a semiconductor element is formed or mounted in the second semiconductor substrate 310, or a portion on which a wiring line and a pad are formed. The second portion P2 may be a portion adjacent to the rear surface of the second semiconductor substrate 310 or the top surface of the second semiconductor substrate 310. The second portion P2 may be exposed on the top surface of the second semiconductor substrate 310. The first portion P1 may separate the second portion P2 from the second circuit layer 320, which will be discussed below. In the present disclosure, for convenience of description, the second semiconductor substrate 310 is divided into the first portion P1 and the second portion P2, but the first portion P1 and the second portion P2 may both be a portion of the second semiconductor substrate 310, and may be a semiconductor layer formed of the same material (e.g., silicon (Si)).

[0058] A value of about 100 nanometers to about 500 nanometers may be given as the thickness T1 of the first portion P1, or the distance from the bottom surface of the second semiconductor substrate 310 to the boundary between the first portion P1 and the second portion P2. However, the distance from the bottom surface of the second semiconductor substrate 310 to the boundary between the first portion P1 and the second portion P2 is only exemplary, and the present disclosure is not limited thereto. The thickness T1 of the first portion P1 may be equal to or greater than about 500 nanometers. For example, the second portion P2 may be disposed about at least 100 nanometers away from the front surface of the second semiconductor substrate 310 on which the second semiconductor element 322 discussed below is formed. The second semiconductor element 322 may include detailed components formed on the lower portion of the second semiconductor substrate 310, such as a device isolation pattern, an n-well layer, a p-well layer, and / or a buried gate electrode. As used herein, the formation depth of the second semiconductor element 322 or the depth of the second semiconductor element 322 may indicate the distance from the front surface of the second semiconductor substrate 310 to the farthest component of the detailed components of the second semiconductor element 322. The thickness T1 of the first portion P1 may be greater than about 20 times the formation depth of the second semiconductor element 322. This will be discussed in further detail below when describing the method for manufacturing a semiconductor package. A value of about 1 nanometer to about 50 nanometers may be given as the thickness T2 of the second portion P2, or the distance from the boundary between the first portion P1 and the second portion P2 to the top surface of the second semiconductor substrate 310.

[0059] The first portion P1 may have more lattice defects than the second portion P2. For example, the dislocation density of the first portion P1 may be less than the dislocation density of the second portion P2. As used herein, the term "dislocation density" may refer to the amount of linear lattice defects per unit area present in a crystal, or the number of dislocation lines per unit volume of dislocations (i.e., cm / cm 3 ). The first portion P1 may have a single crystal structure. The second portion P2 may have a polycrystalline structure. The average grain size of the second portion P2 may decrease as the distance from the first portion P1 increases. As used herein, the average grain area may be obtained by dividing a specific area by the number of grains included in the specific area, and the diameter of a circle having the average grain area may be defined as the average grain size. Alternatively, the average grain size may be determined by diameter measurement, ASTM grain size number, etc. For ease of description, Figure 2 The die shape and die size are exaggerated, and the size ratio between the die and the components of the semiconductor package may be different from the actual ratio.

[0060] exist Figure 1 and Figure 2 , it is described that the first portion P1 and the second portion P2 of the second semiconductor substrate 310 include the same semiconductor material (eg, silicon (Si)), but the present disclosure is not limited thereto.

[0061] Reference Figure 1 and Figure 3 , the second portion P2 may further include an impurity DOP having the same valence electron number as that of the semiconductor material. For example, when the second semiconductor substrate 310 is formed of silicon (Si), the impurity DOP may include germanium (Ge). The second portion P2 may be implanted with the impurity DOP to provide lattice defects to the second portion P2 in the second semiconductor substrate 310 that is configured as a single crystal structure. This will be discussed in further detail below when describing a method for manufacturing a semiconductor package. The concentration of the impurity DOP in the second portion P2 may be greater than the concentration of the impurity DOP in the first portion P1. For example, the first portion P1 may not include the impurity DOP. For convenience of description, Figure 3 The die shape and die size are exaggerated, and the size ratio between the die and the components of the semiconductor package may be different from the actual ratio.

[0062] According to one or more embodiments of the present disclosure, the second portion P2 of the second semiconductor substrate 310 may be provided as a polycrystalline structure adjacent to the rear surface of the second semiconductor chip 300. Therefore, the heat energy required for the bonding process of the first semiconductor chip 200 and the second semiconductor chip 300 may be prevented from being released to the rear surface of the second semiconductor chip 300 through the second semiconductor substrate 310, and the heat energy required for the bonding process may be reduced. This will be discussed in further detail below when describing a method for manufacturing a semiconductor package.

[0063] Still refer to Figure 1 , the second semiconductor chip 300 may have a second circuit layer 320 disposed on a bottom surface of a second semiconductor substrate 310 . The second circuit layer 320 may include a second semiconductor element 322 and a second device wiring portion 324 .

[0064] The second semiconductor element 322 may include a transistor TR2 disposed on the bottom surface of the second semiconductor substrate 310. For example, the transistors TR2 may each include a source and a drain formed on the lower portion of the second semiconductor substrate 310, a gate electrode disposed on the bottom surface of the second semiconductor substrate 310, and a gate dielectric layer between the second semiconductor substrate 310 and the gate electrode. The second semiconductor element 322 may include a plurality of transistors TR2. The second semiconductor element 322 may include a memory circuit or a logic circuit. The second semiconductor element 322 may include a device isolation pattern, a logic unit, and / or a plurality of memory cells disposed on the bottom surface of the second semiconductor substrate 310. Alternatively, the second semiconductor element 322 may include a passive element, such as a capacitor.

[0065] The bottom surface of the second semiconductor substrate 310 may be covered with a second device interlayer dielectric layer 326. The second device interlayer dielectric layer 326 may bury the second semiconductor element 322. For example, the second semiconductor element 322 may not be exposed by the second device interlayer dielectric layer 326. The second device interlayer dielectric layer 326 may include, for example, at least one selected from silicon oxide (SiO), silicon nitride (SiN) and silicon oxynitride (SiON). Alternatively, the second device interlayer dielectric layer 326 may include a low-k dielectric material. The second device interlayer dielectric layer 326 may have a single-layer structure or a multi-layer structure. When the second device interlayer dielectric layer 326 is set to a multi-layer structure, an etch stop layer may be between the dielectric layers.

[0066] The second device interlayer dielectric layer 326 may be provided with a second device wiring portion 324 connected to the transistor TR2. The second device wiring portion 324 may include a wiring pattern buried in the second device interlayer dielectric layer 326. For example, the wiring pattern may include a redistribution pattern for horizontal wiring and a via pattern for vertical connection. The second device wiring portion 324 may vertically penetrate the second device interlayer dielectric layer 326 to be connected to one of the source electrode, the drain electrode, and the gate electrode of the transistor TR2. Alternatively, the second device wiring portion 324 may be connected to each component of the second semiconductor element 322. The second device wiring portion 324 may be located between the top surface and the bottom surface of the second device interlayer dielectric layer 326. The second device wiring portion 324 may include, for example, copper (Cu) or tungsten (W).

[0067] The second device interlayer dielectric layer 326 may be provided with a third pad 328 at a lower portion thereof. The bottom surface of the third pad 328 may be exposed on the bottom surface of the second device interlayer dielectric layer 326. The bottom surface of the third pad 328 may be coplanar with the bottom surface of the second device interlayer dielectric layer 326. The third pad 328 may be connected to the second device wiring portion 324. The third pad 328 may include, for example, copper (Cu) or tungsten (W).

[0068] The second semiconductor chip 300 may be mounted on the first semiconductor chip 200. For example, the second semiconductor chip 300 may be disposed on the mold layer 400 and the first semiconductor chip 200. The second circuit layer 320 of the second semiconductor chip 300 may face the top surface of the first semiconductor chip 200. The third pad 328 of the second semiconductor chip 300 may be vertically aligned with the second pad 248 and the conductive pillar 450 of the first semiconductor chip 200. The second semiconductor chip 300 may contact the first semiconductor chip 200, the mold layer 400, and the conductive pillar 450.

[0069] At the interface between the first semiconductor chip 200 and the second semiconductor chip 300, the redistribution dielectric layer 246 of the first semiconductor chip 200 can be bonded to the second device interlayer dielectric layer 326 of the second semiconductor chip 300. In this case, the redistribution dielectric layer 246 and the second device interlayer dielectric layer 326 can constitute a mixed bond of oxide, nitride or oxynitride. As used herein, the term "mixed bonding" can represent a bonding in which two components of the same type merge at the interface therebetween. For example, a continuous structure can be provided between the redistribution dielectric layer 246 and the second device interlayer dielectric layer 326 bonded to each other, and an invisible interface can exist between the redistribution dielectric layer 246 and the second device interlayer dielectric layer 326. For example, the redistribution dielectric layer 246 and the second device interlayer dielectric layer 326 can be formed of the same material, and there can be no interface between the redistribution dielectric layer 246 and the second device interlayer dielectric layer 326. The redistribution dielectric layer 246 and the second device interlayer dielectric layer 326 can be provided as a single component. For example, the redistribution dielectric layer 246 and the second device interlayer dielectric layer 326 may be joined to form a single integral piece. However, the present disclosure is not limited thereto. The redistribution dielectric layer 246 and the second device interlayer dielectric layer 326 may be formed of materials different from each other. A continuous structure may not be provided between the redistribution dielectric layer 246 and the second device interlayer dielectric layer 326, and a visible interface may exist between the redistribution dielectric layer 246 and the second device interlayer dielectric layer 326.

[0070] The first semiconductor chip 200 may be connected to the second semiconductor chip 300. For example, the first semiconductor chip 200 and the second semiconductor chip 300 may contact each other. On the interface between the first semiconductor chip 200 and the second semiconductor chip 300, the second pad 248 of the first semiconductor chip 200 may be bonded to the third pad 328 of the second semiconductor chip 300. In this case, a hybrid bond may be achieved between the second pad 248 and the third pad 328. For example, a continuous structure may be provided between the second pad 248 and the third pad 328 bonded to each other, and an invisible interface may exist between the second pad 248 and the third pad 328. The second pad 248 and the third pad 328 may be formed of the same material, so there may be no interface between the second pad 248 and the third pad 328. Therefore, the second pad 248 and the third pad 328 may be provided as a single component. For example, the second pad 248 and the third pad 328 may be bonded to form a single integral piece.

[0071] The second semiconductor chip 300 may be connected to the conductive pillars 450. For example, the conductive pillars 450 may vertically penetrate the mold layer 400 to be coupled to bottom surfaces of some of the third pads 328 of the second semiconductor chip 300.

[0072] In the following embodiments, the above reference will be omitted. Figures 1 to 3 The detailed description of the discussed technical features is repeated, and the differences thereof will be discussed in detail. The same reference numerals may be assigned to the same components as those of the semiconductor package discussed above according to one or more embodiments of the present disclosure.

[0073] Figure 4 A cross-sectional view of a semiconductor package according to one or more embodiments of the present disclosure is shown.

[0074] Figure 1 It is shown that the first semiconductor chip 200 and the second semiconductor chip 300 are directly bonded to each other, but the present disclosure is not limited thereto.

[0075] Reference Figure 4 , the connection terminal 420 may be disposed on the top surface of the first semiconductor chip 200. The connection terminal 420 may be disposed on the second pad 248 of the first semiconductor chip 200. The connection terminal 420 may include a solder ball or a solder bump.

[0076] The mold layer 400 may be disposed on the redistribution substrate 100. On the redistribution substrate 100, the mold layer 400 may surround the first semiconductor chip 200. The mold layer 400 may cover the top surface of the first semiconductor chip 200.

[0077] The conductive pillars 450 may be disposed on the redistribution substrate 100. The conductive pillars 450 may vertically penetrate the mold layer 400. For example, the conductive pillars 450 may extend toward the top surface of the mold layer 400 and may be exposed on the top surface of the mold layer 400. The top surface of the conductive pillars 450 may be coplanar with the top surface of the mold layer 400. The top surface of the conductive pillars 450 and the top surface of the mold layer 400 may be located at a higher level than the top surface of the first semiconductor chip 200.

[0078] The second semiconductor chip 300 may be disposed on the mold layer 400. A bottom surface of the second semiconductor chip 300 may be vertically spaced apart from a top surface of the first semiconductor chip 200.

[0079] The second semiconductor chip 300 may be mounted on the first semiconductor chip 200. For example, the connection terminal 420 may connect the third pad 328 of the second semiconductor chip 300 to the second pad 248 of the first semiconductor chip 200. The mold layer 400 may surround the connection terminal 420 while filling the space between the first semiconductor chip 200 and the second semiconductor chip 300.

[0080] Figure 5 A cross-sectional view of a semiconductor package according to one or more embodiments of the present disclosure is shown.

[0081] Reference Figure 5 , the semiconductor package may not include a redistribution substrate (see Figure 1 of 100).

[0082] The conductive pillar 450 may have a bottom surface exposed on the bottom surface of the mold layer 400. The conductive bump 250 may have a bottom surface exposed on the bottom surface of the first semiconductor chip 200.

[0083] The external terminal 130 may be disposed on a bottom surface of the conductive pillar 450 and a bottom surface of the conductive bump 250 .

[0084] Figure 6 A cross-sectional view of a semiconductor package according to one or more embodiments of the present disclosure is shown. Figure 7 and Figure 8 Shown Figure 6 A diagram of the crystal structure of portion B is shown.

[0085] Reference Figure 6 and Figure 7 , the second semiconductor substrate 310 may have a first portion P1, a second portion P2, a third portion P3, and a fourth portion P4. The first portion P1 may be a portion adjacent to the front surface of the second semiconductor substrate 310 or the bottom surface of the second semiconductor substrate 310. For example, the first portion P1 of the second semiconductor substrate 310 may be a portion on which a semiconductor element is formed or mounted in the second semiconductor substrate 310, or a portion on which a wiring line and a pad are formed. The fourth portion P4 may be a portion adjacent to the rear surface of the second semiconductor substrate 310 or the top surface of the second semiconductor substrate 310. The fourth portion P4 may be exposed on the top surface of the second semiconductor substrate 310. The second portion P2 may be between the first portion P1 and the fourth portion P4. The third portion P3 may be between the second portion P2. For example, the second portion P2 may be a portion disposed on the opposite side of the third portion P3. The first portion P1 may separate the second portion P2 and the third portion P3 from the second circuit layer 320, which will be discussed below. In the present disclosure, for the convenience of description, the second semiconductor substrate 310 is divided into a first portion P1, a second portion P2, a third portion P3, and a fourth portion P4, but the first portion P1, the second portion P2, the third portion P3, and the fourth portion P4 may all be a portion of the second semiconductor substrate 310 and may be a semiconductor layer formed of the same material (e.g., silicon (Si)). The third portion P3 may be a heat shielding layer disposed in the second semiconductor substrate 310. For example, the thermal conductivity of the third portion P3 may be less than that of the first portion P1 and the fourth portion P4. The first portion P1 and the fourth portion P4 may be the remaining portion of the second semiconductor substrate 310 on which the third portion P3 is not disposed.

[0086] A value of about 100 nanometers to about 500 nanometers may be given as the thickness of the first portion P1, or the distance from the bottom surface of the second semiconductor substrate 310 to the boundary between the first portion P1 and the second portion P2. However, the distance from the bottom surface of the second semiconductor substrate 310 to the boundary between the first portion P1 and the second portion P2 is only exemplary, and the present disclosure is not limited thereto. The thickness of the first portion P1 may be equal to or greater than about 500 nanometers. For example, the second portion P2 may be disposed about at least 100 nanometers away from the front surface of the second semiconductor substrate 310 on which the second semiconductor element 322 is formed. The second semiconductor element 322 may include detailed components formed on the lower portion of the second semiconductor substrate 310, such as device isolation patterns, n-well layers, p-well layers, and / or buried gate electrodes. As used herein, the formation depth of the second semiconductor element 322 or the depth of the second semiconductor element 322 may indicate the distance from the front surface of the second semiconductor substrate 310 to the farthest component of the detailed components of the second semiconductor element 322. The thickness of the first portion P1 may be greater than about 20 times the formation depth of the second semiconductor element 322 .

[0087] The third portion P3 may have a thickness of about 2 nanometers to about 100 nanometers.

[0088] A value of about 40 nanometers to about 50 nanometers may be given as the thickness of the second portion P2, or the distance from the third portion P3 to the first portion P1 and the distance from the third portion P3 to the fourth portion P4.

[0089] The lattice defects of the first part P1 and the fourth part P4 may be less than the lattice defects of the third part P3. For example, the dislocation density of the first part P1 and the fourth part P4 may be less than the dislocation density of the third part P3. The first part P1 and the fourth part P4 may have their single crystal crystal structure. The third part P3 may have an amorphous structure. The lattice defects of the second part P2 may be more than the lattice defects of the first part P1 and the fourth part P4 and less than the lattice defects of the third part P3. For example, the dislocation density of the second part P2 may be less than the dislocation density of the third part P3 and greater than the dislocation density of the first part P1 and the fourth part P4. The second part P2 may have a polycrystalline structure. The average grain size of the second part P2 may decrease as the distance from the first part P1 and the fourth part P4 increases and as the distance from the third part P3 decreases. For example, the second part P2 may be an interface layer between the first part P1 and the fourth part P4 and the third part P3, or an interface layer between the first part P1 and the fourth part P4 of the single crystal and the amorphous third part P3. For the convenience of description, Figure 7 The die shape and die size are exaggerated, and the size ratio between the die and the components of the semiconductor package may be different from the actual ratio.

[0090] Figure 6 , Figure 7 and Figure 8 It is illustrated that the first portion P1 , the second portion P2 , the third portion P3 , and the fourth portion P4 of the second semiconductor substrate 310 include the same semiconductor material (eg, silicon (Si)), but the present disclosure is not limited thereto.

[0091] Reference Figure 6 and Figure 8 , the second portion P2 and the third portion P3 may further include an impurity DOP having the same valence electron number as that of the semiconductor material. For example, when the second semiconductor substrate 310 is formed of silicon (Si), the impurity DOP may include germanium (Ge). The second portion P2 and the third portion P3 may be implanted with the impurity DOP to provide lattice defects to the second portion P2 and the third portion P3 in the second semiconductor substrate 310 that is configured as a single crystal structure. The concentration of the impurity DOP in the second portion P2 may be greater than the concentration of the impurity DOP in the first portion P1 and the fourth portion P4. For example, the first portion P1 and the fourth portion P4 may not include the impurity DOP. The concentration of the impurity DOP in the second portion P2 may be less than the concentration of the impurity DOP in the third portion P3. For convenience of description, Figure 8 The die shape and die size are exaggerated, and the size ratio between the die and the components of the semiconductor package may be different from the actual ratio.

[0092] According to one or more embodiments, the fourth portion P4 may not be provided. For example, the second semiconductor substrate 310 may have a first portion P1, a second portion P2, and a third portion P3. One of the second portions P2 may be a portion adjacent to the rear surface of the second semiconductor substrate 310 or the top surface of the second semiconductor substrate 310. One of the second portions P2 may be exposed on the top surface of the second semiconductor substrate 310.

[0093] Fig. 9 A cross-sectional view of a semiconductor package according to one or more embodiments of the present disclosure is shown.

[0094] and Figures 6 to 8 In different embodiments, the second semiconductor substrate 310 may have a first portion P1, a second portion P2, and a third portion P3. The third portion P3 may be a portion adjacent to the rear surface of the second semiconductor substrate 310 or the top surface of the second semiconductor substrate 310. The third portion P3 may be exposed on the top surface of the second semiconductor substrate 310. The second portion P2 may be between the first portion P1 and the third portion P3.

[0095] Figures 10 to 20 A cross-sectional view illustrating a method of manufacturing a semiconductor package according to one or more embodiments of the present disclosure is shown.

[0096] Reference Fig.10 , a first semiconductor substrate 210 may be provided. The first semiconductor substrate 210 may include a semiconductor material. For example, the first semiconductor substrate 210 may be a single crystal silicon substrate.

[0097] The first circuit layer 220 and the first via 230 may be formed on the top surface of the first semiconductor substrate 210. For example, a typical process may be performed on the top surface of the first semiconductor substrate 210 to form a first semiconductor element 222 including a plurality of transistors TR1. The first via 230 may be formed in the first semiconductor substrate 210. The first via 230 may have an end exposed on the top surface of the first semiconductor substrate 210 or protruding onto the top surface of the first semiconductor substrate 210. The other end of the first via 230 may be located in the first semiconductor substrate 210. For example, the first via 230 may not be exposed on the bottom surface of the first semiconductor substrate 210. Deposition and patterning of a dielectric layer and deposition and patterning of a conductive layer may be repeatedly performed on the top surface of the first semiconductor substrate 210 to form a first device interlayer dielectric layer 226, a first device wiring portion 224, and a first pad 228. However, in the present disclosure, the formation of the first circuit layer 220 is not limited thereto, and the first circuit layer 220 may be formed using a typical method.

[0098] Reference Fig.11 , a conductive bump 250 and a front protective layer 252 may be formed on the first circuit layer 220. For example, after forming a sacrificial layer on the first circuit layer 220, the sacrificial layer may be patterned to form an opening exposing the first pad 228, and the opening may be filled with a conductive material to form the conductive bump 250. The front protective layer 252 may be formed on the first circuit layer 220 to surround the conductive bump 250. Alternatively, after forming the front protective layer 252 having an opening exposing the first pad 228 on the first circuit layer 220, the opening may be filled with a conductive material to form the conductive bump 250.

[0099] Then, a first thinning process may be performed on the bottom surface of the first semiconductor substrate 210. The first thinning process may polish the bottom surface of the first semiconductor substrate 210. For example, the bottom surface of the first semiconductor substrate 210 may be subjected to a planarization process such as chemical mechanical polishing (CMP). The first thinning process may reduce the thickness of the first semiconductor substrate 210. The first semiconductor substrate 210 may become planarized. The first thinning process may expose the bottom surface of the first via 230.

[0100] Reference Fig.12, a redistribution layer 240 may be formed on the bottom surface of the first semiconductor substrate 210. For example, deposition and patterning of a dielectric layer and deposition and patterning of a conductive layer may be repeatedly performed on the bottom surface of the first semiconductor substrate 210 to form a redistribution wiring portion 244, a redistribution dielectric layer 246, and a second pad 248. However, in the present disclosure, the formation of the redistribution layer 240 is not limited thereto, and a typical method may be used to form the redistribution layer 240. Through the above process, the first semiconductor chip 200 may be manufactured.

[0101] Reference Fig.13 , a second semiconductor substrate 310 may be provided. The second semiconductor substrate 310 may include a semiconductor material. For example, the second semiconductor substrate 310 may be a single crystal silicon substrate.

[0102] The second circuit layer 320 may be formed on the top surface of the second semiconductor substrate 310. For example, a typical process may be performed on the top surface of the second semiconductor substrate 310 to form a second semiconductor element 322 including a plurality of transistors TR2. Deposition and patterning of a dielectric layer and deposition and patterning of a conductive layer may be repeatedly performed on the top surface of the second semiconductor substrate 310 to form a second device interlayer dielectric layer 326, a second device wiring portion 324, and a third pad 328. However, in the present disclosure, the formation of the second circuit layer 320 is not limited thereto, and the second circuit layer 320 may be formed using a typical method.

[0103] Reference Fig.14 , a third portion P3 may be formed in the second semiconductor substrate 310. The third portion P3 may be a heat shielding layer provided in the second semiconductor substrate 310. For example, the crystallinity of the single-crystalline second semiconductor substrate 310 may be partially changed to form the third portion P3. Fig.14 As shown by the arrow in , the bottom surface of the second semiconductor substrate 310 may undergo an implantation process in which impurities are implanted into the third portion P3. The impurities may be the same material as the semiconductor material included in the second semiconductor substrate 310, or a material having the same valence electron number as the semiconductor material. The third portion P3 may have an excessive increase in the number of atoms included in the semiconductor material, or the third portion P3 may be implanted with a material whose atomic size is different from the atomic size included in the semiconductor material. Therefore, the lattice defects of the third portion P3 may increase, and the crystal structure of the third portion P3 may become an amorphous or polycrystalline structure.

[0104] Alternatively, a laser annealing process may be performed on the third portion P3. The laser annealing process may destroy the bonding of atoms of the semiconductor material in the third portion P3. Therefore, the lattice defects of the third portion P3 may increase, and the crystal structure of the third portion P3 may become an amorphous or polycrystalline structure. The thermal conductivity of the third portion P3 having an amorphous or polycrystalline structure may be less than the thermal conductivity of the first portion P1 having a single crystal structure.

[0105] The present disclosure is not limited thereto, and the third portion P3 may be formed using various methods for forming an amorphous layer in the second semiconductor substrate 310 .

[0106] The third portion P3 may be formed to be vertically spaced apart from each other. In the third portion P3, a specific third portion P3 adjacent to the top surface of the second semiconductor substrate 310 may be spaced apart from the top surface of the second semiconductor substrate 310 by about 100 nanometers to about 500 nanometers. However, the distance between the specific third portion P3 and the top surface of the second semiconductor substrate 310 is only exemplary, the present disclosure is not limited thereto, and the third portion P3 may be spaced apart from the top surface of the second semiconductor substrate 310 by at least about 500 nanometers. For example, the second semiconductor element 322 may include detailed components formed on the upper portion of the second semiconductor substrate 310, such as device isolation patterns, n-well layers, p-well layers, and / or buried gate electrodes. As used herein, the formation depth of the second semiconductor element 322 or the depth of the second semiconductor element 322 may indicate the distance from the top surface of the second semiconductor substrate 310 to the farthest component in the detailed components of the second semiconductor element 322. The distance between the top surface of the second semiconductor substrate 310 and the third portion P3 most adjacent to the top surface of the second semiconductor substrate 310 may be greater than about 20 times the formation depth of the second semiconductor element 322. When the third portion P3 is formed at a position less than about 20 times the formation depth of the second semiconductor element 322, the second semiconductor element 322 formed on the top surface of the second semiconductor substrate 310 may be damaged in a process of forming the third portion P3. Fig.14 A third portion P3 of three layers is shown formed in the second semiconductor substrate 310, but the present disclosure is not limited thereto. In one embodiment, only one or two third portions P3 may be provided; alternatively, four or more third portions P3 may be provided.

[0107] In the process of forming the third portion P3, the second portion P2 may be formed between the third portion P3 and the first portion P1 as the remaining portion of the second semiconductor substrate 310. The second portion P2 may have more lattice defects than the first portion P1 and less lattice defects than the third portion P3. For example, the second portion P2 may be an interface layer between the first portion P1 and the third portion P3, or an interface layer between the single crystal first portion P1 and the amorphous third portion P3. Through the above process, the second semiconductor chip 300 may be manufactured.

[0108] Reference Fig.15 , a conductive pillar 450 may be formed on the second semiconductor chip 300. For example, a sacrificial layer may be formed on the second circuit layer 320 of the second semiconductor chip 300, the sacrificial layer may be patterned to form an opening exposing the third pad 328, the opening may be filled with a conductive material to form the conductive pillar 450, and then the sacrificial layer may be removed.

[0109] exist Fig.14 and Fig.15 In the embodiment of FIG. 5 , it is shown that the conductive pillar 450 is formed after the second portion P2 and the third portion P3 are formed in the second semiconductor substrate 310 , but the present disclosure is not limited thereto. Fig.16 As shown, a conductive pillar 450 may be formed on the second semiconductor chip 300 , and then a second portion P2 and a third portion P3 may be formed in the second semiconductor substrate 310 .

[0110] Reference Fig.17 , the first semiconductor chip 200 may be mounted on the second semiconductor chip 300 .

[0111] The first semiconductor chip 200 may be aligned on the second semiconductor chip 300 to allow the second pad 248 of the first semiconductor chip 200 to be located on the third pad 328 of the second semiconductor chip 300. The first semiconductor chip 200 may be disposed on the second semiconductor chip 300 to allow the second pad 248 to contact the third pad 328. An annealing process may be performed on the first semiconductor chip 200. The annealing process may bond the second pad 248 to the third pad 328. For example, the second pad 248 and the third pad 328 may be bonded to form a single integral piece. The bonding between the second pad 248 and the third pad 328 may be performed automatically. For example, the second pad 248 and the third pad 328 may be formed of the same material (e.g., copper (Cu)), and may be bonded to each other by a metal-to-metal hybrid bonding process generated by surface activation at the interface between the second pad 248 and the third pad 328 in contact with each other.

[0112] According to one or more embodiments of the present disclosure, a third portion P3 (heat shielding layer) may be provided in the second semiconductor substrate 310 of the second semiconductor chip 300. The heat HEA provided when the annealing process is performed on the first semiconductor chip 200 may pass through the first semiconductor chip 200 to facilitate the bonding between the second pad 248 and the third pad 328. The third portion P3 may shield the heat HEA in the second semiconductor substrate 310. For example, the heat HEA may be prevented from being released downward through the second semiconductor chip 300, and most of the heat HEA may be used to bond the second pad 248 to the third pad 328 without loss. Therefore, a semiconductor package manufacturing method that improves energy efficiency and reduces process temperature may be provided. In addition, in view of heat loss, it may not be necessary to increase the process temperature, and the occurrence of failures caused by high temperature of the semiconductor package may be reduced.

[0113] exist Fig.17 In the embodiment, an example in which the first semiconductor chip 200 and the second semiconductor chip 300 are directly bonded to each other is provided, but the present disclosure is not limited thereto. According to one or more embodiments, the first semiconductor chip 200 may be mounted on the second semiconductor chip 300 via a connection terminal such as a solder ball. For example, a solder ball may be attached to a third pad 328 of the second semiconductor chip 300, the first semiconductor chip 200 may be moved onto the second semiconductor chip 300 to allow the solder ball to contact the second pad 248 of the first semiconductor chip 200, and a reflow process may be performed to bond the solder ball to the second pad 248 and the third pad 328. An annealing process may be performed in the reflow process, and the third portion P3 may allow the heat of the annealing process to be used for the reflow process of the solder ball without loss. In this case, a reference may be manufactured. Figure 4 The following description will focus on the semiconductor package Fig.17 Embodiment of the invention.

[0114] Reference Fig.18 , a molding layer 400 may be formed on the second semiconductor chip 300. For example, a molding material may be coated or deposited on the second circuit layer 320 of the second semiconductor chip 300, and then the molding material may be cured to form the molding layer 400. On the second semiconductor chip 300, the molding layer 400 may surround the first semiconductor chip 200 and the conductive pillars 450. The top surface of the first semiconductor chip 200 and the top surface of the conductive pillars 450 may be exposed on the top surface of the molding layer 400.

[0115] Reference Fig.19, a second thinning process may be performed on the bottom surface of the second semiconductor substrate 310. The second thinning process may polish the bottom surface of the second semiconductor substrate 310. For example, the bottom surface of the second semiconductor substrate 310 may be subjected to a planarization process such as chemical mechanical polishing (CMP). The second thinning process may reduce the thickness of the second semiconductor substrate 310. The second semiconductor substrate 310 may become planarized. The second thinning process may completely remove the third portion P3 and the second portion P2 of the second semiconductor substrate 310.

[0116] According to one or more embodiments of the present disclosure, the third portion P3 and the second portion P2 of the manufacturing process for the semiconductor package can be completely removed in the back-end-of-line process. Therefore, the heat generated when operating the semiconductor package can be easily released through the second semiconductor substrate 310 of the second semiconductor chip 300. In short, the semiconductor package can be manufactured to have improved heat radiation characteristics.

[0117] According to one or more embodiments, Fig. 20 As shown, the second thinning process may remove the third portion P3 and the second portion P2 of the second semiconductor substrate 310. In this operation, one of the third portions P3 may not be removed. For example, after the second thinning process, one third portion P3 may remain in the second semiconductor substrate 310. After the second thinning process, depending on the position of the bottom surface of the second semiconductor substrate 310, one of the second portions P2 may be exposed on the bottom surface of the second semiconductor substrate 310, or the third portion P3 may be exposed on the bottom surface of the second semiconductor substrate 310. Alternatively, both the third portion P3 and the second portion P2 may not be exposed on the bottom surface of the second semiconductor substrate 310.

[0118] According to one or more embodiments of the present disclosure, a portion of the third portion P3 may be retained without being removed, which is used in the manufacturing process of the semiconductor package. Therefore, depending on the thickness of the third portion P3, one or two layers of the third portion P3 will not excessively inhibit the transfer of heat generated when operating the semiconductor package.

[0119] According to one or more embodiments, the second thinning process may remove the third portion P3 and the second portion P2 of the second semiconductor substrate 310. In this operation, all of the third portions P3 may be removed, but one of the second portions P2 may not be removed. In this case, reference Figure 1 Semiconductor packaging discussed.

[0120] Return to reference Figure 6, a redistribution substrate 100 may be formed on the mold layer 400 and the first semiconductor chip 200. For example, deposition and patterning of a dielectric layer and deposition and patterning of a conductive layer may be repeatedly performed on the bottom surface of the mold layer 400 and the bottom surface of the first semiconductor chip 200 to form a redistribution dielectric layer 110 and a redistribution conductive pattern 120. However, in the present disclosure, the formation of the redistribution substrate 100 is not limited thereto, and a typical method may be employed to form the redistribution substrate 100. Thereafter, an external terminal 130 may be provided on a pad portion of the redistribution substrate 100.

[0121] In a semiconductor package according to one or more embodiments of the present disclosure and a method for manufacturing the semiconductor package, a heat shielding layer may be provided in a second semiconductor substrate having a second semiconductor chip with a large width. When an annealing process is performed on the first semiconductor chip, heat energy may pass through the first semiconductor chip to facilitate bonding between bumps or pads. The heat shielding layer may shield heat energy in the second semiconductor substrate. For example, heat energy may be prevented from being released downward through the second semiconductor chip, and most of the heat energy may be used to bond bumps or pads without loss. Therefore, a semiconductor package manufacturing method that improves energy efficiency and reduces process temperature may be provided. In addition, in view of heat loss, it may not be necessary to increase the process temperature, and the occurrence of failures caused by high temperature of the semiconductor package may be reduced.

[0122] In addition, the heat shielding layer used in the manufacturing process of the semiconductor package can be completely or mostly removed in the back-end process. Therefore, the heat generated when operating the semiconductor package can be easily released through the second semiconductor substrate. In short, the semiconductor package can be manufactured to have improved heat radiation characteristics.

[0123] Although the present disclosure has been described in conjunction with one or more embodiments of the present disclosure shown in the accompanying drawings, it should be understood by those skilled in the art that changes can be made in form and detail without departing from the spirit and essential features of the present disclosure. Therefore, the embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A semiconductor package, comprising: a first semiconductor chip; a second semiconductor chip, on a top surface of the first semiconductor chip, wherein a width of the second semiconductor chip is smaller than a width of the first semiconductor chip; as well as a molding layer on the first semiconductor chip and surrounding the second semiconductor chip, Wherein, the first semiconductor chip comprises: a first semiconductor substrate; and a first circuit layer, on a top surface of the first semiconductor substrate, Wherein, the first semiconductor substrate comprises: a first portion adjacent to the top surface of the first semiconductor substrate; and a second portion, adjacent to a bottom surface of the first semiconductor substrate, wherein the first portion and the second portion include semiconductor material, wherein the first portion comprises a single crystal structure, and Wherein, the second portion comprises a polycrystalline structure.

2. The semiconductor package according to claim 1, wherein The first portion separates the second portion from the first circuit layer.

3. The semiconductor package according to claim 1, in, The thickness of the first portion is in the range of 100 nanometers to 500 nanometers, and Wherein, the thickness of the second portion is in the range of 1 nanometer to 50 nanometers.

4. The semiconductor package according to claim 1, wherein: An average grain size of the second portion decreases as the distance from the first portion increases.

5. The semiconductor package according to claim 1, in, The second portion also includes impurities, and Wherein, the impurity includes the same number of valence electrons as the valence electrons of the semiconductor material.

6. The semiconductor package according to claim 1, wherein The semiconductor material includes silicon Si.

7. The semiconductor package according to claim 1, wherein: The second portion is exposed on the bottom surface of the first semiconductor substrate.

8. The semiconductor package according to claim 1, wherein The second semiconductor chip comprises: a second semiconductor substrate; a second circuit layer on a top surface of the second semiconductor substrate; a first pad on a bottom surface of the second semiconductor substrate; and A via hole vertically penetrates the second semiconductor substrate and connects the second circuit layer to the first pad.

9. The semiconductor package according to claim 8, in, The first semiconductor chip further includes a second pad on a top surface of the first circuit layer, wherein the first semiconductor chip and the second semiconductor chip are in direct contact with each other, and Wherein, the first pad and the second pad constitute a single integral piece formed of material.

10. The semiconductor package according to claim 8, in, The first semiconductor chip further includes a second pad on a top surface of the first circuit layer, and The second semiconductor chip is mounted on the first semiconductor chip via a connection terminal between the first pad and the second pad.

11. The semiconductor package according to claim 1, further comprising: a redistribution substrate on the molding layer and the second semiconductor chip; a conductive pillar vertically penetrating the molding layer and connecting the redistribution substrate to the first semiconductor chip; as well as An external terminal is coupled to the redistribution substrate.

12. A semiconductor package, comprising: a first semiconductor chip; a second semiconductor chip on a top surface of the first semiconductor chip; a molding layer on the first semiconductor chip and surrounding the second semiconductor chip; a redistribution substrate on the molding layer and the second semiconductor chip; a conductive pillar vertically penetrating the molding layer and connecting the redistribution substrate to the first semiconductor chip; as well as an external terminal coupled to the redistribution substrate, Wherein, the first semiconductor chip comprises: a first semiconductor substrate; a first circuit layer on a top surface of the first semiconductor substrate; and a first pad, on a top surface of the first circuit layer, wherein the first semiconductor substrate comprises a heat shielding layer in the first semiconductor substrate, and The heat shielding layer is spaced apart from the top surface of the first semiconductor substrate by a distance of 100 nanometers to 500 nanometers.

13. The semiconductor package according to claim 12, in, The heat shield layer and the first semiconductor substrate include semiconductor materials, Wherein, the first semiconductor substrate comprises a single crystal structure, and Wherein, the heat shielding layer includes an amorphous structure or a polycrystalline structure.

14. The semiconductor package according to claim 13, wherein: The semiconductor material includes silicon Si.

15. The semiconductor package according to claim 13, in, The heat shielding layer also includes impurities, and Wherein, the impurity includes the same number of valence electrons as the valence electrons of the semiconductor material.

16. The semiconductor package according to claim 12, wherein: The thickness of the heat shielding layer is in the range of 2 nanometers to 100 nanometers.

17. The semiconductor package according to claim 12, in, The first semiconductor substrate further includes an interface layer between a top surface of the heat shielding layer and a bottom surface of the heat shielding layer, Wherein, the interface layer and the first semiconductor substrate comprise semiconductor materials, Wherein, the heat shielding layer comprises an amorphous structure, and Wherein, the interface layer includes a polycrystalline structure.

18. The semiconductor package according to claim 17, wherein: The average grain size of the interface layer decreases as the distance from the heat shielding layer decreases.

19. The semiconductor package according to claim 17, wherein: The thickness of the heat shielding layer is in the range of 40 nanometers to 50 nanometers.

20. The semiconductor package according to claim 12, wherein The second semiconductor chip comprises: a second semiconductor substrate; a second circuit layer on a top surface of the second semiconductor substrate; a second pad on a bottom surface of the second semiconductor substrate; and A chip via vertically penetrates the second semiconductor substrate and connects the second circuit layer to the second pad.

Images