Semiconductor device and forming method thereof

Abstract

In an embodiment, a device includes: an interposer including: a front side redistribution structure; a backside redistribution structure; an encapsulant between the front side redistribution structure and the back side redistribution structure; an interconnect die in the encapsulant; and a thermal storage die in the encapsulant, the thermal storage die being adjacent to the interconnect die; a memory device attached to the front side redistribution structure, the memory device overlapping the thermal storage die in a plan view; and a logic device attached to the front side redistribution structure, the logic device and the memory device each overlapping the interconnect die in a plan view. The embodiment of the invention relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the demand for smaller and more creative packaging technologies for semiconductor dies has emerged. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, comprising: an interposer, comprising: a front-side redistribution structure; a back-side redistribution structure; an encapsulant located between the front-side redistribution structure and the back-side redistribution structure; an interconnect die located in the encapsulant; and a thermal storage die located in the encapsulant, the thermal storage die being adjacent to the interconnect die; a memory device attached to the front-side redistribution structure, the memory device overlapping with the thermal storage die in a plan view; and a logic device attached to the front-side redistribution structure, the logic device and the memory device each overlapping with the interconnect die in a plan view.

[0004] Some other embodiments of the present application provide a semiconductor device, including: a packaging substrate; an interposer, including: a back-side redistribution structure attached to the packaging substrate, the back-side redistribution structure including a first dummy metal sheet having a first opening; an interconnect die located above the back-side redistribution structure; a thermal storage die located above the back-side redistribution structure, the first dummy metal sheet extending from under the interconnect die to under the thermal storage die; an encapsulant located around the interconnect die and the thermal storage die; and a front-side redistribution structure located above the encapsulant; and an integrated circuit device attached to the front-side redistribution structure.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: sealing an interconnect die and a thermal storage die with a sealant, wherein a front side surface of the sealant is substantially coplanar with a front side surface of the thermal storage die; forming a front side redistribution structure on the front side surface of the sealant and the front side surface of the thermal storage die, wherein the front side redistribution structure comprises a first redistribution line connected to the interconnect die; and attaching a logic device and a memory device to the front side redistribution structure, wherein the memory device overlaps with the thermal storage die in a plan view. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 It is a cross-sectional view of an integrated circuit die.

[0008] FIG. 2A to FIG. 2B is a cross-sectional view of a die stack.

[0009] Figures 3 to 12 is a diagram of an intermediate stage in the fabrication of an integrated circuit package in accordance with some embodiments.

[0010] Figures 13 to 14B is a diagram of an integrated circuit package according to some other embodiments.

[0011] Fig.15 is a cross-sectional view of an integrated circuit package according to some other embodiments.

[0012] Fig.16 is a cross-sectional view of an integrated circuit package according to some other embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] According to various embodiments, an interposer of an integrated circuit package includes a molding compound between two redistribution structures. An interconnect die and a heat storage die are disposed in the molding compound and are thus embedded in the interposer. The interconnect die may include active devices, which may cause the interconnect die to consume a high amount of power and generate a large amount of heat during operation. The heat storage die is electrically non-functional and serves as a heat sink for the interconnect die and the active devices. During operation, heat may be dissipated from the interconnect die to the heat storage die. Therefore, the operating temperature of the interconnect die may be reduced, which may improve the performance of the integrated circuit package.

[0016] Figure 1 is a cross-sectional view of an integrated circuit die 50. Multiple integrated circuit dies 50 will be packaged in subsequent processing to form an integrated circuit package. Each integrated circuit die 50 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC) die, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof. The integrated circuit die 50 can be formed in a wafer, and the wafer may include different die regions that are segmented in subsequent steps to form multiple integrated circuit dies 50. The integrated circuit die 50 includes a semiconductor substrate 52, an interconnect structure 54, a die connector 56, and a dielectric layer 58.

[0017] Semiconductor substrate 52 may be a doped or undoped silicon substrate, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may also be used, such as multilayer or gradient substrates. Semiconductor substrate 52 has an active surface (e.g., Figure 1 upward-facing surface) and non-active surfaces (e.g. Figure 1 ). Devices (not shown separately) are located at the active surface of the semiconductor substrate 52. The devices may be active devices (eg, transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface may be free of devices.

[0018] The interconnect structure 54 is located above the active surface of the semiconductor substrate 52 and is used to electrically connect the devices of the semiconductor substrate 52 together to form an integrated circuit. The interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers in the dielectric layers. Acceptable dielectric materials for the dielectric layers include oxides such as silicon oxide or aluminum oxide, nitrides such as silicon nitride, combinations thereof such as silicon oxynitride, and the like. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, and the like. The metallization layer may include conductive vias and / or wires to interconnect the devices of the semiconductor substrate 52. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, and the like. The metallization layer of the interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

[0019] Die connector 56 is located at front side 50F of integrated circuit die 50. Die connector 56 may be a conductive post, pad, etc. that makes an external connection. Die connector 56 is located in and / or on interconnect structure 54. For example, die connector 56 may be part of an upper metallization layer of interconnect structure 54. Die connector 56 may be formed of a metal such as copper, aluminum, etc., and may be formed by, for example, plating, etc.

[0020] Optionally, during the formation of the integrated circuit die 50, a solder area (not shown separately) can be provided on the die connector 56. The solder area can be used to implement a chip probe (CP) test on the integrated circuit die 50. For example, the solder area can be a solder ball, a solder bump, etc., which is used to attach a chip probe to the die connector 56. The chip probe test can be implemented on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only the integrated circuit die 50 (which is a KGD) that has been subsequently processed is packaged, and the die that has not passed the chip probe test is not packaged. After the test, the solder area can be removed.

[0021] The dielectric layer 58 is located at the front side 50F of the integrated circuit die 50. The dielectric layer 58 is located in and / or on the interconnect structure 54. For example, the dielectric layer 58 can be an upper dielectric layer of the interconnect structure 54. The dielectric layer 58 laterally seals the die connector 56. The dielectric layer 58 can be an oxide, a nitride, a polymer, etc. or a combination thereof, which can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The front side surfaces of the die connector 56 and the dielectric layer 58 can be substantially coplanar at the front side 50F of the integrated circuit die 50 (within process variations).

[0022] FIG. 2A to FIG. 2B60A, 60B, respectively. The die stacks 60A, 60B may each have a single function (e.g., a logic device, a memory die, etc.), or may have multiple functions. In some embodiments, the die stack 60A is a logic device such as a system on an integrated chip (SoIC) device, and the die stack 60B is a memory device such as a high bandwidth memory (HBM) device.

[0023] like Figure 2A As shown in , the die stack 60A includes two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, the first integrated circuit die 50A is a logic die, and the second integrated circuit die 50B is an interface die. The interface die bridges the logic die to the memory die and translates commands between the logic die and the memory die. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B are bonded so that the active surfaces face each other (e.g., are "face-to-face" bonded). A conductive via 62 can be formed through one of the integrated circuit dies 50 so that an external connection to the die stack 60A can be made. The conductive via 62 can be a through-substrate via (TSV), such as a through-silicon via, etc. In the illustrated embodiment, the conductive via 62 is formed in the second integrated circuit die 50B (e.g., the interface die). The conductive via 62 extends through the semiconductor substrate 52 of the corresponding integrated circuit die 50 to be physically and electrically connected to the metallization layer of the interconnect structure 54.

[0024] like Figure 2B As shown in , the die stack 60B is a stacked device including a plurality of semiconductor substrates 52. For example, the die stack 60B may be a memory device including a plurality of memory dies, such as a hybrid memory multidimensional cube (HMC) device, a high bandwidth memory (HBM) device, etc. Each semiconductor substrate 52 may (or may not) have a separate interconnect structure 54. The semiconductor substrates 52 are connected by conductive vias 62 such as TSVs.

[0025] Figures 3 to 12 is an integrated circuit package 200 according to some embodiments (see Figures 10 to 12 ) is a view of an intermediate stage in the manufacture of. Figures 3 to 10 is a cross-sectional view, and Figure 11 to Figure 12is a plan view (or top view). A packaging region 100P is shown, and an integrated circuit package 200 is formed in the packaging region 100P. Although a single packaging region 100P is shown, it should be understood that multiple packaging regions 100P may be formed. An interposer wafer 100 is formed. The interposer wafer 100 includes an interposer 240 in the packaging region 100P. An integrated circuit device 202 is attached to the interposer 240. The interposer 240 may include an interconnect die 110 for interconnecting the integrated circuit devices 202 in the packaging region 100P. A packaging substrate 220 is attached to the interposer 240. The packaging region 100P is segmented to form an integrated circuit package 200, which includes a segmented portion of the packaging substrate 220 and the interposer wafer 100 (e.g., the interposer 240). In an embodiment, the integrated circuit package 200 is a chip on wafer on a substrate. Packages such as CoWoS-L packages are described herein, but it should be understood that embodiments may be applicable to other three-dimensional integrated circuit (3DIC) packages.

[0026] exist Figure 3 In the embodiment, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, so that a plurality of packages may be formed on the carrier substrate 102 at the same time.

[0027] The release layer 104 can be formed of a polymer-based material that can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 102. In some embodiments, the release layer 104 is a thermal release material based on epoxy resin that loses its viscosity when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 can be an ultraviolet (UV) glue that loses its viscosity when exposed to UV light. The release layer 104 can be dispensed as a liquid and cured, can be a laminated film laminated to the carrier substrate 102, or can be similar. The top surface of the release layer 104 can be flush and can have a high degree of planarity.

[0028] A through hole 106 is formed above the release layer 104. Although the cross section shown shows a single through hole 106, it should be understood that a plurality of through holes 106 can be formed. As an example of forming a through hole 106, a seed layer (not shown separately) is formed above the release layer 104. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including a plurality of sublayers formed by different materials. In some embodiments, the seed layer includes a copper layer above a titanium layer and a titanium layer. The seed layer can be formed using a deposition process, such as physical vapor deposition (PVD), etc. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the through hole 106. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as chemical plating or electroplating from the seed layer. The conductive material may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms a through hole 106.

[0029] The interconnect die 110 is placed on the release layer 104. The interconnect die 110 may be placed on the release layer 104 using, for example, a pick and place tool. The interconnect die 110 will be used for direct communication between integrated circuit devices (described later) of the integrated circuit package 200.

[0030] Each interconnection die 110 may be a local silicon interconnect (LSI), a large-scale integrated package, an interposer die, etc. The interconnection die 110 may be a bridge die. In the cross section shown, two interconnection dies 110 are attached in the package region 100P. It should be understood that any desired number of interconnection dies 110 may be attached in each package region 100P.

[0031] Each interconnect die 110 includes a substrate 112 having conductive features formed in and / or on the substrate 112. The substrate 112 may include a semiconductor substrate, one or more dielectric layers, etc. In addition, each interconnect die 110 may include a through substrate via (TSV) 114 extending into or through the substrate 112 and may be coupled to the conductive features of the interconnect die 110. In the illustrated embodiment, the substrate 112 initially covers the TSV 114 at the back side of the interconnect die 110. In another embodiment, the TSV 114 is exposed at the back side of the interconnect die 110. The interconnect die 110 also includes a die connector 116 disposed at the front side of the interconnect die 110. Some of the die connectors 116 may be electrically coupled to the back side of the interconnect die 110 through the TSV 114. The TSV 114 may be very small, such as smaller than the through hole 106.

[0032] In some embodiments, the interconnection die 110 may include a die bridge 118. The die bridge 118 may be a metallization layer formed in and / or on, for example, the substrate 112, and is used to interconnect integrated circuit devices (described later) to each other. The die bridge 118 may include interconnects, redistribution lines, etc. The die bridge 118 is located at the front side of the interconnection die 110. Therefore, the interconnection die 110 can be used for direct connection and allow communication between integrated circuit devices. In such an embodiment, the interconnection die 110 can be placed in a corresponding area between the integrated circuit devices attached later, so that each interconnection die 110 overlaps with a plurality of the above integrated circuit devices. In some embodiments, the interconnection die 110 may also include passive devices and / or active devices. In some embodiments, the interconnection die 110 is substantially free of active devices and passive devices. The interconnection die 110 may be placed above the carrier substrate 102 so that the die bridge 118 is away from the carrier substrate 102 (e.g., toward the integrated circuit device attached later).

[0033] The thermal storage wick 120 is placed on the release layer 104. The thermal storage wick 120 can be placed on the release layer 104 using, for example, a pick and place tool. The thermal storage wick 120 is placed adjacent to the corresponding interconnect wick 110. Some types of interconnect wicks 110, such as those with active devices, may consume high amounts of power and generate large amounts of heat during operation. The thermal storage wick 120 will act as a heat sink to draw heat away from the interconnect wick 110 during operation.

[0034] Each heat storage core 120 includes a substrate, which may include a single, continuous layer of material. In some embodiments, the heat storage core 120 includes a semiconductor substrate. The semiconductor substrate may be formed of a semiconductor material such as silicon. The semiconductor substrate may be formed by a suitable growth process. In some embodiments, the heat storage core 120 includes a metal substrate. The metal substrate may be formed of a metal such as copper. The metal substrate may be formed by a suitable machining process. In some embodiments (subsequently for Figures 13 to 14B Description), the thermal storage core 120 includes metal components in the substrate.

[0035] exist Figure 4 In the embodiment of the present invention, a sealant 128 is formed around each component. After being formed, the sealant 128 laterally seals the thermal storage core 120, the interconnection core 110, and the through-hole 106. The sealant 128 may be a molding compound, an epoxy resin, or the like. The sealant 128 may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate 102 so as to bury or cover the thermal storage core 120, the interconnection core 110, and / or the through-hole 106. The sealant 128 may be formed in the gap area between the various components. The sealant 128 may be applied in a liquid or semi-liquid form, and then subsequently cured.

[0036] A removal process may optionally be performed on the encapsulant 128 to expose the thermal storage die 120, the interconnect die 110, and the through-via 106. The removal process may remove material of the encapsulant 128, the thermal storage die 120, the interconnect die 110, and / or the through-via 106 until the die connector 116 and the through-via 106 are exposed. The removal process may include, for example, a planarization process, such as chemical mechanical polishing (CMP), a grinding process, etc. The front side surfaces of the encapsulant 128, the thermal storage die 120, the interconnect die 110 (e.g., the die connector 116), and the through-via 106 may be substantially coplanar (within process variation) after the planarization process. Planarization may be omitted, for example, if the through-via 106 and the die connector 116 are already exposed. After the removal process, the through-via 106 extends through the encapsulant 128. Therefore, the through-via 106 may be referred to as a through-molded via (TMV).

[0037] In some embodiments, the encapsulant 128 is formed of a molding material having a high thermal conductivity. Thus, the encapsulant 128 can help dissipate heat from the interconnect die 110 to the thermal storage die 120 during operation. Fig.15 Description), a separate thermal interface material with high thermal conductivity can be formed between the adjacent thermal storage dies 120 and the interconnection dies 110. When the molding material of the sealant 128 has high thermal conductivity, the separate thermal interface material between the adjacent thermal storage dies 120 and the interconnection dies 110 can be omitted.

[0038] exist Figure 5 In the embodiment of the present invention, a front side redistribution structure 130 is formed on the front side surface of the encapsulant 128, the thermal storage die 120, the interconnect die 110 (e.g., the die connector 116), and the through-hole 106. The front side redistribution structure 130 includes a dielectric layer 132 and a metallization layer 134 (sometimes referred to as a redistribution layer or a redistribution line) in the dielectric layer 132. Therefore, the front side redistribution structure 130 includes metallization layers 134 separated from each other by respective dielectric layers 132. The metallization layers 134 of the front side redistribution structure 130 are connected to the through-hole 106 and to the interconnect die 110 (e.g., the die connector 116).

[0039] In some embodiments, dielectric layer 132 is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithographic mask, such as PBO, polyimide, BCB-based polymers, etc. In other embodiments, dielectric layer 132 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, etc. Dielectric layer 132 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. After dielectric layer 132 is formed, it may be patterned to expose underlying conductive features, such as vias 106, die connectors 116, and / or portions of metallization layer 134. Patterning may be performed by any acceptable process, such as by exposing dielectric layer 132 to light when dielectric layer 132 is formed of a photosensitive material, or by etching using, for example, anisotropic etching. If dielectric layer 132 is formed of a photosensitive material, dielectric layer 132 may be developed after exposure.

[0040] Each of the metallization layers 134 includes a conductive via and / or a conductor. The conductive via extends through the corresponding dielectric layer 132, and the conductor extends along the corresponding dielectric layer 132. As an example of forming the metallization layer 134, a seed layer (not shown separately) is formed above the corresponding lower component. For example, the seed layer can be formed on the corresponding dielectric layer 132 and in any opening through the corresponding dielectric layer 132. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a copper layer above the titanium layer and the titanium layer. The seed layer can be formed using a deposition process, such as PVD, etc. Then a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 134. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as chemical plating or electroplating from a seed layer. The conductive material may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, or a combination thereof. The photoresist and the portion of the seed layer on which the conductive material is not formed are then removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms the metallization layer 134 of the front side redistribution structure 130.

[0041] The front side redistribution structure 130 is shown as an example. More or fewer dielectric layers 132 and metallization layers 134 than shown may be formed by performing the previously described steps any desired number of times.

[0042] Other variations of the front-side redistribution structure 130 are contemplated. For example, some of the dielectric layer 132 may be formed of an encapsulant, such as a molding compound, epoxy, etc. The metallization layer 134 may be formed by plating conductive vias from wires. The dielectric layer 132 may be formed by encapsulating the metallization layer 134. Any desired material stack may be used for the dielectric layer 132.

[0043] Under-bump metallization (UBM) 136 may be formed through the upper dielectric layer 132 of the front-side redistribution structure 130. The UBM 136 is physically and electrically coupled to the upper metallization layer 134 of the front-side redistribution structure 130. Each of the UBMs 136 includes a conductive via and a conductive bump. The conductive via extends through the upper dielectric layer 132, and the conductive bump extends along the upper dielectric layer 132. The UBM 136 may be formed of the same material as the metallization layer 134. In some embodiments, the UBM 136 has a different size than the metallization layer 134.

[0044] exist Figure 6 , an integrated circuit device 202 is attached to the front side redistribution structure 130. A plurality of integrated circuit devices 202 are placed adjacent to each other in the package region 100P. The integrated circuit devices 202 in each package region 100P may include a logic device 202A and a memory device 202B. Although the cross section shown shows a single logic device 202A, it should be understood that a plurality of logic devices 202A may be attached. The logic device 202A and the memory device 202B may be formed in a process of the same technology node, or may be formed in processes of different technology nodes. For example, the logic device 202A may be formed of a more advanced process node than the memory device 202B.

[0045] Each logic device 202A may be a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), a microcontroller, etc. The logic device 202A may be an integrated circuit die (similar to the Figure 1 The integrated circuit die 50 described above may be a die stack (similar to the integrated circuit die 50 described above). Figure 2A 1. In some embodiments, the logic device 202A is an integrated circuit die, such as a system-on-chip (SoC) die. In some embodiments, the logic device 202A is a die stack, such as a system-on-integrated chip (SoIC) device.

[0046] Each memory device 202B may be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. The memory device 202B may be an integrated circuit die (similar to a device for a processor). Figure 1 The integrated circuit die 50 described above may be a die stack (similar to the integrated circuit die 50 described above). Figure 2B In some embodiments, the memory device 202B is a die stack, such as a high bandwidth memory (HBM) device.

[0047] In the illustrated embodiment, the integrated circuit device 202 is attached to the front side redistribution structure 130 with a solder joint, such as with a conductive connector 204. The conductive connector 204 can be formed of a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 204 is formed by initially forming a solder layer by a method such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, a reflow can be performed to shape the conductive connector 204 into a desired bump shape. Attaching the integrated circuit device 202 to the front side redistribution structure 130 can include: placing the integrated circuit device 202 on the front side redistribution structure 130; and reflowing the conductive connector 204. The integrated circuit device 202 can be placed on the front side redistribution structure 130 using, for example, a pick-and-place tool. The conductive connectors 204 are reflowed to attach the die connectors 206 at the front side of the integrated circuit device 202 to the UBM 136 of the front side redistribution structure 130, thereby electrically connecting the front side redistribution structure 130 to the integrated circuit device 202. In another embodiment, the integrated circuit device 202 is attached to the front side redistribution structure 130 with direct bonding (using the die connectors 206).

[0048] The memory device 202B is disposed directly above the thermal storage die 120. As described in more detail subsequently, the memory device 202B overlaps the thermal storage die 120 in a plan view. The thermal storage die 120 is located in the encapsulant 128. Therefore, the thermal storage die 120 will be embedded in the resulting interposer. The thermal storage die 120 occupies a space in the interposer that may not have been occupied otherwise (e.g., a space in the encapsulant 128 directly below the memory device 202B). Therefore, a heat sink can be incorporated into the integrated circuit package 200 without increasing the package size or increasing the manufacturing complexity other than the placement of the thermal reservoir die 120. During operation, heat can be dissipated from the interconnect die 110 to the thermal storage die 120. Therefore, the operating temperature of the interconnect die 110 can be reduced, which can reduce the accumulation of hot spots in the integrated circuit package 200, which can improve the performance of the integrated circuit package 200 (especially when the interconnect die 110 includes active devices).

[0049] exist Figure 7In the embodiment of the present invention, an underfill 210 is formed around the conductive connector 204 and between the front side redistribution structure 130 and the integrated circuit device 202. The underfill 210 can reduce stress and protect joints created by the reflow of the conductive connector 204. The underfill 210 can be formed of an underfill material, such as a molding compound, an epoxy resin, etc. The underfill 210 can be formed by a capillary flow process after the integrated circuit device 202 is attached to the front side redistribution structure 130, or can be formed by a suitable deposition method before the integrated circuit device 202 is attached to the front side redistribution structure 130. The underfill 210 can be applied in a liquid or semi-liquid form and then subsequently cured.

[0050] The encapsulant 212 is formed around the various components. After being formed, the encapsulant 212 laterally seals the underfill 210 (if present) and the integrated circuit device 202. The encapsulant 212 may be a molding compound, an epoxy resin, or the like. The encapsulant 212 may be applied by compression molding, transfer molding, or the like, and may be formed over the front side redistribution structure 130 so as to bury or cover the integrated circuit device 202. The encapsulant 212 is also formed in the gap areas between the underfill 210 (if present) and / or the integrated circuit device 202. The encapsulant 212 may be applied in a liquid or semi-liquid form, and then subsequently cured.

[0051] A removal process may optionally be performed on the encapsulant 212 to expose the integrated circuit device 202. The removal process may include, for example, a planarization process, such as chemical mechanical polishing (CMP), a grinding process, etc. The top surfaces of the encapsulant 212 and the integrated circuit device 202 may be substantially coplanar after the planarization process (within process variation). Planarization may be omitted, for example, if the integrated circuit device 202 is already exposed.

[0052] exist Figure 8 In the process, carrier substrate peeling is performed to separate (or "peel") carrier substrate 102 from interposer wafer 100. According to some embodiments, peeling includes projecting light, such as laser or UV light, onto release layer 104 so that release layer 104 decomposes under the heat of the light and carrier substrate 102 can be removed. Interposer wafer 100 is then flipped over to prepare for processing the back side of interposer wafer 100. Interposer wafer 100 can be placed on tape, a carrier substrate, or another suitable support structure (not separately shown) for subsequent processing.

[0053] A removal process may optionally be performed on the substrate 112 and the encapsulant 128 to expose the vias 106 and the TSVs 114. The removal process may remove material of the encapsulant 128, the thermal storage die 120, the interconnect die 110 (e.g., the substrate 112 and the TSVs 114), and / or the vias 106 until the TSVs 114 and the vias 106 are exposed. The removal process may include, for example, a planarization process such as chemical mechanical polishing (CMP), a grinding process, etc. The backside surfaces of the encapsulant 128, the thermal storage die 120, the interconnect die 110 (e.g., the substrate 112 and the TSVs 114), and the vias 106 may be substantially coplanar (within process variation) after the planarization process.

[0054] exist Fig. 9 In the embodiment of the present invention, a backside redistribution structure 150 is formed on the backside surface of the encapsulant 128, the thermal storage die 120, the interconnect die 110 (e.g., the substrate 112 and the TSV 114), and the through-hole 106. The backside redistribution structure 150 includes a dielectric layer 152 and a metallization layer 154 (sometimes referred to as a redistribution layer or a redistribution line) in the dielectric layer 152. Therefore, the backside redistribution structure 150 includes metallization layers 154 separated from each other by respective dielectric layers 152. The metallization layers 154 of the backside redistribution structure 150 are connected to the through-hole 106 and to the interconnect die 110 (e.g., the TSV 114).

[0055] In some embodiments, dielectric layer 152 is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithographic mask, such as PBO, polyimide, a BCB-based polymer, etc. In other embodiments, dielectric layer 152 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, etc. Dielectric layer 152 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. After dielectric layer 152 is formed, it may be patterned to expose underlying conductive features, such as portions of vias 106, TSVs 114, and / or metallization layer 154. Patterning may be performed by any acceptable process, such as by exposing the dielectric layer to light when the dielectric layer is formed of a photosensitive material, or by etching using, for example, anisotropic etching. If dielectric layer 152 is formed of a photosensitive material, dielectric layer 152 may be developed after exposure.

[0056] Each of the metallization layers 154 includes a conductive via and / or a conductor. The conductive via extends through the corresponding dielectric layer 152, and the conductor extends along the corresponding dielectric layer 152. As an example of forming the metallization layer 154, a seed layer (not shown separately) is formed above the corresponding lower component. For example, the seed layer can be formed on the corresponding dielectric layer 152 and in any opening through the corresponding dielectric layer 152. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a copper layer above the titanium layer and the titanium layer. The seed layer can be formed using a deposition process, such as PVD, etc. Then a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 154. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as chemical plating or electroplating from a seed layer. The conductive material may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof. The photoresist and the portion of the seed layer on which the conductive material is not formed are then removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, or the like. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms the metallization layer 154 of the backside redistribution structure 150.

[0057] At least some of the metallization layers 154 (e.g., the lower metallization layers 154) include functional redistribution lines 154F and dummy metal sheets 154D. The functional redistribution lines 154F are electrically functional and can be electrically coupled to the interconnect die 110 and the vias 106. The dummy metal sheets 154D are electrically non-functional and can be electrically isolated from the interconnect die 110 (e.g., TSV 114) and the vias 106. As described in more detail later, each dummy metal sheet 154D can have a pattern of openings (portions of the dielectric layer 152 extend through the openings). The dummy metal sheet 154D extends from under the interconnect die 110 to under the thermal storage die 120 adjacent to the interconnect die 110. Optionally, the dummy metal sheet 154D can include a conductive via extending through the underlying dielectric layer 152 to contact the interconnect die 110 (e.g., substrate 112) and the thermal storage die 120. The dummy metal sheet 154D has high thermal conductivity and can help dissipate heat from the interconnect die 110 to the thermal reservoir die 120 during operation. Therefore, the operating temperature of the interconnect die 110 can be reduced, which can improve the performance of the integrated circuit package 200 (especially when the interconnect die 110 includes active devices).

[0058] Backside redistribution structure 150 is shown as an example. More or fewer dielectric layers 152 and metallization layers 154 than shown may be formed by performing the previously described steps any desired number of times.

[0059] Other variations of the backside redistribution structure 150 are contemplated. For example, some of the dielectric layer 152 may be formed of an encapsulant, such as a molding compound, epoxy, etc. The metallization layer 154 may be formed by plating conductive vias from wires. The dielectric layer 152 may be formed by encapsulating such a metallization layer 154. Any desired material stack may be used for the dielectric layer 152.

[0060] The UBM 156 may be formed through the lower dielectric layer 152 of the backside redistribution structure 150. The UBM 156 is physically and electrically coupled to the lower metallization layer 154 of the backside redistribution structure 150. The UBM 156 each includes a conductive via and a conductive bump. The conductive via extends through the lower dielectric layer 152, and the conductive bump extends along the lower dielectric layer 152. The UBM 156 may be formed of the same material as the metallization layer 154. In some embodiments, the UBM 156 has a different size than the metallization layer 154.

[0061] The thermal storage die 120 is located between the front side redistribution structure 130 and the back side redistribution structure 150. Therefore, the thermal storage die 120 will be embedded in the resulting interposer. The thermal storage die 120 is electrically non-functional and can be electrically isolated from the metallization layers of the front side redistribution structure 130 and the back side redistribution structure 150.

[0062] exist Fig.10 , the package substrate 220 is attached to the interposer wafer 100 (e.g., attached to the backside redistribution structure 150). The package substrate 220 includes a substrate core 222, which can be formed of a semiconductor material such as silicon, germanium, diamond, etc. Optionally, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, etc. can also be used. Optionally, the substrate core 222 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as a layer of silicon, germanium, silicon germanium, or a combination thereof. In some embodiments, the substrate core 222 is an insulating core such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin such as FR4. Optional materials for the core material include bismaleimide-triazine (BT) resin, or optionally other printed circuit board (PCB) materials or films. A laminated film such as Ajinomoto Build-up Film (ABF) or other laminated materials can be used for the substrate core 222.

[0063] The substrate core 222 may include passive devices and / or active devices (not shown separately). Devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to generate the structural and functional requirements for the design of the system. The devices may be formed using any suitable method. In some embodiments, the substrate core 222 is substantially free of active and passive devices.

[0064] The substrate core 222 may also include a metallization layer (not shown separately). The package substrate 220 also includes a bonding pad 224 over the metallization layer of the substrate core 222. The metallization layer may be formed over passive devices and / or active devices and is designed to connect the various devices to form a functional circuit. The metallization layer may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), with vias interconnecting the conductive material layers, and may be formed by any suitable process (such as deposition, damascene, etc.).

[0065] The package substrate 220 can be attached to the backside redistribution structure 150 with solder bonding, such as with conductive connectors 226. The conductive connectors 226 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-electroless palladium-immersion gold technology (ENEPIG), etc. The conductive connectors 226 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connectors 226 are formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the solder into the desired bump shape of the conductive connectors 226. Attaching the package substrate 220 to the backside redistribution structure 150 can include: placing the package substrate 220 on the backside redistribution structure 150; and reflowing the conductive connectors 226. The package substrate 220 can be placed on the backside redistribution structure 150 using, for example, a pick and place tool. The conductive connectors 226 are reflowed to attach the bonding pads 224 to the UBMs 156 of the backside redistribution structure 150. The conductive connectors 226 connect the interposer wafer 100 (including the metallization layer of the backside redistribution structure 150) to the package substrate 220 (including the metallization layer of the substrate core 222). Therefore, the package substrate 220 is electrically connected to the integrated circuit devices 202 in the package region 100P.

[0066] In addition, passive devices (not shown separately) can be attached to the interposer wafer 100 and / or the package substrate 220. For example, the passive devices can be attached to the interposer wafer 100, such as to the same surface of the backside redistribution structure 150 as the conductive connector 226. Additionally or alternatively, the passive devices can be attached to the package substrate 220, such as to the same surface of the package substrate 220 as the conductive connector 226. The passive devices can include capacitors, resistors, inductors, etc. or combinations thereof. The passive devices can be surface mount devices (SMDs), 2-terminal integrated passive devices (IPDs), multi-terminal IPDs, etc.

[0067] In some embodiments, an encapsulant 232 is formed around the various components. After formation, the encapsulant 232 laterally seals the passive devices (if present), the conductive connectors 226, and the package substrate 220. The encapsulant 232 may be formed between the package substrate 220 and the backside redistribution structure 150. The encapsulant 232 may be a molding compound, an epoxy, or the like. The encapsulant 232 may be applied by compression molding, transfer molding, or the like. The encapsulant 232 may be applied in a liquid or semi-liquid form and then subsequently cured.

[0068] In addition, a singulation process is performed by cutting along a scribe line region between the package region 100P and an adjacent package region (not shown separately). The singulation process may include sawing, cutting, etc. The singulation process separates the package regions from each other. The resulting, singulated integrated circuit package 200 is from the package region 100P. The singulation process forms the interposer 240 from the singulated portion of the interposer wafer 100. Due to the singulation process, the outer sidewalls of the interposer 240, the sealant 212, and the sealant 232 are laterally coterminal (within the process variation range).

[0069] Fig.11 2 is a plan view of the integrated circuit package 200 , showing the layout of the interconnect die 110 , the thermal storage die 120 , and the integrated circuit device 202 . Fig.10 is along Fig.11 The integrated circuit device 202 is shown with solid lines, while the underlying components (eg, the interconnect die 110 and the thermal storage die 120) are shown with dashed lines.

[0070] The logic device 202A may be larger than the memory device 202B. The integrated circuit device 202 may have a symmetrical layout or an asymmetrical layout in a plan view. In this example, the integrated circuit device 202 has a symmetrical layout in which the memory device 202B is arranged along opposite sides of the logic device 202A.

[0071] The interconnect die 110 will be used for direct communication between the logic device 202A and the memory device 202B. The interconnect die 110 is located in a region disposed between the integrated circuit devices 202, such that each interconnect die 110 is disposed under a plurality of integrated circuit devices 202. In this example, each interconnect die 110 overlaps the logic device 202A and a plurality of memory devices 202B in a plan view, or overlaps a plurality of logic devices 202A in a plan view.

[0072] The thermal storage die 120 may be electrically isolated from the integrated circuit device 202. The thermal storage die 120 is located in an otherwise unoccupied area, specifically, in a space directly below the memory device 202B. The thermal storage die 120 may be disposed directly below the logic device 202A. In this example, each thermal storage die 120 overlaps with a corresponding memory device 202B in a plan view. The thermal storage die 120 may be confined within the edge of the upper memory device 202B in a plan view (e.g., Fig.11 ). The thermal storage die 120 may not be confined within the edge of the upper memory device 202B (as shown in FIG. Fig.10 ).

[0073] Fig.12 is a plan view of an integrated circuit package 200 showing portions of the backside redistribution structure 150—particularly from Fig.10 Components of the metallization layer 154 (including the functional redistribution lines 154F and the plurality of dummy metal sheets 154D) are shown with solid lines, while the components above (eg, the interconnect die 110 and the thermal storage die 120) are shown with dashed lines.

[0074] The dummy metal sheet 154D is a portion of a dummy metal pattern that overlaps the interconnect die 110 and the thermal storage die 120 in a plan view. Each dummy metal sheet 154D overlaps at least one interconnect die 110 and at least one thermal storage die 120 in a plan view. Each dummy metal sheet 154D may extend from below the interconnect die 110 to below the thermal storage die 120. Each dummy metal sheet 154D may include a single, continuous metal layer. Each dummy metal sheet 154D has a pattern of openings 158. The pattern of the openings 158 may be a regular pattern or an irregular pattern. The openings 158 are shown as square openings, but they may be circular openings, slot-shaped openings, etc. A first subset of the openings 158 of the dummy metal sheet 154D is disposed under the interconnect die 110, while a second subset of the openings 158 of the dummy metal sheet 154D is disposed under the thermal storage die 120. The openings 158 may each be the same size, having the same width and the same length. The width of the openings 158 may be substantially equal to the length of the openings 158. In some embodiments, the width of opening 158 is in the range of 10 μm to 30 μm, and the length of opening 158 is in the range of 10 μm to 30 μm. Opening 158 can be sized to accommodate outgassing during thermal expansion under high heat, which can improve the reliability of integrated circuit package 200.

[0075] The functional redistribution line 154F may overlap the interconnection die 110 and the thermal storage die 120 in a plan view. The functional redistribution line 154F may be disposed between two of the dummy metal sheets 154D in a plan view.

[0076] Figures 13 to 14B is a diagram of an integrated circuit package according to some other embodiments. Fig.13 is a cross-sectional view, and FIG. 14A to FIG. 14B is a plan view. This embodiment is similar to Fig.10 , except that the thermal storage core 120 includes a metal feature 122 in its substrate, which can help to further increase the amount of heat dissipated from the interconnect core 110. The metal feature 122 can extend from the front side surface of the thermal storage core 120 to the back side surface of the thermal storage core 120. Before packaging the thermal storage core 120, the metal feature 122 can be formed in the substrate of the thermal storage core 120 (for example, by acceptable etching and plating techniques). The metal feature 122 can be a through substrate via (TSV), such as a through silicon via, etc. The metal feature 122 is electrically non-functional and can be electrically isolated from the metallization layers of the front side redistribution structure 130 and the back side redistribution structure 150. Optionally, when the dummy metal sheet 154D includes a conductive via, the conductive via can extend through the underlying dielectric layer 152 to contact the interconnect core 110 (for example, the substrate 112) and the metal feature 122 of the thermal storage core 120.

[0077] FIG. 14A to FIG. 14B FIG. 1 is a plan view of the heat storage core 120, showing the layout of the metal component 122. The metal component 122 may be a metal column, such as Fig.14A The metal component 122 may be a metal plate, such as Fig. 14B Other types of metal components 122 may also be utilized.

[0078] Fig.15 is a cross-sectional view of an integrated circuit package 200 according to some other embodiments. Fig.10 The embodiment of the present invention differs in that a thermal interface material 124 is formed between adjacent pairs of the thermal storage die 120 and the interconnection die 110. The thermal interface material 124 may be a metal paste (e.g., silver paste, indium solder paste, etc.), a polymer material (e.g., a molding compound, which may (or may not) have a high k value), etc., which may be formed by dispensing, printing, etc. In this embodiment, the thermal interface material 124 is different from the sealant 128.

[0079] Fig.16 is a cross-sectional view of an integrated circuit package 200 according to some other embodiments. Fig.10 Embodiments of the present invention are different in that additional interconnect die 110R is used to replace some of the thermal storage die 120. The additional interconnect die 110R can be confined within the edge of the upper memory device 202B in a plan view (similar to the thermal storage die 120). The additional interconnect die 110R can be substantially free of active devices, and therefore can consume a low amount of power and generate a low amount of heat during operation. Such an interconnect die 110R may also be able to act as a heat sink to draw heat away from the interconnect die 110A having active devices during operation. The substrate 112 of the interconnect die 110R may be larger than the substrate 112 of the interconnect die 110A (in a plan view). Optionally, the dummy metal sheet 154D may include a conductive via extending through the underlying dielectric layer 152 to contact the interconnect die 110A (e.g., substrate 112) and the interconnect die 110R (e.g., substrate 112).

[0080] Embodiments can achieve advantages. The thermal storage die 120 is a heat sink that draws heat away from the interconnect die 110 during operation. Specifically, during operation, heat can be dissipated from the interconnect die 110 to the thermal storage die 120. In addition, the dummy metal sheet 154D having a high thermal conductivity can help dissipate heat from the interconnect die 110 to the thermal storage die 120 during operation. Therefore, the operating temperature of the interconnect die 110 can be reduced, which can improve the performance of the integrated circuit package 200 (especially when the interconnect die 110 includes active devices).

[0081] In an embodiment, a device includes: an interposer including: a front-side redistribution structure; a back-side redistribution structure; an encapsulant located between the front-side redistribution structure and the back-side redistribution structure; an interconnect die located in the encapsulant; and a thermal storage die located in the encapsulant, the thermal storage die being adjacent to the interconnect die; a memory device attached to the front-side redistribution structure, the memory device overlapping the thermal storage die in a plan view; and a logic device attached to the front-side redistribution structure, the logic device and the memory device each overlapping the interconnect die in a plan view. In some embodiments of the device, the thermal storage die includes a semiconductor substrate. In some embodiments of the device, the thermal storage die includes a metal substrate. In some embodiments of the device, the thermal storage die includes: a substrate; and a metal component located in the substrate. In some embodiments of the device, the thermal storage die is confined within the edge of the memory device in a plan view. In some embodiments of the device, the interconnect die includes a die bridge connecting the memory device to the logic device. In some embodiments of the device, the back-side redistribution structure includes: a dummy metal pattern, the interconnect die and the thermal storage die each overlapping the dummy metal pattern in a plan view. In some embodiments, the device further includes: a packaging substrate attached to the backside redistribution structure.

[0082] In an embodiment, a device comprises: a package substrate; an interposer comprising: a backside redistribution structure attached to the package substrate, the backside redistribution structure comprising a first dummy metal sheet having a first opening; an interconnect die located above the backside redistribution structure; a thermal storage die located above the backside redistribution structure, the first dummy metal sheet extending from below the interconnect die to below the thermal storage die; an encapsulant located around the interconnect die and the thermal storage die; and a frontside redistribution structure located above the encapsulant; and an integrated circuit device attached to the frontside redistribution structure. In some embodiments of the device, the width of the first opening is substantially equal to the length of the first opening. In some embodiments of the device, each of the first openings has the same width and the same length. In some embodiments of the device, the backside redistribution structure further comprises: a second dummy metal sheet having a second opening; and a functional redistribution line located between the first dummy metal sheet and the second dummy metal sheet. In some embodiments of the device, the interposer further comprises: a thermal interface material located between the thermal storage die and the interconnect die. In some embodiments of the device, the interconnect die comprises an active device. In some embodiments of the device, a surface of the encapsulant is substantially coplanar with a surface of the thermal storage die.

[0083] In an embodiment, the method includes: sealing the interconnect die and the thermal storage die with an encapsulant, the front side surface of the encapsulant being substantially coplanar with the front side surface of the thermal storage die; forming a front side redistribution structure on the front side surface of the encapsulant and the front side surface of the thermal storage die, the front side redistribution structure including a first redistribution line connected to the interconnect die; and attaching a logic device and a memory device to the front side redistribution structure, the memory device overlapping the thermal storage die in a plan view. In some embodiments of the method, the thermal storage die is confined within the edge of the memory device in a plan view. In some embodiments of the method, the logic device and the memory device each overlap the interconnect die in a plan view. In some embodiments of the method, the method further includes: forming a back side redistribution structure on the back side surface of the encapsulant and the back side surface of the thermal storage die; and attaching a package substrate to the back side redistribution structure. In some embodiments of the method, the back side redistribution structure is formed after attaching the logic device and the memory device to the front side redistribution structure.

[0084] Some embodiments of the present application provide a semiconductor device, comprising: an interposer, comprising: a front-side redistribution structure; a back-side redistribution structure; an encapsulant located between the front-side redistribution structure and the back-side redistribution structure; an interconnect die located in the encapsulant; and a thermal storage die located in the encapsulant, the thermal storage die being adjacent to the interconnect die; a memory device attached to the front-side redistribution structure, the memory device overlapping with the thermal storage die in a plan view; and a logic device attached to the front-side redistribution structure, the logic device and the memory device each overlapping with the interconnect die in a plan view.

[0085] In some embodiments, the thermal storage die includes a semiconductor substrate. In some embodiments, the thermal storage die includes a metal substrate. In some embodiments, the thermal storage die includes: a substrate; and a metal component located in the substrate. In some embodiments, the thermal storage die is confined within the edge of the memory device in the plan view. In some embodiments, the interconnect die includes a die bridge connecting the memory device to the logic device. In some embodiments, the backside redistribution structure includes: a dummy metal pattern, each of the interconnect die and the thermal storage die overlaps the dummy metal pattern in the plan view. In some embodiments, the semiconductor device further includes: a packaging substrate attached to the backside redistribution structure.

[0086] Some other embodiments of the present application provide a semiconductor device, including: a packaging substrate; an interposer, including: a back-side redistribution structure attached to the packaging substrate, the back-side redistribution structure including a first dummy metal sheet having a first opening; an interconnect die located above the back-side redistribution structure; a thermal storage die located above the back-side redistribution structure, the first dummy metal sheet extending from under the interconnect die to under the thermal storage die; an encapsulant located around the interconnect die and the thermal storage die; and a front-side redistribution structure located above the encapsulant; and an integrated circuit device attached to the front-side redistribution structure.

[0087] In some embodiments, the width of the first opening is substantially equal to the length of the first opening. In some embodiments, each of the first openings has the same width and the same length. In some embodiments, the backside redistribution structure further includes: a second dummy metal sheet having a second opening; and a functional redistribution line located between the first dummy metal sheet and the second dummy metal sheet. In some embodiments, the interposer further includes: a thermal interface material located between the thermal storage die and the interconnect die. In some embodiments, the interconnect die includes an active device. In some embodiments, a surface of the encapsulant is substantially coplanar with a surface of the thermal storage die.

[0088] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: sealing an interconnect die and a thermal storage die with a sealant, wherein a front side surface of the sealant is substantially coplanar with a front side surface of the thermal storage die; forming a front side redistribution structure on the front side surface of the sealant and the front side surface of the thermal storage die, wherein the front side redistribution structure comprises a first redistribution line connected to the interconnect die; and attaching a logic device and a memory device to the front side redistribution structure, wherein the memory device overlaps with the thermal storage die in a plan view.

[0089] In some embodiments, the thermal storage die is confined within the edge of the memory device in the plan view. In some embodiments, the logic device and the memory device each overlap the interconnect die in the plan view. In some embodiments, the method further comprises: forming a backside redistribution structure on a backside surface of the encapsulant and a backside surface of the thermal storage die; and attaching a package substrate to the backside redistribution structure. In some embodiments, the backside redistribution structure is formed after attaching the logic device and the memory device to the frontside redistribution structure.

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: The intermediary layer includes: Front redistribution structure; Dorsal redistribution structures; a sealant disposed between the front-side redistribution structure and the back-side redistribution structure; an interconnect die disposed in the encapsulant; and a thermal storage die in the encapsulant, the thermal storage die being adjacent to the interconnect die; a memory device attached to the front side redistribution structure, the memory device overlapping the thermal storage die in plan view; and A logic device is attached to the front side redistribution structure, the logic device and the memory device each overlapping the interconnect die in a plan view.

2. The semiconductor device according to claim 1, wherein The thermal storage core includes a semiconductor substrate.

3. The semiconductor device according to claim 1, wherein The thermal storage core includes a metal substrate.

4. The semiconductor device according to claim 1, wherein: The heat storage tube core comprises: substrate; and A metal component is located in the substrate.

5. The semiconductor device according to claim 1, wherein The thermal storage die is confined within the edge of the memory device in the plan view.

6. The semiconductor device according to claim 1, wherein The interconnect die includes a die bridge connecting the memory device to the logic device.

7. The semiconductor device according to claim 1, wherein The backside redistribution structure comprises: A dummy metal pattern, the interconnect die and the thermal storage die each overlap with the dummy metal pattern in the plan view.

8. The semiconductor device according to claim 1, further comprising: A package substrate is attached to the backside redistribution structure.

9. A semiconductor device comprising: Package substrate; The intermediary layer includes: a backside redistribution structure attached to the package substrate, the backside redistribution structure comprising a first dummy metal sheet having a first opening; an interconnect die located above the backside redistribution structure; A heat storage core is located above the backside redistribution structure, and the first dummy metal sheet extends from below the interconnection core to below the heat storage core; an encapsulant disposed around the interconnect die and the thermal storage die; and a front-side redistribution structure located above the sealant; and An integrated circuit device is attached to the front-side redistribution structure.

10. A method of forming a semiconductor device, comprising: Sealing the interconnection die and the thermal storage die with a sealant, wherein the front side surface of the sealant is substantially coplanar with the front side surface of the thermal storage die; forming a front side redistribution structure on the front side surface of the encapsulant and the front side surface of the thermal storage die, the front side redistribution structure comprising a first redistribution line connected to the interconnect die; as well as Logic devices and memory devices are attached to the front side redistribution structure, the memory devices overlapping the thermal storage die in plan view.

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