Semiconductor device and preparation method thereof
By setting a trench isolation structure and an electrical lead-out structure on the top silicon layer of the semiconductor device, the problem of voltage coupling between devices on both sides of the deep trench isolation structure is solved, the working performance of the device is improved and the circuit area is reduced.
Patent Information
- Application Number
- CN202311347130.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-17
- Publication Date
- 2025-04-18
AI Technical Summary
Devices on both sides of the deep trench isolation structure are prone to voltage coupling when switching the working voltage, which affects the working status of the device.
A semiconductor device is designed in which a plurality of device regions arranged spaced apart on the top silicon layer and a partial structure of at least two trench isolation structures is provided between adjacent device regions. These trench isolation structures are provided with lead-out regions, and an electrical lead-out structure electrically connected to the top silicon layer is formed on the lead-out region.
Through the design of the trench isolation structure and the electrical lead-out structure, adjacent device areas are effectively isolated, mutual interference between devices is reduced, voltage coupling phenomenon is improved, the working performance of semiconductor devices is improved, and circuit area is reduced.
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Figure CN119852249A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a method for preparing the same. Background Art
[0002] As the integration of components within integrated circuits continues to increase, the distance between adjacent components is shortened, and the possibility of electronic interference between adjacent components is also increased. Therefore, a proper isolation structure is necessary.
[0003] Deep trench isolation structures are widely used in today's semiconductor technology. Deep trench isolation structures have good isolation properties and can integrate various high and low voltage devices such as analog, digital and high voltage. For example, deep trench isolation structures can be used as isolation structures to isolate electronic devices with different operating voltages. However, in actual operation, the devices on both sides of the deep trench isolation structure will experience voltage coupling as the operating voltage of the device switches, which affects the working state of the device. Summary of the invention
[0004] Based on this, it is necessary to provide a semiconductor device and a method for manufacturing the same to address the above problems.
[0005] In order to achieve the above objectives, in a first aspect, the present application provides a semiconductor device, the semiconductor device comprising:
[0006] Base layer;
[0007] A buried layer, disposed on the base layer;
[0008] A top silicon layer is disposed on the buried layer; the top silicon layer has a plurality of device regions arranged at intervals;
[0009] A plurality of trench isolation structures arranged at intervals are provided on the top silicon layer; at least two portions of the trench isolation structures are located between two adjacent device regions;
[0010] Among the at least two trench isolation structures, a lead-out region is provided between two adjacent trench isolation structures, and the lead-out region is provided with an electrical lead-out structure electrically connected to the top silicon layer.
[0011] In one embodiment, at least one trench isolation structure is disposed around the periphery of each device region.
[0012] In one embodiment, the trench isolation structure includes a first trench isolation structure and a second trench isolation structure, each device area is surrounded by a first trench isolation structure, and the second trench isolation structure is surrounded to form a layout area, and the device area and the first trench isolation structure are both located in the layout area.
[0013] In one embodiment, the lead-out region between the first trench isolation structure and the second trench isolation structure is adjacent to the lead-out region between two adjacent first trench isolation structures;
[0014] An electrical lead-out structure is provided on the top silicon layer.
[0015] In one embodiment, the electrical lead-out structure comprises:
[0016] A heavily doped region, disposed in the top silicon layer and located in the lead-out region;
[0017] The conductive structure is disposed on the top silicon layer and is electrically connected to the heavily doped region.
[0018] In one of the embodiments, the trench isolation structure extends from the surface of the top silicon layer toward the buried layer and penetrates the top silicon layer;
[0019] The trench isolation structure has a first end adjacent to the buried layer and a second end away from the buried layer; the orthographic projection outer contour of the second end on the buried layer is located outside the orthographic projection outer contour of the first end on the buried layer.
[0020] In one embodiment, the trench isolation structure includes an isolation trench and a dielectric layer filled in the isolation trench, wherein the isolation trench extends from the surface of the top silicon layer toward the buried layer and penetrates the top silicon layer;
[0021] The dimension of the isolation trench at one end close to the buried layer along the first direction is smaller than the dimension of the isolation trench at one end away from the buried layer along the first direction; the first direction is perpendicular to the thickness direction of the base layer and the length direction of the isolation trench.
[0022] In one embodiment, the isolation trench includes a first sub-trench and a second sub-trench, the second sub-trench is arranged on a side of the first sub-trench away from the buried layer; one end of the first sub-trench is adjacent to the buried layer, and the other end is connected to the second sub-trench;
[0023] Along the direction away from the base layer, the size of the first sub-groove along the first direction gradually increases.
[0024] In one embodiment, the dimension of the isolation trench along the thickness direction of the base layer is a first dimension, the dimension of the first sub-trench along the thickness direction of the base layer is a second dimension, and the ratio of the second dimension to the first dimension is between 0.1-0.2.
[0025] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor device, comprising:
[0026] A base layer is provided with a buried layer and a top silicon layer; the buried layer is provided on the base layer, the top silicon layer is provided on the buried layer; and a plurality of device regions are arranged at intervals on the top silicon layer;
[0027] A plurality of trench isolation structures are formed on the top silicon layer and arranged at intervals; at least two of the trench isolation structures have partial structures located between two adjacent device regions; and a lead-out region is provided between two adjacent trench isolation structures in the at least two trench isolation structures;
[0028] An electrical lead-out structure electrically connected to the top silicon layer is formed on the top silicon layer, and the electrical lead-out structure is located in the lead-out region.
[0029] In one embodiment, the step of forming a plurality of trench isolation structures arranged at intervals on the top silicon layer comprises:
[0030] forming a patterned mask layer on the top silicon layer;
[0031] Performing a first etching on the top silicon layer based on the patterned mask layer to form a second sub-trench in the top silicon layer;
[0032] The top silicon layer is etched for a second time based on the patterned mask layer to form a first sub-groove in the top silicon layer; wherein the second sub-groove and the first sub-groove together constitute the isolation groove; along the direction away from the base layer, the size of the first sub-groove along the first direction gradually increases; the first direction is perpendicular to the thickness direction of the base layer and the length direction of the isolation groove;
[0033] A dielectric layer is filled in the isolation trench to form the trench isolation structure.
[0034] In one embodiment, a dry etching process is used to perform a first etching and a second etching on the top silicon layer; the etching rate of the second etching is lower than the etching rate of the first etching.
[0035] In one of the embodiments, the process gas of the dry etching process includes etching gas and auxiliary gas;
[0036] The ratio of the auxiliary gas to the etching gas in the first etching is a first value, and the ratio of the auxiliary gas to the etching gas in the second etching is a second value, and the second value is greater than the first value.
[0037] In one embodiment, the etching gas includes at least one of SF6, C4F8 and CF4;
[0038] And / or, the auxiliary gas includes at least one of O2 and N2.
[0039] In one embodiment, the step of forming an electrical lead-out structure electrically connected to the top silicon layer on the top silicon layer, wherein the electrical lead-out structure is located in the lead-out region, comprises:
[0040] forming a heavily doped region in the top silicon layer, wherein the heavily doped region is located in the lead-out region;
[0041] forming an isolation layer on the top silicon layer;
[0042] A conductive structure is formed on the isolation layer, wherein the conductive structure penetrates the isolation layer and is electrically connected to the heavily doped region.
[0043] The semiconductor device and the preparation method thereof provided in the embodiment of the present application are provided by providing at least two partial structures of the trench isolation structure between two adjacent device regions, and providing an electrical lead-out structure in the lead-out region between the two adjacent trench isolation structures. Thus, on the one hand, the at least two trench isolation structures can better isolate the two adjacent device regions and reduce the mutual interference between the devices in the two device regions; on the other hand, the electrical lead-out structure can conduct the induced charges between the trench isolation structures, thereby improving the voltage coupling phenomenon of the devices on both sides of the trench isolation structure, which is beneficial to improving the working performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0045] Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device provided in one embodiment of the present application.
[0046] Figure 2 for Figure 1 A schematic top view of a semiconductor device is shown.
[0047] Figure 3 for Figure 1 Another schematic top view of the semiconductor device is shown.
[0048] Figure 4A schematic flow chart of a method for preparing a semiconductor device provided in one embodiment of the present application.
[0049] Figure 5 for Figure 4 A schematic diagram of a process flow of S200 in the preparation method shown.
[0050] Figure 6 for Figure 4 A schematic diagram of a process of S300 in the preparation method shown.
[0051] Figures 7 to 16 for Figure 4 Schematic diagram of the cross-sectional structure of the device structure during the preparation method shown.
[0052] Description of reference numerals:
[0053] 1. semiconductor device; 11. base layer; 12. buried layer; 13. top silicon layer; 13a. device area; 13b. lead-out area; 14. trench isolation structure; 14a. first trench isolation structure; 14b. second trench isolation structure; 14c. first end; 14d. second end; 141. isolation trench; 1411. first sub-trench; 1412. second sub-trench; 142. dielectric layer; 15. electrical lead-out structure; 151. heavily doped area; 152. conductive structure; 16. isolation layer; 21. etching stop layer; 22. first photoresist layer; 23. second photoresist layer. DETAILED DESCRIPTION
[0054] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0056] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0057] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0059] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.
[0060] As described in the background art, the devices on both sides of the deep trench isolation structure will experience voltage coupling in actual operation as the operating voltage of the devices is switched. Specifically, among the devices on both sides of the deep trench isolation structure, when the operating voltage of the device on one side is switched during operation, an induced potential is easily generated on the other side of the deep trench isolation structure, and affects the device on that side.
[0061] In related semiconductor devices, the voltage coupling phenomenon is avoided by increasing the distance between the device and the deep trench isolation structure. However, this structure leads to a significant increase in circuit area.
[0062] In view of the above problems, an embodiment of the present application provides a semiconductor device and a method for preparing the same, which can, on the one hand, improve the voltage coupling phenomenon of devices on both sides of the trench isolation structure, which is beneficial to improving the working performance of the semiconductor device; on the other hand, compared with the related technology, can reduce the circuit area.
[0063] Specifically, the semiconductor device 1 includes a base layer 11, a buried layer 12, a top silicon layer 13 and a plurality of trench isolation structures 14, wherein the buried layer 12 is disposed on the base layer 11. The top silicon layer 13 is disposed on the buried layer 12. The top silicon layer 13 has a plurality of device regions 13a arranged at intervals. The trench isolation structure 14 is disposed on the top silicon layer 13. Partial structures of at least two isolation structures 14 are located between two adjacent device regions 13a. In one example, taking two isolation structures 14 as an example, a partial structure of one isolation structure 14 is located between two adjacent device regions 13a, a partial structure of another isolation structure 14 is also located between the two adjacent device regions 13a, and the portions of the two isolation structures 14 located between the two device regions 13a are arranged side by side between the two device regions 13a.
[0064] Furthermore, in the at least two trench isolation structures 14 , a lead-out region 13 b is provided between two adjacent trench isolation structures 14 , and the lead-out region 13 b is provided with an electrical lead-out structure 15 electrically connected to the top silicon layer 13 .
[0065] Here, it should be noted that the device region 13 a is a region for arranging the component structure, and the lead-out region 13 b is a region for arranging the electrical lead-out structure 15 .
[0066] In one example, at least two partial structures of trench isolation structures 14 are provided between any two adjacent device regions 13a. Exemplarily, three device regions 13a are provided on the top silicon layer 13, namely, a first device region, a second device region, and a third device region, wherein the second device region is located between the first device region and the third device region. Further, at least two partial structures of isolation structures 14 are located between the first device region and the second device region, and at least two partial structures of isolation structures 14 are located between the second device region and the third device region.
[0067] In another example, three device regions 13a are provided on the top silicon layer 13, namely, the first device region, the second device region and the third device region, wherein the second device region is located between the first device region and the third device region. Since the operating voltage of the devices in the first device region is higher, and the operating voltages of the devices in the second device region and the third device region are lower, the devices in the first device region and the devices in the second device region are prone to voltage coupling, while the devices in the second device region and the devices in the third device region are not prone to voltage coupling. Then, at least two portions of the trench isolation structures 14 are located between the first device region and the second device region, and a portion of the trench isolation structure 14 is located between the second device region 13a and the third device region 13a.
[0068] The semiconductor device 1 provided in the embodiment of the present application has at least two trench isolation structures 14 partially located between two adjacent device regions 13a, so that the at least two trench isolation structures 14 can better isolate the two adjacent device regions 13a and reduce the mutual interference between the devices in the two device regions 13a. By providing an electrical lead-out structure 15 in the lead-out region 13b between the two adjacent trench isolation structures 14, on the one hand, the electrical lead-out structure 15 can conduct the induced charges between the trench isolation structures 14, thereby improving the voltage coupling phenomenon of the devices on both sides of the trench isolation structure 14, which is beneficial to improving the working performance of the semiconductor device 1; on the other hand, compared with the related art, there is no need to increase the distance between the devices in the device region 13a and the trench isolation structure 14, which is beneficial to reducing the circuit area.
[0069] It can be understood that the trench isolation structure 14 can be a ring structure or a strip structure.
[0070] In one embodiment, the materials of the base layer 11 and the top silicon layer 13 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound or low temperature polysilicon (LTPS), or other materials known to those skilled in the art.
[0071] In one embodiment, the material of the buried layer 12 may be silicon dioxide, silicon nitride or silicon oxyfluoride. In another embodiment, the material of the buried layer 12 may also be other dielectric materials with a dielectric constant smaller than that of silicon dioxide.
[0072] In one embodiment, referring to Figure 2 As shown, at least one trench isolation structure 14 is disposed around the periphery of each device region 13 a .
[0073] In a specific example, a trench isolation structure 14 is disposed around the periphery of each device region 13 a . Thus, two adjacent device regions 13 a are isolated by two trench isolation structures 14 .
[0074] In a specific example, referring to Figure 3 As shown, two trench isolation structures 14 are disposed around the periphery of each device region 13 a , so that the anti-interference performance of the devices in the device region 13 a can be improved.
[0075] In one embodiment, referring to Figure 2 As shown, the trench isolation structure 14 includes a first trench isolation structure 14a and a second trench isolation structure 14b. Each device region 13a is surrounded by a first trench isolation structure 14a, and the second trench isolation structure 14b is surrounded to form a layout area (not marked in the figure). The device region 13a and the first trench isolation structure 14a are both located in the layout area.
[0076] In this way, while ensuring the device isolation performance, the number of trench isolation structures 14 on the top silicon layer 13 can be reduced, which is beneficial to reducing the circuit area.
[0077] In one embodiment, the lead-out region 13b between the first trench isolation structure 14a and the second trench isolation structure 14b is adjacent to the lead-out region 13b between two adjacent first trench isolation structures 14a. An electrical lead-out structure 15 is provided on the top silicon layer 13. In this way, only one electrical lead-out structure 15 is required to conduct away the induced charges in all the lead-out regions 13b, which is beneficial to reduce the number of electrical lead-out structures 15.
[0078] In one embodiment, referring to Figure 1As shown, the electrical extraction structure 15 includes a heavily doped region 151 and a conductive structure 152. The heavily doped region 151 is disposed in the top silicon layer 13 and located in the extraction region 13b. The conductive structure 152 is disposed on the top silicon layer 13 and is electrically connected to the heavily doped region 151. In this way, the induced charges on the top silicon layer 13 located in the extraction region 13b can be sequentially extracted through the heavily doped region 151 and the electrical extraction structure 15.
[0079] In one embodiment, the semiconductor device 1 further includes an isolation layer 16 disposed on the top silicon layer 13, and the conductive structure 152 penetrates the isolation layer 16 and is electrically connected to the heavily doped region 151. The isolation layer 16 can protect the component structure disposed in the top silicon layer 13.
[0080] In one embodiment, referring to Figure 1 As shown, the trench isolation structure 14 extends from the surface of the top silicon layer 13 toward the buried layer 12 and penetrates the top silicon layer 13. The trench isolation structure 14 has a first end 14c adjacent to the buried layer 12 and a second end 14d away from the buried layer 12. The orthographic projection outer contour of the second end 14d on the buried layer 12 is located outside the orthographic projection outer contour of the first end 14c on the buried layer 12.
[0081] In this way, during the process of manufacturing the semiconductor device 1 , it is possible to prevent the top silicon layer 13 between two adjacent trench isolation structures 14 from being etched through, which is beneficial to improving process stability.
[0082] In one embodiment, the trench isolation structure 14 includes an isolation trench 141 and a dielectric layer 142 filled in the isolation trench 141. The isolation trench 141 extends from the surface of the top silicon layer 13 toward the buried layer 12 and penetrates the top silicon layer 13. The dimension of the end of the isolation trench 141 close to the buried layer 12 along the first direction X is smaller than the dimension of the end of the isolation trench 141 away from the buried layer 12 along the first direction X. The first direction X is perpendicular to the thickness direction of the base layer 11 and the length direction of the isolation trench 141.
[0083] In this way, during the process of manufacturing the semiconductor device 1 , it is possible to prevent the top silicon layer 13 between two adjacent isolation trenches 141 from being etched through, which is beneficial to improving process stability.
[0084] In one embodiment, the isolation trench 141 includes a first sub-groove 1411 and a second sub-groove 1412, and the second sub-groove 1412 is arranged on a side of the first sub-groove 1411 away from the buried layer 12. One end of the first sub-groove 1411 is adjacent to the buried layer 12, and the other end is connected to the second sub-groove 1412. Along the direction away from the base layer 11, the size of the first sub-groove 1411 along the first direction X gradually increases. In one example, along the direction away from the base layer 11, the size of the second sub-groove 1412 in the first direction X is equal everywhere. In one example, the size of the first sub-groove 1411 along the first direction X is the width of the first sub-groove 1411, and the size of the second sub-groove 1412 in the first direction X is the width of the second sub-groove 1412.
[0085] In this way, during the process of manufacturing the semiconductor device 1 , it is possible to prevent the top silicon layer 13 between two adjacent isolation trenches 141 from being etched through, which is beneficial to improving process stability.
[0086] In one embodiment, the dimension of the isolation trench 141 along the thickness direction of the base layer 11 is a first dimension, and in one example, the first dimension is the depth of the isolation trench 141. The dimension of the first sub-groove 1411 along the thickness direction of the base layer 11 is a second dimension, and in one example, the second dimension is the depth of the first sub-groove 1411. The ratio of the second dimension to the first dimension is between 0.1 and 0.2. Exemplarily, the ratio of the second dimension to the first dimension may be 0.1, 0.12, 0.15, 0.17, 0.19, or 0.2.
[0087] Thus, a faster etching rate can be used to form the second sub-groove 1412, and a slower etching rate can be used to form the first sub-groove 1411. By making the ratio of the second size to the first size within the above range, it is beneficial to control the depth of the first sub-groove 1411, thereby minimizing the etching time of the isolation trench 141.
[0088] Second, refer to Figure 4 As shown, the embodiment of the present application provides a method for preparing a semiconductor device, which specifically includes the following steps:
[0089] S100: Provide a base layer 11 having a buried layer 12 and a top silicon layer 13. The buried layer 12 is disposed on the base layer 11, and the top silicon layer 13 is disposed on the buried layer 12. The top silicon layer 13 has a plurality of device regions 13a arranged at intervals. Exemplarily, the materials of the base layer 11 and the top silicon layer 13 may be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound or low temperature polycrystalline silicon (LTPS), or other materials known to those skilled in the art. The material of the buried layer 12 may be silicon dioxide, silicon nitride or silicon oxyfluoride.
[0090] S200: forming a plurality of trench isolation structures 14 arranged at intervals on the top silicon layer 13. Partial structures of at least two trench isolation structures 14 are located between two adjacent device regions 13a. Among the at least two trench isolation structures 14, a lead-out region 13b is provided between two adjacent trench isolation structures 14.
[0091] S300 : forming an electrical lead-out structure 15 electrically connected to the top silicon layer 13 on the top silicon layer 13 , wherein the electrical lead-out structure 15 is located in the lead-out region 13 b .
[0092] The method for preparing a semiconductor device provided in an embodiment of the present application makes part of the structure of at least two trench isolation structures 14 located between two adjacent device regions 13a, so that the at least two trench isolation structures 14 can better isolate the two adjacent device regions 13a and reduce the mutual interference between the devices in the two device regions 13a. By setting an electrical lead-out structure 15 in the lead-out region 13b between two adjacent trench isolation structures 14, on the one hand, the electrical lead-out structure 15 can conduct the induced charges between the trench isolation structures 14, thereby improving the voltage coupling phenomenon of the devices on both sides of the trench isolation structure 14, which is beneficial to improving the working performance of the semiconductor device 1; on the other hand, compared with the related art, there is no need to increase the distance between the device in the device region 13a and the trench isolation structure 14, which is beneficial to reducing the circuit area.
[0093] In one embodiment, referring to Figure 5 S200: forming a plurality of trench isolation structures 14 arranged at intervals on the top silicon layer 13, specifically comprising the following steps:
[0094] S210 : forming a patterned mask layer on the top silicon layer 13 .
[0095] In a specific embodiment, referring to Figure 7 , Figure 8 and Fig. 9 As shown, S210 specifically includes the following steps:
[0096] S211: forming an etching stop layer 21 on the top silicon layer 13. The etching stop layer 21 may be made of silicon nitride.
[0097] S212 : forming a first photoresist layer 22 on the etching stop layer 21 , and exposing and developing the first photoresist layer 22 to define a first etching window.
[0098] S213: etching the etch stop layer 21 based on the first etch window to form a patterned mask layer.
[0099] Reference Fig.10 and Fig.11AAs shown, after S213 is completed, the following steps are then performed:
[0100] S220 : performing a first etching on the top silicon layer 13 based on the patterned mask layer to form a second sub-trench 1412 in the top silicon layer 13 .
[0101] S230: etching the top silicon layer 13 for a second time based on the patterned mask layer to form a first sub-groove 1411 in the top silicon layer 13. The second sub-groove 1412 and the first sub-groove 1411 together constitute the isolation groove 141. In the direction away from the base layer 11, the size of the first sub-groove 1411 along the first direction X gradually increases. The first direction X is perpendicular to the thickness direction of the base layer 11 and the length direction of the isolation groove 141. Exemplarily, the size of the first sub-groove 1411 along the first direction X is the width of the first sub-groove 1411.
[0102] S240: Fill the isolation trench 141 with a dielectric layer 142 to form a trench isolation structure 14. Exemplarily, the dielectric layer 142 is made of silicon dioxide.
[0103] It should be noted that forming the isolation trench 141 by etching twice can, on the one hand, reduce the etching time of the isolation trench 141, and on the other hand, form a "narrow bottom and wide top" trench structure to avoid etching through the top silicon layer 13 between two adjacent trench isolation structures 14, which is beneficial to improving process stability.
[0104] It should be noted that, refer to Fig. 11B As shown, the isolation trench 141 can also be formed by a single etching process. However, the bottom of the isolation trench 141 formed by a single etching process is prone to "hollowing out", which makes the preparation process of the semiconductor device 1 have the risk of poor stability. The isolation trench 141 formed by two etching processes can avoid the formation of the "hollowing out" phenomenon.
[0105] In one embodiment, a dry etching process is used to perform a first etching and a second etching on the top silicon layer 13. The etching rate of the second etching is lower than the etching rate of the first etching. In this way, when etching the bottom of the isolation trench 141, the etching rate is low, which is conducive to avoiding the "inward hollowing" phenomenon, thereby forming a "narrow bottom and wide top" trench structure.
[0106] In one embodiment, the process gas of the dry etching process includes an etching gas and an auxiliary gas. The ratio of the auxiliary gas to the etching gas in the first etching is a first value, and the ratio of the auxiliary gas to the etching gas in the second etching is a second value, and the second value is greater than the first value.
[0107] In this way, by adjusting the ratio of the etching gas and the auxiliary gas in the process gas, the etching rate of the second etching can be made different from the etching rate of the first etching.
[0108] In a specific example, the ratio of the auxiliary gas to the etching gas in the first etching is 1. The ratio of the auxiliary gas to the etching gas in the second etching is 1.2.
[0109] In one embodiment, the etching gas includes at least one of SF6, C4F8 and CF4.
[0110] In one embodiment, the auxiliary gas includes at least one of O2 and N2.
[0111] In one embodiment, the power of the first etching is the same as that of the second etching, and further, the power is between 450W-600W.
[0112] In one embodiment, the chamber pressure of the first etching and the chamber pressure of the second etching are the same. Further, the chamber pressure is between 25 MPa and 40 MPa.
[0113] In one embodiment, referring to Fig.12 and Fig.13 As shown, after the dielectric layer 142 is filled, the etching stop layer 21 needs to be removed and the surface of the top silicon layer 13 needs to be planarized.
[0114] In one embodiment, referring to Figure 6 As shown, S300: forming an electrical lead-out structure 15 electrically connected to the top silicon layer 13 on the top silicon layer 13, wherein the electrical lead-out structure 15 is located in the lead-out region 13b, specifically comprising the following steps:
[0115] S310 : forming a heavily doped region 151 in the top silicon layer 13 , wherein the heavily doped region 151 is located in the lead-out region 13 b .
[0116] Specifically, refer to Fig.14 and Fig.15 As shown, first, a second photoresist layer 23 is formed on the top silicon layer 13, and the second photoresist layer 23 is exposed and developed to define a second etching window. Then, ion implantation is performed on the top silicon layer 13 in the lead-out region 13b based on the second etching window to form a heavily doped region 151.
[0117] S320: forming an isolation layer 16 on the top silicon layer 13. Exemplarily, the isolation layer 16 may be formed by a chemical vapor deposition process. The isolation layer 16 may be made of silicon dioxide or silicon nitride.
[0118] S330 : forming a conductive structure 152 on the isolation layer 16 , wherein the conductive structure 152 penetrates the isolation layer 16 and is electrically connected to the heavily doped region 151 .
[0119] Specifically, refer to Fig.16 and Figure 1 As shown, first, the isolation layer 16 is etched to form a conductive groove, so as to expose a portion of the surface of the heavily doped region 151. Then, a conductive material is filled in the conductive groove.
[0120] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.
[0121] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0122] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0123] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A semiconductor device, characterized in that: include: Base layer; A buried layer, disposed on the base layer; A top silicon layer, disposed on the buried layer; The top silicon layer has a plurality of device regions arranged at intervals; A plurality of trench isolation structures arranged at intervals are provided on the top silicon layer; at least two portions of the trench isolation structures are located between two adjacent device regions; Among the at least two trench isolation structures, a lead-out region is provided between two adjacent trench isolation structures, and the lead-out region is provided with an electrical lead-out structure electrically connected to the top silicon layer.
2. The semiconductor device according to claim 1, wherein: At least one trench isolation structure is disposed around the periphery of each device region.
3. The semiconductor device according to claim 2, characterized in that The trench isolation structure includes a first trench isolation structure and a second trench isolation structure. The first trench isolation structure is disposed around the periphery of each device region. The second trench isolation structure is disposed around a layout region. The device region and the first trench isolation structure are both located within the layout region.
4. The semiconductor device according to claim 3, characterized in that The lead-out region between the first trench isolation structure and the second trench isolation structure is adjacent to the lead-out region between two adjacent first trench isolation structures; An electrical lead-out structure is provided on the top silicon layer.
5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The electrical lead structure comprises: A heavily doped region, disposed in the top silicon layer and located in the lead-out region; The conductive structure is disposed on the top silicon layer and is electrically connected to the heavily doped region.
6. The semiconductor device according to any one of claims 1 to 4, characterized in that: The trench isolation structure extends from the surface of the top silicon layer toward the buried layer and penetrates the top silicon layer; The trench isolation structure has a first end adjacent to the buried layer and a second end away from the buried layer; the orthographic projection outer contour of the second end on the buried layer is located outside the orthographic projection outer contour of the first end on the buried layer.
7. The semiconductor device according to claim 6, characterized in that The trench isolation structure includes an isolation trench and a dielectric layer filled in the isolation trench, wherein the isolation trench extends from the surface of the top silicon layer toward the buried layer and penetrates the top silicon layer; The dimension of one end of the isolation trench close to the buried layer along the first direction is smaller than the dimension of one end of the isolation trench away from the buried layer along the first direction; The first direction is perpendicular to a thickness direction of the base layer and a length direction of the isolation trench.
8. The semiconductor device according to claim 7, characterized in that The isolation trench comprises a first sub-trench and a second sub-trench, wherein the second sub-trench is arranged on a side of the first sub-trench away from the buried layer; one end of the first sub-trench is adjacent to the buried layer, and the other end is connected to the second sub-trench; Along the direction away from the base layer, the size of the first sub-groove along the first direction gradually increases.
9. The semiconductor device according to claim 8, characterized in that The dimension of the isolation trench along the thickness direction of the base layer is a first dimension, the dimension of the first sub-trench along the thickness direction of the base layer is a second dimension, and the ratio of the second dimension to the first dimension is between 0.1-0.
2.
10. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate layer having a buried layer and a top silicon layer; The buried layer is disposed on the base layer, and the top silicon layer is disposed on the buried layer; The top silicon layer has a plurality of device regions arranged at intervals; A plurality of trench isolation structures are formed on the top silicon layer and arranged at intervals; at least two of the trench isolation structures have partial structures located between two adjacent device regions; and a lead-out region is provided between two adjacent trench isolation structures in the at least two trench isolation structures; An electrical lead-out structure electrically connected to the top silicon layer is formed on the top silicon layer, and the electrical lead-out structure is located in the lead-out region.
11. The method for preparing a semiconductor device according to claim 10, characterized in that: The step of forming a plurality of trench isolation structures arranged at intervals on the top silicon layer comprises: forming a patterned mask layer on the top silicon layer; Performing a first etching on the top silicon layer based on the patterned mask layer to form a second sub-trench in the top silicon layer; The top silicon layer is etched for a second time based on the patterned mask layer to form a first sub-groove in the top silicon layer; wherein the second sub-groove and the first sub-groove together constitute the isolation groove; along the direction away from the base layer, the size of the first sub-groove along the first direction gradually increases; the first direction is perpendicular to the thickness direction of the base layer and the length direction of the isolation groove; A dielectric layer is filled in the isolation trench to form the trench isolation structure.
12. The method for preparing a semiconductor device according to claim 11, characterized in that: The top silicon layer is etched for the first time and for the second time by using a dry etching process; the etching rate of the second etching is lower than the etching rate of the first etching.
13. The method for preparing a semiconductor device according to claim 12, characterized in that: The process gas of the dry etching process includes etching gas and auxiliary gas; The ratio of the auxiliary gas to the etching gas in the first etching is a first value, and the ratio of the auxiliary gas to the etching gas in the second etching is a second value, and the second value is greater than the first value.
14. The method for preparing a semiconductor device according to claim 13, characterized in that: The etching gas includes at least one of SF6, C4F8 and CF4; And / or, the auxiliary gas includes at least one of O2 and N2.
15. The method for preparing a semiconductor device according to claim 10, characterized in that: The step of forming an electrical lead-out structure electrically connected to the top silicon layer on the top silicon layer, wherein the electrical lead-out structure is located in the lead-out region, comprises: forming a heavily doped region in the top silicon layer, wherein the heavily doped region is located in the lead-out region; forming an isolation layer on the top silicon layer; A conductive structure is formed on the isolation layer, wherein the conductive structure penetrates the isolation layer and is electrically connected to the heavily doped region.