Hybrid power module, multiphase full-bridge hybrid module, power conversion device, and vehicle

Abstract

The application provides a hybrid power module, a multiphase full-bridge hybrid module, a power conversion device and a vehicle, comprising: a substrate; a first direct current connection layer and an alternating current connection layer located on the substrate, the alternating current connection layer comprising a first alternating current connection layer and a second alternating current connection layer which are arranged on both sides of the first direct current connection layer; further comprising an upper bridge chip set arranged on the first direct current connection layer, and a lower bridge chip set, part of the chips of the lower bridge chip set are arranged on the first alternating current connection layer, and the other part of the chips are arranged on the second alternating current connection layer; the chips in the upper bridge chip set are electrically connected to the alternating current connection layer. The scheme of the application can better expand the power level, take into account the switching loss and the cost problem, and also can provide the current sharing performance of the chip.

Description

Technical Field

[0001] This application relates to the field of power conversion technology, and in particular to a hybrid power module, a multiphase full-bridge hybrid module, a power conversion device, and a vehicle. Background Technology

[0002] Hybrid power modules composed of wide-bandgap semiconductor power devices (e.g., silicon carbide metal-oxide-semiconductor field-effect transistors, SiMOSFETs) and silicon-based fully controllable power semiconductor devices (e.g., silicon insulated-gate bipolar transistors, Si IGBTs) are gradually gaining widespread attention.

[0003] When a hybrid power module includes multiple devices connected in parallel, improving the current sharing performance under the condition of multiple devices in parallel is a relatively important issue. Summary of the Invention

[0004] This application provides a hybrid power module, a multiphase full-bridge hybrid module, a power conversion device, and a vehicle to improve the current sharing performance of multiple devices connected in parallel.

[0005] In a first aspect, this application provides a hybrid power module, the hybrid power module comprising:

[0006] substrate;

[0007] A first DC connection layer and an AC connection layer are located on the substrate, wherein the AC connection layer includes a first AC connection layer and a second AC connection layer that are separated and disposed on both sides of the first DC connection layer;

[0008] The upper bridge chipset is disposed on the first DC connection layer;

[0009] A downbridge chipset, wherein a portion of the chips in the downbridge chipset are disposed on a first AC interconnect layer, and another portion of the chips are disposed on a second AC interconnect layer;

[0010] The chips within the upper bridge chipset are electrically connected to the AC connection layer.

[0011] In some embodiments, the first DC connection layer is disposed between the first AC connection layer and the second AC connection layer, and the first AC connection layer and the second AC connection layer are electrically connected by leads or terminals.

[0012] In some embodiments, the lower bridge chipset includes a second wide bandgap chipset, the chips in the upper bridge chipset are electrically connected to the first AC connection layer, and the second wide bandgap chipset is disposed on the first AC connection layer.

[0013] In some embodiments, the downbridge chipset further includes a second silicon-based chipset disposed on the second AC interconnect layer.

[0014] In some embodiments, the upper bridge chipset includes a first wide bandgap chipset, the first wide bandgap chipset and the second wide bandgap chipset are arranged along a first direction, and both the first wide bandgap chipset and the second wide bandgap chipset include a plurality of wide bandgap power chips arranged along a second direction.

[0015] In some embodiments, the second wide bandgap chipset is connected in series with the wide bandgap power chips in the first wide bandgap chipset in a one-to-one correspondence.

[0016] In some embodiments, the upper bridge chipset further includes a first silicon-based chipset, wherein the silicon-based power chips in the first silicon-based chipset are connected in series with the silicon-based power chips in the second silicon-based chipset.

[0017] In some embodiments, the first AC connection layer includes a first AC connection terminal, and the current path length between each wide bandgap power chip in the first wide bandgap chipset and the first AC connection terminal is the same.

[0018] In some embodiments, the hybrid power module further includes a second DC connection layer, to which the second wide bandgap chipset is electrically connected.

[0019] In some embodiments, the hybrid power module includes a second DC connection terminal located on the second DC connection layer; the current path length between each wide bandgap power chip in the second wide bandgap chipset and the second DC connection terminal is the same.

[0020] In some embodiments, the bridge chipset includes:

[0021] The first silicon-based chipset and the first wide-bandgap chipset are arranged along a first direction on the first DC interconnect layer.

[0022] In some embodiments, the downbridge chipset further includes:

[0023] The second silicon-based chipset and the second wide-bandgap chipset are arranged in a first direction.

[0024] In some embodiments, on the second DC connection layer, the second DC connection terminal is disposed close to the second wide bandgap chipset.

[0025] In some embodiments, the first silicon-based chipset includes a plurality of silicon-based power chips and a plurality of diode chips, wherein the silicon-based power chips and the diode chips are connected in parallel in a one-to-one correspondence.

[0026] In some embodiments, the second silicon-based chipset includes a plurality of silicon-based power chips and a plurality of diode chips, wherein the silicon-based power chips and the diode chips are connected in parallel in a one-to-one correspondence.

[0027] In some embodiments, the second DC connection layer includes a first DC negative connection layer and a second DC negative connection layer, wherein the first DC negative connection layer and the second DC negative connection layer are connected.

[0028] In some embodiments, the first AC connection layer, the first DC connection layer, and the second AC connection layer are disposed between the first DC negative connection layer and the second DC negative connection layer.

[0029] In some embodiments, the first AC connection layer is disposed close to the first DC negative connection layer in a first direction, and the second AC connection layer is disposed close to the second DC negative connection layer in the first direction.

[0030] In some embodiments, the first DC negative electrode connection layer and the second DC negative electrode connection layer enclose the first AC connection layer, the first DC connection layer and the second AC connection layer.

[0031] In some embodiments, the second DC negative electrode connection layer is disposed at least partially close to the first DC connection layer.

[0032] In some embodiments, the current direction of the second DC negative electrode connection layer is opposite to the current direction of the first DC connection layer.

[0033] In some embodiments, the second AC connection layer includes a second AC connection terminal, and the chip of the first silicon-based chipset is connected to the second AC connection terminal.

[0034] In some embodiments, on the second AC connection layer, the second AC connection terminal is disposed close to the first silicon-based chipset.

[0035] In some embodiments, the hybrid power module includes two first DC terminals, which are respectively located on the first DC negative terminal connection layer and the second DC negative terminal connection layer.

[0036] In some embodiments, the arrangement of the plurality of wide bandgap power chips includes at least one of the following:

[0037] Each of the wide bandgap power chips is flush in the second direction;

[0038] Two adjacent wide-bandgap power chips are staggered in the first direction;

[0039] Wherein, the first direction and the second direction are two mutually perpendicular directions on a plane.

[0040] In some embodiments, the silicon-based chipset includes:

[0041] The arrangement of multiple silicon-based power chips and multiple diode chips includes at least one of the following:

[0042] A first chip assembly, a second chip assembly, and a third chip assembly are arranged sequentially in a second direction. The first chip assembly includes at least one silicon-based power chip arranged sequentially in the second direction. The second chip assembly includes at least one diode chip arranged sequentially in the second direction. The third chip assembly includes at least one silicon-based power chip arranged sequentially in the second direction.

[0043] The fourth chip assembly, the fifth chip assembly, and the sixth chip assembly are arranged sequentially in the second direction. The fourth chip assembly includes at least one diode chip arranged sequentially in the second direction. The fifth chip assembly includes at least one silicon-based power chip arranged sequentially in the second direction. The sixth chip assembly includes at least one diode chip arranged sequentially in the second direction.

[0044] Multiple silicon-based power chips and multiple diode chips are arranged in a cross pattern in the second direction.

[0045] In some embodiments, the hybrid power module includes:

[0046] A first gate driving layer and a first source driving layer are located on the substrate;

[0047] The gate of each wide bandgap power chip in the first wide bandgap chipset is connected to the first gate driving layer, and the source of each wide bandgap power chip in the first wide bandgap chipset is connected to the first source driving layer.

[0048] In some embodiments, the hybrid power module includes:

[0049] A second gate driving layer and a first emitter driving layer are located on the substrate; the gate of each silicon-based power chip in the first silicon-based chip group is connected to the second gate driving layer, and the emitter of each silicon-based power chip in the first silicon-based chip group is connected to the first emitter driving layer.

[0050] In some embodiments, the hybrid power module includes:

[0051] The third gate driving layer and the second source driving layer located on the substrate

[0052] The gate of each wide bandgap power chip in the second wide bandgap chipset is connected to the third gate driving layer, and the source of each wide bandgap power chip in the second wide bandgap chipset is connected to the second source driving layer.

[0053] In some embodiments, the hybrid power module includes:

[0054] A fourth gate driving layer and a second emitter driving layer are located on the substrate; the gate of each silicon-based power chip in the second silicon-based chip group is connected to the fourth gate driving layer, and the emitter of each silicon-based power chip in the second silicon-based chip group is connected to the second emitter driving layer.

[0055] In some embodiments, the hybrid power module includes:

[0056] A first gate driving terminal and a first source driving terminal are disposed in the first gate driving layer.

[0057] In some embodiments, the hybrid power module includes:

[0058] A second gate driving terminal is disposed in the second gate driving layer and a first emitter driving terminal is disposed in the first emitter driving layer.

[0059] In some embodiments, the hybrid power module includes:

[0060] The third gate driving terminal is disposed in the third gate driving layer and the second source driving terminal is disposed in the second source driving layer.

[0061] In some embodiments, the hybrid power module includes:

[0062] The fourth gate driving terminal is disposed in the fourth gate driving layer and the second emitter driving terminal is disposed in the second emitter driving layer.

[0063] In some embodiments, at least one of the first DC connection layer, the second DC connection layer, and the AC connection layer is a copper layer.

[0064] In some embodiments, the wide bandgap power chip includes a silicon carbide metal-oxide-semiconductor field-effect transistor or a gallium nitride high electron mobility transistor.

[0065] In some embodiments, the silicon-based power chip includes a silicon insulated gate bipolar transistor or a silicon metal-oxide-semiconductor field-effect transistor;

[0066] The diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

[0067] Secondly, this application provides a multiphase full-bridge hybrid module, including at least two of the above-mentioned hybrid power modules.

[0068] Thirdly, this application provides a power conversion device including at least one of the above-described hybrid power modules.

[0069] Fourthly, this application provides a vehicle including the aforementioned power conversion device.

[0070] This application provides a hybrid power module, a multiphase full-bridge hybrid module, a power conversion device, and a vehicle, comprising: a substrate; a first DC connection layer and an AC connection layer located on the substrate, the AC connection layer including a first AC connection layer and a second AC connection layer separately disposed on both sides of the first DC connection layer; further comprising an upper bridge chipset and a lower bridge chipset disposed on the first DC connection layer, a portion of the lower bridge chipset being disposed on the first AC connection layer and another portion of the chipset being disposed on the second AC connection layer; the chips in the upper bridge chipset are electrically connected to the AC connection layer. The solution of this application can effectively expand power levels, balance switching losses and cost issues, and also provide current sharing performance for the chips. Attached Figure Description

[0071] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0072] Figure 1 A schematic diagram of the layout of a hybrid power module provided in an embodiment of this application;

[0073] Figure 2 A schematic diagram of the layout of a hybrid power module provided in another embodiment of this application;

[0074] Figure 3 A layout schematic diagram of a hybrid power module provided in yet another embodiment of this application;

[0075] Figure 4 A schematic diagram of the current path of a first chip provided in an embodiment of this application;

[0076] Figure 5 This is a schematic diagram of the structure of a chip provided in one embodiment of this application;

[0077] Figure 6 A schematic diagram of an AC terminal provided in an embodiment of this application;

[0078] Figure 7A schematic diagram of the equivalent circuit and switching waveforms of a hybrid power module provided in an embodiment of this application;

[0079] Figure 8 This is a schematic diagram of the layout of a first chipset provided in an embodiment of this application;

[0080] Figure 9 A layout schematic diagram of a hybrid power module provided in another embodiment of this application;

[0081] Figure 10 This is a schematic diagram of the layout of a second chipset provided in an embodiment of this application;

[0082] Figure 11 This is a schematic diagram of a multiphase hybrid power module provided in an embodiment of this application. Detailed Implementation

[0083] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0084] In various fields such as automobiles and power systems, reducing power losses in power conversion devices such as inverters and frequency converters is crucial, and power semiconductor devices in these devices play a vital role. However, the performance of traditional silicon-based power semiconductor devices is insufficient to meet current demands for power switching devices in terms of blocking voltage, on-state current, operating frequency, high temperature, and high efficiency.

[0085] Silicon-based fully controllable power semiconductor devices, represented by silicon-insulated-gate bipolar transistors (SiIGBTs), possess excellent performance characteristics such as simple control circuits, high voltage resistance, and high current handling capacity, and are widely used in power conversion devices such as inverters and frequency converters. However, when silicon-based fully controllable power semiconductor devices, represented by SiIGBTs, turn off, the collector current decays slowly, i.e., a significant tail current. This tail current is amplified by switching losses, especially when used as a high-frequency switch.

[0086] Wide bandgap semiconductor materials, such as silicon carbide, possess excellent physical properties including a large bandgap, high saturated electron drift rate, and high thermal conductivity. These properties can significantly reduce losses in power conversion devices such as inverters and frequency converters, thereby improving conversion efficiency. However, wide bandgap semiconductor power devices, represented by silicon carbide, are relatively expensive.

[0087] Therefore, wide-bandgap semiconductor power devices and silicon-based fully controllable power semiconductor devices can be connected in parallel to form a hybrid power module. The wide-bandgap semiconductor power devices control the switching of the hybrid power module, while the silicon-based fully controllable power semiconductor devices bear the main conduction current, thereby combining the advantages of the two types of devices to reduce switching losses and costs.

[0088] When a hybrid power module includes multiple devices connected in parallel, current sharing problems are likely to occur. Therefore, improving the current sharing performance of multiple devices connected in parallel is a crucial issue.

[0089] To address this, this application proposes a hybrid power module, wherein the AC connection layer includes a first AC connection layer and a second AC connection layer. A portion of the chips in the lower bridge chipset are disposed on the first AC connection layer, and another portion of the chips are disposed on the second AC connection layer. This approach can effectively expand the power level, balance switching losses and cost issues, and also provide current sharing performance for the chips, thereby improving the electrical performance and reliability of the half-bridge power module. Furthermore, since the hybrid power module is formed on a single substrate, it can reduce manufacturing processes and improve space utilization.

[0090] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0091] Figures 1-3 A schematic diagram of a hybrid power module according to an embodiment of this application is shown. (Combined with...) Figures 1-3 As shown, the hybrid power module in this embodiment may include:

[0092] Substrate 20; a first DC connection layer 21 and an AC connection layer 22 located on the substrate 20, wherein the AC connection layer 22 includes a first AC connection layer 221 and a second AC connection layer 222 disposed on both sides of the first DC connection layer 21.

[0093] The upper bridge chipset 31 is disposed on the first DC connection layer 21;

[0094] The lower bridge chipset 32 ​​has a portion of its chips disposed on the first AC connection layer 221 and another portion of its chips disposed on the second AC connection layer 222.

[0095] The chip in the upper bridge chipset 31 is electrically connected to the AC connection layer 22.

[0096] In this embodiment, substrate 20 is used to support the interconnect layer and the chipset. By forming the interconnect layer and chipset on a single substrate, the problem of excessive manufacturing processes caused by the need for interconnection between multiple substrates is solved, reducing the number of manufacturing processes. Furthermore, forming the chipset and interconnect layer on a single substrate allows for improved space utilization through the rational placement of the chipset and interconnect layer on the substrate. It also includes an upper-bridge chipset and a lower-bridge chipset, which can address switching losses and cost issues. In addition, the lower-bridge chipset includes multiple chips, enabling better expansion of power levels.

[0097] For example, substrate 20 may include a ceramic substrate, such as an alumina substrate, a silicon nitride substrate, a zirconia substrate, etc.

[0098] It should be noted that the upper bridge chipset 31, the lower bridge chipset 32, and the connection layer in the hybrid power module constitute a half-bridge structure. The half-bridge structure is connected to the power supply and the load, and can convert DC power into AC power for the load.

[0099] In some embodiments, a first DC connection layer 21 is disposed between a first AC connection layer 221 and a second AC connection layer 222. The first AC connection layer 221 and the second AC connection layer 222 are electrically connected by leads or terminals to facilitate the connection between the chipset and the AC connection layer, thereby shortening the length of the connection lines, etc.

[0100] In some embodiments, the lower bridge chipset 32 ​​includes a second wide bandgap chipset 312, which can bear the switching losses, thereby achieving the purpose of reducing switching losses.

[0101] In some examples, the downbridge chipset 32 ​​also includes a second silicon-based chipset 322 disposed on the second AC interconnect layer 222. The downbridge chipset 32 ​​is controlled to be turned on or off by the second silicon-based chipset 322 and the second wide bandgap chipset 312.

[0102] Power device losses are categorized into switching losses and conduction losses. Switching losses are the losses incurred during the instant the power device switches on, while conduction losses are the losses that occur over a prolonged period after the device completes the switching process. Switching losses further include turn-on losses and turn-off losses. Turn-on losses are the losses incurred during the instant the power device turns on, and turn-off losses are the losses incurred during the instant the power device turns off. Wide-bandgap chipsets handle the switching action and bear the switching losses, while silicon-based chipsets handle the conduction current. Because wide-bandgap power chips have lower switching losses and silicon-based power chips have lower costs, the goal of reducing switching losses and costs can be achieved.

[0103] In other examples, the upper bridge chipset 31 includes a first wide bandgap chipset 311, which can absorb switching losses, thereby reducing switching losses. Furthermore, the first wide bandgap chipset 311 and the second wide bandgap chipset 312 are arranged along a first direction to improve space utilization. In addition, both the first wide bandgap chipset 311 and the second wide bandgap chipset 312 include multiple wide bandgap power chips arranged along a second direction, enabling the upper bridge chipset 31 and the lower bridge chipset 32 ​​to handle greater power and output greater current. For example, the first and second directions are two perpendicular directions on a plane.

[0104] As one implementation, the wide bandgap power chips 11 in the second wide bandgap chipset 312 and the first wide bandgap chipset 311 are connected in series one-to-one. The two corresponding wide bandgap power chips 11 can form a half-bridge circuit. Furthermore, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current specification amplified by N times (the number of half-bridge circuits is N) can be formed, which is beneficial to improving the power level of the half-bridge power module.

[0105] In some other examples, the upper bridge chipset 31 also includes a first silicon-based chipset 321, which, along with the first wide bandgap chipset 311, controls the upper bridge chipset 31 to be turned on or off. The first silicon-based chipset 321 can handle the conduction current and is low-cost, thus reducing costs. The first wide bandgap chipset 311 handles switching losses, thereby reducing switching losses and costs.

[0106] Furthermore, the chips in the first silicon-based chipset 321 are connected in series with the chips in the second silicon-based chipset 322 to form a half-bridge structure.

[0107] In some embodiments, the first AC connection layer 221 includes a first AC connection terminal 431, and the current path length between each wide-bandgap power chip 11 in the first wide-bandgap chipset 311 and the first AC connection terminal 431 is the same. The first AC connection terminal 431 is a region, and its length, size, etc., affect the current path length. Therefore, the fact that the current path length between each wide-bandgap power chip 11 in the first wide-bandgap chipset 311 and the first AC connection terminal 431 is the same can mean that the shortest current path length from the source of each wide-bandgap power chip 11 in the first wide-bandgap chipset 311 to the first AC connection terminal 431 is the same. Furthermore, this "sameness" can be completely identical, or a slight difference in the current path length is allowed. For example, the difference between the current path lengths of any two wide-bandgap power chips 11 in the first wide-bandgap chipset 311 and the first AC connection terminal 431 is within a preset difference range, which can be determined according to actual conditions.

[0108] In some embodiments, the hybrid power module further includes a second DC connection layer 23, to which the second wide bandgap chipset 312 is electrically connected so that the lower bridge chipset 32 ​​can be brought out.

[0109] It should be noted that the upper bridge chipset 31, the lower bridge chipset 32, and the connection layer in the hybrid power module constitute a half-bridge structure. The half-bridge structure is connected to the power supply and the load, and can convert DC power into AC power for the load.

[0110] Specifically, the upper bridge chipset 31 is located on the first DC connection layer 21, and the first DC connection layer 21 can be used to connect to the positive terminal of the power supply, thereby allowing the upper bridge chipset 31 to be connected to the positive terminal of the power supply; the lower bridge chipset 32 ​​is connected to the second DC connection layer 23, and the second DC connection layer 23 can be used to connect to the negative terminal of the power supply, for example, by connecting to the negative terminal of the power supply through the second DC terminal 42, thereby allowing the lower bridge chipset 32 ​​to be connected to the negative terminal of the power supply; the upper bridge chipset 31 is connected to the AC connection layer 22, and the lower bridge chipset 32 ​​is located on the AC connection layer 22, and the AC connection layer 22 is used to connect to the load, for example, by connecting to the load through the AC terminal 43, thereby allowing the upper bridge chipset 31 and the lower bridge chipset 32 ​​to be connected to the load. For example, the lower bridge chipset 32 ​​can be connected to the second DC connection layer 23 via a bonding wire, and the upper bridge chipset 31 can be connected to the AC connection layer 22 via a bonding wire, or via other connecting wires.

[0111] In practical applications, at least one of the first DC connection layer 21, the second DC connection layer 23, the first AC connection layer 221, and the second AC connection layer 222 is a copper layer. For example, the first DC connection layer 21 can be a positive DC copper layer, and the second DC connection layer 23 can be a negative DC copper layer.

[0112] In one implementation, multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 311 are connected in parallel. Specifically, all the wide-bandgap power chips 11 in the first wide-bandgap chipset 311 are located on the first DC connection layer 21, and the multiple wide-bandgap power chips 11 are connected to the AC connection layer 22, thereby realizing the parallel connection of the multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 311. For example, each wide-bandgap power chip 11 in the first wide-bandgap chipset 311 can be connected to the AC connection layer 22 via bonding wires.

[0113] Multiple wide-bandgap power chips 11 in the second wide-bandgap chipset 312 are connected in parallel. Specifically, all wide-bandgap power chips 11 in the second wide-bandgap chipset 312 are located on the AC connection layer 22, and are connected to the second DC connection layer 23, thereby realizing the parallel connection of the multiple wide-bandgap power chips 11 in the second wide-bandgap chipset 312. For example, each wide-bandgap power chip 11 in the second wide-bandgap chipset 312 can be connected to the second DC connection layer 23 via bonding wires.

[0114] Furthermore, the second wide bandgap chipset 312 corresponds one-to-one with and is connected to the wide bandgap power chips 11 in the first wide bandgap chipset 211. The two corresponding wide bandgap power chips 11 can form a half-bridge circuit. Moreover, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current specification amplification of N times (the number of half-bridge circuits is N) can be formed, which is beneficial to improving the power level of the half-bridge power module.

[0115] In some embodiments, the hybrid power module includes a second DC connection terminal 42 located on the second DC connection layer 23, and the current path length between each wide bandgap power chip 11 in the second wide bandgap chipset 312 and the second DC connection terminal 42 is the same, thereby improving the current sharing performance of the lower bridge.

[0116] The second DC connection terminal 42 is a region that connects to each wide-bandgap power chip 11 in the second wide-bandgap chipset 312. The length and dimensions of the second DC connection terminal 42 affect the current path length. Therefore, the current path length between each wide-bandgap power chip 11 in the second wide-bandgap chipset 312 and the second DC connection terminal 42 is the same. This means the shortest current path length from the source of each wide-bandgap power chip 11 in the second wide-bandgap chipset 311 to the second DC connection terminal 42 is the same. This "same" can be completely identical, or a slight difference in the current path length is allowed. For example, the difference between the current path lengths of any two wide-bandgap power chips 11 in the second wide-bandgap chipset 312 and the second DC connection terminal 42 can be within a preset difference range, which can be determined based on actual conditions.

[0117] In practical applications, the wide bandgap power chip 11 may include a silicon carbide metal oxide semiconductor field effect transistor (SiCMOSFET) or a gallium nitride high electron mobility transistor (GaN HEMT).

[0118] Figure 5 Figure (A) shows a schematic diagram of a wide bandgap power chip. The surface electrodes of the wide bandgap power chip 11 include a source 111, a gate 12, and a drain 113 located at the bottom. Correspondingly, the drain 113 of the wide bandgap power chip 11 in the second wide bandgap chip group 312 is attached to the AC connection layer 22, and the source 111 of the wide bandgap power chip 11 in the second wide bandgap chip group 312 is connected to the second DC connection layer 23. The drain of the wide bandgap power chip 11 in the first wide bandgap chip group 311 is attached to and connected to the first DC connection layer 21, and the source of the wide bandgap power chip 11 in the first wide bandgap chip group 311 is connected to the AC connection layer 22.

[0119] It should be noted that when multiple wide-bandgap power chips 11 are arranged in one direction, and the direction of the current after the multiple wide-bandgap power chips 11 are combined is perpendicular to the arrangement direction of the multiple wide-bandgap power chips 11, such as Figure 4 As shown in (A), each first chip has a current path of the same length, i.e., the same current path length, thus achieving good dynamic current sharing performance. When multiple wide-bandgap power chips 11 are arranged in one direction, and the current direction after the multiple wide-bandgap power chips 11 converge is parallel to the arrangement direction of the multiple wide-bandgap power chips 11, as shown in (A), each first chip has a current path of the same length, i.e., the current path is parallel to the arrangement direction of the multiple wide-bandgap power chips 11. Figure 4 As shown in (B), each wide bandgap power chip 11 has a current path of different lengths, which can cause dynamic uneven current.

[0120] It is understandable that, since the multiple wide bandgap power chips 11 in the first wide bandgap chipset 311 are arranged along the second direction, the current path length between the multiple wide bandgap power chips 11 in the first wide bandgap chipset 311 and the first AC connection terminal 43 is as similar as possible, thereby improving the current sharing performance of the upper bridge.

[0121] The multiple wide bandgap power chips 11 in the second wide bandgap chipset 312 are arranged along the second direction, so that the current path length between the multiple wide bandgap power chips 11 in the second wide bandgap chipset 312 and the second DC connection terminal 42 is as similar as possible, thereby improving the current sharing performance of the lower bridge.

[0122] In some embodiments, combined with Figure 2 and Figure 3 As shown, the upper bridge chipset 31 includes a first silicon-based chipset 321 and a first wide bandgap chipset 311. On the first DC connection layer 21, the first silicon-based chipset 321 and the first wide bandgap chipset 311 are arranged along a first direction. The upper bridge chipset 31 is controlled to be turned on or off by the first silicon-based chipset 321 and the first wide bandgap chipset 311, thereby achieving the purpose of reducing switching losses and costs.

[0123] In other embodiments, the downbridge chip group 32 includes a second silicon-based chip group 322 and a second wide bandgap chip group 312, which are arranged in a first direction. The second silicon-based chip group 322 and the second wide bandgap chip group 312 are used to control the downbridge chip group 32 to be turned on or off.

[0124] In some examples, the first silicon-based chipset 321 includes multiple silicon-based power chips 12, thereby enabling the upper-bridge chipset 31 to output a larger current. Specifically, the multiple silicon-based power chips 12 in the first silicon-based chipset 321 are connected in parallel. All of the multiple silicon-based power chips 12 in the first silicon-based chipset 321 are located on the first DC connection layer 21, and the multiple silicon-based power chips 12 are connected to the AC connection layer 22, thus realizing the parallel connection of the multiple silicon-based power chips 12 in the first silicon-based chipset 321. For example, the multiple silicon-based power chips 12 in the first silicon-based chipset 321 can be connected to the AC connection layer 22 via bonding wires.

[0125] In addition, the first silicon-based chipset 321 may also include multiple diode chips 13, with the silicon-based power chip 12 and the diode chip 13 connected in parallel in a one-to-one correspondence. Specifically, each diode 13 is connected in parallel with one silicon-based power chip 12 in the first silicon-based chipset 321 to undertake reverse current freewheeling and improve the overall reverse current freewheeling capability of the module.

[0126] In other examples, the second silicon-based chipset 322 includes multiple silicon-based power chips 12, thereby enabling the lower-bridge chipset 32 ​​to output a larger current. Specifically, the multiple silicon-based power chips 12 in the second silicon-based chipset 322 are connected in parallel. All of the multiple silicon-based power chips 12 in the second silicon-based chipset 322 are located on the AC connection layer 22, and the multiple silicon-based power chips 12 are connected to the second DC connection layer 23, thus realizing the parallel connection of the multiple silicon-based power chips 12 in the second silicon-based chipset 322. For example, the multiple silicon-based power chips 12 in the second silicon-based chipset 322 can be connected to the second DC connection layer 23 via bonding wires.

[0127] Furthermore, the second silicon-based chipset 322 may also include multiple diode chips 13, with the silicon-based power chip 12 and diode chips 13 connected in parallel in a one-to-one correspondence. Specifically, each diode chip 13 is connected in parallel with one silicon-based power chip 12 in the second silicon-based chipset 304 to undertake reverse current freewheeling, thereby improving the overall reverse current freewheeling capability of the module.

[0128] In practical applications, the silicon-based power chip 12 may include a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field effect transistor (Si MOSFET).

[0129] The diode chip 13 may include a silicon fast recovery diode (SiRFD) chip or a silicon carbide Schottky barrier diode (SiCSBD) chip.

[0130] Figure 5 Figure (B) shows a schematic diagram of a silicon-based power chip 12. The surface electrodes of the silicon-based power chip 12 include an emitter 121, a gate 122, and a collector 123 located at the bottom. Correspondingly, the collector of the silicon-based power chip 12 in the second silicon-based chip group 322 is bonded to the AC connection layer 22, and the emitter of the silicon-based power chip 12 in the second silicon-based chip group 322 is connected to the second DC connection layer 23 via bonding wires. The collector of the silicon-based power chip 12 in the first silicon-based chip group 321 is bonded to the first DC connection layer 22, and the emitter of the silicon-based power chip 12 in the first silicon-based chip group 321 is connected to the AC connection layer 22 via bonding wires.

[0131] Figure 5 Figure (C) shows a schematic diagram of a third chip, in which diode chip 13 includes an anode 131 at the top and a cathode 132 at the bottom. Correspondingly, the cathode of diode chip 13 in the second silicon-based chipset 322 is bonded to AC connection layer 22, and the anode of diode chip 13 in the second silicon-based chipset 322 is bonded to a second DC connection layer 23 via bonding wires. The cathode of diode chip 13 in the first silicon-based chipset 321 is bonded to a first DC connection layer 22, and the diode chip 13 in the first silicon-based chipset 321 is bonded to AC connection layer 22 via bonding wires.

[0132] In some embodiments, combined with Figure 2 and Figure 3 As shown, the second DC connection layer 23 includes a first DC negative connection layer 231 and a second DC negative connection layer 232. The first DC negative connection layer 231 and the second DC negative connection layer 232 are connected to facilitate the setting and shortening of the traces from the chip to the connection layer.

[0133] In some examples, the first AC connection layer 221, the first DC connection layer 21, and the second AC connection layer 222 are disposed between the first DC negative connection layer 231 and the second DC negative connection layer 232 to shorten the connection lines between each chip and the corresponding connection layer.

[0134] In one implementation, the first AC connection layer 221 is disposed close to the first DC negative connection layer 231 in the first direction to shorten the connection line from the wide bandgap power chip 11 in the second wide bandgap chipset 312 to the AC connection layer, and the second AC connection layer 222 is disposed close to the second DC negative connection layer 232 in the first direction to shorten the connection line from the silicon-based power chip 12 and the diode chip 13 in the second silicon-based chipset 322 to the AC connection layer.

[0135] As another implementation, the first DC negative electrode connection layer 231 and the second DC negative electrode connection layer 232 enclose the first AC connection layer 221, the first DC connection layer 21 and the second AC connection layer, which facilitates the setting and shortening of the traces from the first wide bandgap chipset 311 to the first AC connection layer 221, the first silicon-based chipset 321 to the second AC connection layer 222, the second wide bandgap chipset 312 to the first DC negative electrode connection layer 231, and the second silicon-based chipset 322 to the second DC negative electrode connection layer 232.

[0136] For example, the first DC connection layer 21 and the second DC negative connection layer 232 adopt a double "C" shape design, with the "C" shape of the second DC negative connection layer 232 located outside the "C" shape of the first DC connection layer 21. For instance, the first DC negative connection layer 231 and the second DC negative connection layer 232 are connected by bonding wires.

[0137] As another implementation, the second DC negative electrode connection layer 232 is disposed at least partially close to the first DC connection layer 21 to shorten the trace from the chip to the second DC negative electrode connection layer 232.

[0138] For example, the current direction of the second DC negative terminal connection layer 232 is opposite to the current direction of the first DC connection layer 21, which can be compensated by mutual inductance to reduce parasitic inductance. For instance, the current direction along the first direction in the second DC negative terminal connection layer 232 is opposite to the current direction along the first direction in the first DC connection layer 21.

[0139] In some examples, in order to bring out the first AC connection layer 221 and the second AC connection layer 222, the second AC connection layer 222 includes a second AC connection terminal 432, and the chip of the first silicon-based chipset 321 is connected to the second AC connection terminal 432, so that the first AC connection layer 221 and the second AC connection layer 222 can be brought out through the first AC connection terminal 431 and the second AC connection terminal 432 respectively.

[0140] To better understand the impact of DC terminal location on the commutation circuit of wide-bandgap power chips, the following explanation uses the equivalent circuit of a hybrid power module considering parasitic inductance as an example. Figure 7 As shown, the wide bandgap power chip 11 is turned on first, at which point the voltage drops and the wide bandgap power chip 11 carries the entire current. Then the silicon-based power chip 12 is turned on, and the wide bandgap power chip 11 and the silicon-based power chip 12 commutate. Finally, the wide bandgap power chip 11 and the silicon-based power chip 12 each carry a portion of the current. During the turn-off process, the wide bandgap power chip 11 is turned off first. At this time, the silicon-based power chip 12 and the wide bandgap power chip 11 commutate. After the wide bandgap power chip 11 carries the entire current, it turns off, at which point the voltage rises and a turn-off voltage spike appears.

[0141] Because the wide-bandgap power chip 11 has a faster switching speed than the silicon-based power chip 12, the voltage spike generated by the wide-bandgap power chip 11 under the same inductance is much higher than that generated by the silicon-based power chip 12. Therefore, the turn-off spike caused by parasitic inductance in the switching commutation circuit of the wide-bandgap power chip 11 is more severe. Reducing the commutation circuit length of the wide-bandgap power chip 11 is the main problem.

[0142] Therefore, in some examples, on the second DC connection layer 23, the second DC connection terminal 42 is located close to the second wide bandgap chipset 312, for example, on the side of the second wide bandgap chipset 312 away from the second silicon-based chipset 322, so as to reduce the commutation loop length of the second wide bandgap chipset 312, reduce the parasitic inductance in the commutation loop, and thereby reduce the voltage turn-off spike generated by the wide bandgap power chip 11.

[0143] In other examples, the hybrid power module includes two first DC terminals 41 located on the first DC connection layer 21. These two first DC terminals 41 are respectively located on the first DC negative connection layer 231 and the second DC negative connection layer 232. The two first DC terminals 41 are positioned on either side of the second DC terminal 42 in a second direction. This improves the current sharing performance of the multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 311, reduces the commutation loop length of the wide-bandgap power chips 11 during switching, reduces the parasitic inductance between the wide-bandgap power chips 11 and the first DC terminals 41, and reduces voltage turn-off spikes. The first DC terminals 41 are used to connect to external circuits, such as the positive terminal of a power supply, and the connection between the external circuits and the upper bridge chipset 31 can be achieved through the first DC terminals 41 and the first DC connection layer 21.

[0144] In some other examples, on the second AC connection layer 222, the second AC connection terminal 43 is positioned close to the first silicon-based chipset 321 to reduce the commutation loop length of the second silicon-based chipset 322.

[0145] In some embodiments, such as Figure 8 As shown, the arrangement of the plurality of wide bandgap power chips 11 in the first wide bandgap chipset 311 and the plurality of wide bandgap power chips 11 in the second wide bandgap chipset 312 can each include at least one of the following:

[0146] Each wide-bandgap power chip 11 is flush in the second direction;

[0147] Each wide bandgap power chip 11 is arranged sequentially in the second direction, and two adjacent wide bandgap power chips 11 are staggered in the first direction;

[0148] The first direction and the second direction are two mutually perpendicular directions on a plane.

[0149] like Figure 8 As shown in (A), each wide bandgap power chip 11 is arranged sequentially and neatly along the second direction, with bonding wires connected to the corresponding interconnect layer along the first direction. For example, when multiple wide bandgap power chips 11 in the first wide bandgap chip group 311 are arranged sequentially and neatly along the second direction, the bonding wires of each wide bandgap power chip 11 are connected to the AC interconnect layer 22 along the first direction; similarly, when multiple wide bandgap power chips 11 in the second wide bandgap chip group 312 are arranged sequentially and neatly along the second direction, the bonding wires of each wide bandgap power chip 11 are connected to the AC interconnect layer 22 along the first direction. This arrangement is more compact and helps to improve space utilization.

[0150] like Figure 8As shown in (B), each wide bandgap power chip 11 is arranged sequentially in the second direction, and adjacent wide bandgap power chips 11 are staggered in the first direction, with bonding wires connected to the corresponding interconnect layers along the first direction. This arrangement is optimized for heat dissipation, which can further reduce thermal coupling and improve heat dissipation performance.

[0151] In practical applications, different wide-bandgap power chip arrangement methods can be flexibly selected according to requirements to meet different performance needs.

[0152] For example, such as Figure 9 As shown, when multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 311 are arranged in the second direction, adjacent wide-bandgap power chips 11 in the first wide-bandgap chipset 311 can be staggered in the first direction to reduce thermal coupling of the first wide-bandgap chipset 311 and to have better heat dissipation performance. When multiple wide-bandgap power chips 11 in the second wide-bandgap chipset 312 are arranged in the second direction, adjacent wide-bandgap power chips 11 in the second wide-bandgap chipset 312 can be staggered in the first direction to give the second wide-bandgap chipset 312 better heat dissipation performance.

[0153] In some embodiments, such as Figure 10 As shown, the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the first silicon-based chipset 321, and the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the second silicon-based chipset 322, can each include at least one of the following:

[0154] The first chip assembly, the second chip assembly, and the third chip assembly are arranged sequentially in the second direction. The first chip assembly includes at least one silicon-based power chip 12 arranged sequentially in the second direction. The second chip assembly includes at least one diode chip 13 arranged sequentially in the second direction. The third chip assembly includes at least one silicon-based power chip 12 arranged sequentially in the second direction.

[0155] The fourth chip assembly, the fifth chip assembly, and the sixth chip assembly are arranged sequentially in the second direction. The fourth chip assembly includes at least one diode chip 13 arranged sequentially in the second direction. The fifth chip assembly includes at least one silicon-based power chip 12 arranged sequentially in the second direction. The sixth chip assembly includes at least one diode chip 13 arranged sequentially in the second direction.

[0156] Multiple silicon-based power chips 12 and multiple diode chips 13 are arranged in a cross pattern in the second direction;

[0157] The first direction and the second direction are two mutually perpendicular directions on a plane.

[0158] Due to the thermal coupling effect, the intermediate chip has a higher junction temperature in steady state under the same power loss conditions. The power loss of silicon-based power chip 12 and diode chip 13 depends on the driving control method of silicon-based power chip 12 and diode chip 13. Therefore, the loss of silicon-based power chip 12 and diode chip 13 can be evaluated during the design.

[0159] When the loss of the silicon-based power chip 12 is higher than that of the diode chip 13, the silicon-based power chip 12 can be disposed on both sides of the diode chip 13 in the second direction to reduce the temperature rise of the silicon-based power chip 12, such as... Figure 10 As shown in (A), the first chip assembly, the second chip assembly, and the third chip assembly are arranged sequentially in the second direction, and the first chip assembly and the third chip assembly include silicon-based power chips 12, and the second chip assembly includes diode chips 13.

[0160] When the loss of the silicon-based power chip 12 is lower than that of the diode chip 13, the diode chip 13 can be disposed on both sides of the silicon-based power chip 12 in the second direction to reduce the temperature rise of the diode chip 13, such as... Figure 10 As shown in (B), the fourth chip assembly, the fifth chip assembly, and the sixth chip assembly are arranged sequentially in the second direction, and the fourth chip assembly and the sixth chip assembly include diode chip 13, and the fifth chip assembly includes silicon-based power chip 12.

[0161] When the losses of the silicon-based power chip 12 and the diode chip 13 are close, the silicon-based power chip 12 and the diode chip 13 can be arranged in a cross pattern in the second direction, such as... Figure 10 As shown in (C) in the diagram.

[0162] In practical applications, different arrangements of silicon-based power chips 12 and diode chips 13 can be flexibly selected according to requirements.

[0163] In some embodiments, combined with Figure 2 and Figure 3 As shown, the hybrid power module includes a first gate driving layer 241 and a first source driving layer 242 located on the substrate 20. For example, the first gate driving layer 241 and the first source driving layer 242 can be copper layers.

[0164] The gate of the wide bandgap power chip 11 in the first wide bandgap chipset 311 is connected to the first gate driving layer 241 via a bonding wire, and the source of the wide bandgap power chip 11 in the first wide bandgap chipset 311 is connected to the first source driving layer 242 via a bonding wire, so that the voltage difference between the gate and the source of the wide bandgap power chip 11 in the first wide bandgap chipset 311 can be controlled, thereby controlling the wide bandgap power chip 11 in the first wide bandgap chipset 311 to be in the on or off state.

[0165] In other embodiments, the hybrid power module further includes a second gate driving layer 261 and a first emitter driving layer 262 located on the substrate 20. For example, the second gate driving layer 262 and the first emitter driving layer 262 may be copper layers.

[0166] The gate of the silicon-based power chip 12 in the first silicon-based chipset 321 is connected to the second gate driving layer 261 via a bonding wire, and the emitter of the silicon-based power chip 12 in the first silicon-based chipset 321 is connected to the first emitter driving layer 262 via a bonding wire, so that the voltage difference between the gate and emitter of the silicon-based power chip 12 in the first silicon-based chipset 321 can be controlled, thereby controlling the silicon-based power chip 12 in the first silicon-based chipset 321 to be in the on or off state.

[0167] For example, when multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 311 are arranged in the second direction, and multiple silicon-based power chips 12 and multiple diode chips 13 in the first silicon-based chipset 321 are arranged in the second direction, the first gate driving layer 241 and the first source driving layer 242 can be disposed between the first wide-bandgap chipset 311 and the first silicon-based chipset 321, and the second gate driving layer 261 and the first emitter driving layer 262 can be disposed between the first silicon-based chipset 321 and the second AC connection layer 222, thereby shortening the bonding line between the first wide-bandgap chipset 311 and the driving layer, and shortening the bonding line between the first silicon-based chipset 321 and the driving layer.

[0168] As one implementation, the first source driving layer 242 and the first emitter driving layer 262 can be the same driving layer, which shortens the commutation loop between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reduces the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reduces the commutation time.

[0169] In some examples, combined Figure 2 and Figure 3 As shown, a first gate driving terminal 441 is formed in the first gate driving layer 241, and a first source driving terminal 442 is formed in the first source driving layer 242. External circuitry is connected via the first gate driving terminal 441 and the first source driving terminal 442, enabling the gate and source of the wide-bandgap power chip 11 in the first wide-bandgap chipset 311 to receive external voltage, thereby controlling the wide-bandgap power chip 11 in the first wide-bandgap chipset 311 to be in an on or off state.

[0170] In other examples, a second gate driving terminal 461 is formed in the second gate driving layer 261, and a first emitter driving terminal 462 is formed in the first emitter driving layer 262. External circuitry is connected via the second gate driving terminal 461 and the first emitter driving terminal 462, enabling the gate and emitter of the silicon-based power chip 12 in the first silicon-based chipset 321 to receive external voltage, thereby controlling the silicon-based power chip 12 in the first silicon-based chipset 321 to be in an on or off state.

[0171] For example, when the first source driving layer 242 and the first emitter driving layer 262 are the same driving layer, the first source driving terminal 442 and the first emitter driving terminal 462 are the same driving terminal.

[0172] In other embodiments, combined with Figure 2 and Figure 3 As shown, the hybrid power module includes a third gate driving layer 251 and a second source driving layer 252 located on the substrate 20. For example, the third gate driving layer 251 and the second source driving layer 252.

[0173] The gate of the wide bandgap power chip 11 in the second wide bandgap chipset 312 is connected to the third gate driving layer 251 via a bonding wire, and the source of the wide bandgap power chip 11 in the second wide bandgap chipset 312 is connected to the second source driving layer 252 via a bonding wire, so that the voltage difference between the gate and the source of the wide bandgap power chip 11 in the second wide bandgap chipset 312 can be controlled, thereby controlling the wide bandgap power chip 11 in the second wide bandgap chipset 312 to be in the on or off state.

[0174] In some other embodiments, the hybrid power module further includes a fourth gate driving layer 271 and a second emitter driving layer 272 located on the substrate 20. For example, the fourth gate driving layer 271 and the second emitter driving layer 272 may be copper layers.

[0175] The gate of the silicon-based power chip 12 in the second silicon-based chipset 322 is connected to the fourth gate driving layer 271 via a bonding wire, and the emitter of the silicon-based power chip 12 in the second silicon-based chipset 322 is connected to the second emitter driving layer 272 via a bonding wire, so that the voltage difference between the gate and emitter of the silicon-based power chip 12 in the second silicon-based chipset 322 can be controlled, thereby controlling the silicon-based power chip 12 in the second silicon-based chipset 322 to be in the on or off state.

[0176] For example, when multiple wide-bandgap power chips 11 in the second wide-bandgap chipset 312 are arranged in the second direction, and multiple silicon-based power chips 12 and multiple diode chips 13 in the second silicon-based chipset 311 are arranged in the second direction, the third gate driving layer 251 and the second source driving layer 252 can be disposed between the second wide-bandgap chipset 312 and the first DC negative electrode connection layer 231, and the fourth gate driving layer 271 and the fourth source driving layer 272 can be disposed between the first DC connection layer 21 and the second silicon-based chipset 322, thereby shortening the bonding line between the second wide-bandgap chipset 312 and the driving layer, and shortening the bonding line between the second silicon-based chipset 322 and the driving layer.

[0177] As one implementation, the second source driving layer 252 and the second emitter driving layer 272 can be the same driving layer, which further shortens the commutation loop between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reduces the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reduces the commutation time.

[0178] In some examples, a third gate drive terminal 451 is formed in the third gate drive layer 251, and a second source drive terminal 452 is formed in the second source drive layer 252. External circuitry is connected via the third gate drive terminal 451 and the second source drive terminal 452, enabling the gate and source of the wide bandgap power chip 11 in the second wide bandgap chipset 312 to receive external voltage, thereby controlling the wide bandgap power chip 11 in the second wide bandgap chipset 312 to be in an on or off state.

[0179] In other examples, a fourth gate driving terminal 471 is formed in the fourth gate driving layer 271, and a second emitter driving terminal 472 is formed in the second emitter driving layer 272. External circuitry is connected via the fourth gate driving terminal 271 and the second emitter driving terminal 272, enabling the gate and emitter of the silicon-based power chip 12 in the second silicon-based chipset 322 to receive external voltage, thereby controlling the silicon-based power chip 12 in the second silicon-based chipset 322 to be in an on or off state.

[0180] For example, when the second source driving layer 252 and the second emitter driving layer 272 are the same driving layer, the second source driving terminal 452 and the second emitter driving terminal 452 are the same driving terminal.

[0181] The above describes the hybrid power module provided in this application. This application also provides a multiphase full-bridge hybrid module, including at least two of the above-described hybrid power modules connected in parallel.

[0182] like Figure 11As shown, three hybrid power modules are placed together to form a three-phase full-bridge hybrid module. For example, the three hybrid power modules can be connected on the same heat sink 6.

[0183] This application also provides a power conversion device, including at least one of the above-described hybrid power modules.

[0184] This application also provides a vehicle including the aforementioned power conversion device.

[0185] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A hybrid power module, characterized by, The hybrid power module comprises: a substrate (20); a first direct current connection layer (21) and an alternating current connection layer (22) located on the substrate (20), wherein the alternating current connection layer (22) comprises a first alternating current connection layer (221) and a second alternating current connection layer (222) which are separately arranged on both sides of the first direct current connection layer (21); an upper bridge chip set (31) arranged on the first direct current connection layer (21), wherein the upper bridge chip set (31) comprises a first silicon-based chip set (321), and the first silicon-based chip set (321) comprises a plurality of silicon-based power chips (12) and a plurality of diode chips (13), and the silicon-based power chips (12) and the diode chips (13) are one-to-one corresponding and connected in parallel; a lower bridge chip set (32), wherein a part of chips of the lower bridge chip set (32) are arranged on the first alternating current connection layer (221), and another part of chips are arranged on the second alternating current connection layer (222), and the lower bridge chip set (32) comprises a second silicon-based chip set (322), and the second silicon-based chip set (322) comprises a plurality of silicon-based power chips (12) and a plurality of diode chips (13), and the silicon-based power chips (12) and the diode chips (13) are one-to-one corresponding and connected in parallel; the chips in the upper bridge chip set (31) are electrically connected to the alternating current connection layer (22).

2. The hybrid power module of claim 1, wherein, The first direct current connection layer (21) is arranged between the first alternating current connection layer (221) and the second alternating current connection layer (222), and the first alternating current connection layer (221) and the second alternating current connection layer (222) are electrically connected through leads or terminals.

3. The hybrid power module of claim 1, wherein, The lower bridge chip set (32) further comprises a second wide bandgap chip set (312), and the chips in the upper bridge chip set (31) are electrically connected to the first alternating current connection layer (221), and the second wide bandgap chip set (312) is arranged on the first alternating current connection layer (221).

4. The hybrid power module of claim 3, wherein, The second silicon-based chip set (322) is arranged on the second alternating current connection layer (222).

5. The hybrid power module of claim 4, wherein, The upper bridge chip set (31) further comprises a first wide bandgap chip set (311), and the first wide bandgap chip set (311) and the second wide bandgap chip set (312) are arranged along a first direction, and the first wide bandgap chip set (311) and the second wide bandgap chip set (312) each comprise a plurality of wide bandgap power chips (11) arranged along a second direction.

6. The hybrid power module of claim 5, wherein, The second wide bandgap chip set (312) and the wide bandgap power chips in the first wide bandgap chip set (311) are one-to-one corresponding and connected in series.

7. The hybrid power module of claim 5, wherein, The silicon-based power chips (12) in the first silicon-based chip set (321) are one-to-one corresponding and connected in series with the silicon-based power chips (12) in the second silicon-based chip set (322).

8. The hybrid power module of claim 5, wherein, The first alternating current connection layer (221) comprises a first alternating current connection end (431), and the current path length between each wide bandgap power chip (11) in the first wide bandgap chip set (311) and the first alternating current connection end (431) is the same.

9. The hybrid power module of claim 5, wherein, The hybrid power module further comprises a second DC connection layer (23), and the second wide bandgap chip set (312) is electrically connected to the second DC connection layer (23).

10. The hybrid power module of claim 9, wherein, The hybrid power module comprises a second DC connection end (42) on the second DC connection layer (23), and a current path length between each wide bandgap power chip (11) in the second wide bandgap chip set (312) and the second DC connection end (42) is the same.

11. The hybrid power module of claim 1, wherein, The upper bridge chip set comprises: A first silicon-based chip set (321) and a first wide bandgap chip set (311) are arranged in a first direction on the first DC connection layer (21).

12. The hybrid power module of claim 4, wherein, The lower bridge chip set further comprises: A second silicon-based chip set (322) and the second wide bandgap chip set (312) are arranged in a first direction.

13. The hybrid power module of claim 10, wherein, The second DC connection end (42) is arranged close to the second wide bandgap chip set (312) on the second DC connection layer (23).

14. The hybrid power module of claim 9, wherein, The second DC connection layer (23) comprises a first DC negative connection layer (231) and a second DC negative connection layer (232), and the first DC negative connection layer (231) and the second DC negative connection layer (232) are connected.

15. The hybrid power module of claim 14, wherein, The first AC connection layer (221), the first DC connection layer (21) and the second AC connection layer (222) are arranged between the first DC negative connection layer (231) and the second DC negative connection layer (232).

16. The hybrid power module of claim 15, wherein, The first AC connection layer (221) is arranged close to the first DC negative connection layer (231) in a first direction, and the second AC connection layer (222) is arranged close to the second DC negative connection layer (232) in the first direction.

17. The hybrid power module of claim 15, wherein, The first DC negative connection layer (231) and the second DC negative connection layer (232) enclose the first AC connection layer (221), the first DC connection layer (21) and the second AC connection layer (222).

18. The hybrid power module of claim 15, wherein, The second DC negative connection layer (232) is at least partially arranged close to the first DC connection layer (21).

19. The hybrid power module of claim 18, wherein, The current direction of the second DC negative connection layer (232) is opposite to the current direction of the first DC connection layer (21).

20. The hybrid power module of claim 7, wherein, The second AC connection layer (222) comprises a second AC connection end (432), and a chip of the first silicon-based chip set (321) is connected to the second AC connection end (432).

21. The hybrid power module of claim 7, wherein, The second AC connection end (432) is arranged close to the first silicon-based chip set (321) on the second AC connection layer (222).

22. The hybrid power module of claim 14, wherein, The hybrid power module comprises two first DC terminals (41), and the two first DC terminals (41) are respectively arranged on the first DC negative connection layer (231) and the second DC negative connection layer (232).

23. The hybrid power module of claim 5, wherein, The arrangement mode of the plurality of wide bandgap power chips (11) comprises at least one of the following: Each wide bandgap power chip (11) is flush in a second direction; Two adjacent wide bandgap power chips (11) are staggered in a first direction; The first direction and the second direction are two directions perpendicular to each other in a plane.

24. The hybrid power module of claim 1, wherein, Silicon-based chip set Comprise: The arrangement mode of the plurality of silicon-based power chips (12) and the plurality of diode chips (13) comprises at least one of the following: The first chip combination, the second chip combination and the third chip combination are arranged in the second direction in turn, the first chip combination comprises at least one silicon-based power chip (12) arranged in the second direction in turn, the second chip combination comprises at least one diode chip (13) arranged in the second direction in turn, and the third chip combination comprises at least one silicon-based power chip (12) arranged in the second direction in turn; The fourth chip combination, the fifth chip combination and the sixth chip combination are arranged in the second direction in turn, the fourth chip combination comprises at least one diode chip (13) arranged in the second direction in turn, the fifth chip combination comprises at least one silicon-based power chip (12) arranged in the second direction in turn, and the sixth chip combination comprises at least one diode chip (13) arranged in the second direction in turn; The plurality of silicon-based power chips (12) and the plurality of diode chips (13) are arranged in the second direction in cross.

25. The hybrid power module of claim 5, wherein, The hybrid power module comprises: The first gate drive layer (241) and the first source drive layer (242) on the substrate (20); The gate of each wide bandgap power chip (11) in the first wide bandgap chip group (311) is connected to the first gate drive layer (241), and the source of each wide bandgap power chip (11) in the first wide bandgap chip group (311) is connected to the first source drive layer (242).

26. The hybrid power module of claim 7, wherein, The hybrid power module comprises: The second gate drive layer (261) and the first emitter drive layer (262) on the substrate (20); the gate of each silicon-based power chip (12) in the first silicon-based chip group (321) is connected to the second gate drive layer (261), and the emitter of each silicon-based power chip (12) in the first silicon-based chip group (321) is connected to the first emitter drive layer (262).

27. The hybrid power module of claim 5, wherein, The hybrid power module comprises: The third gate drive layer (251), the second source drive layer (252), and the second emitter drive layer (253) on the substrate (20); The gate of each wide bandgap power chip (11) in the second wide bandgap chip group (312) is connected to the third gate drive layer (251), and the source of each wide bandgap power chip (11) in the second wide bandgap chip group (312) is connected to the second source drive layer (252).

28. The hybrid power module of claim 7, wherein, The hybrid power module comprises: A fourth gate drive layer (271) and a second emitter drive layer (272) are located on the substrate (20); a gate of each of the silicon-based power chips (12) in the second silicon-based chip set (322) is connected to the fourth gate drive layer (271), and an emitter of each of the silicon-based power chips (12) in the second silicon-based chip set (322) is connected to the second emitter drive layer (272).

29. The hybrid power module of claim 25, wherein, The hybrid power module comprises: A first gate drive terminal (441) is arranged in the first gate drive layer (241), and a first source drive terminal (442) is arranged in the first source drive layer (242).

30. The hybrid power module of claim 26, wherein, The hybrid power module comprises: A second gate drive terminal (461) is arranged in the second gate drive layer (261), and a first emitter drive terminal (462) is arranged in the first emitter drive layer (262).

31. The hybrid power module of claim 27, wherein, The hybrid power module comprises: A third gate drive terminal (451) is arranged in the third gate drive layer (251), and a second source drive terminal (452) is arranged in the second source drive layer (252).

32. The hybrid power module of claim 28, wherein, The hybrid power module comprises: A fourth gate drive terminal (471) is arranged in the fourth gate drive layer (271), and a second emitter drive terminal (472) is arranged in the second emitter drive layer (272).

33. The hybrid power module of claim 9, wherein, At least one of the first direct current connection layer (21), the second direct current connection layer (23), and the alternating current connection layer (22) is a copper layer.

34. The hybrid power module of claim 5, wherein, The wide bandgap power chip comprises a silicon carbide metal oxide semiconductor field effect transistor, or a gallium nitride high electron mobility transistor.

35. The hybrid power module of claim 1, wherein, The silicon-based power chip comprises a silicon insulated gate bipolar transistor, or a silicon metal oxide semiconductor field effect transistor. The diode chip comprises a silicon fast recovery diode chip, or a silicon carbide Schottky diode chip.

36. A multiphase full-bridge hybrid module characterized by, The hybrid power module comprises at least two hybrid power modules according to any one of claims 1-35.

37. A power conversion device, characterized by The hybrid power module comprises at least one hybrid power module according to any one of claims 1-35.

38. A vehicle characterized by The power conversion device comprises the hybrid power module according to claim 37.

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